JPH0438022B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data storage device that sequentially stores digital data of each channel of a multi-channel processed in a digital device in a memory.

BACKGROUND ART As a conventional data storage device of this kind, there is one shown in FIG. 1 that stores multi-channel serial digital data reproduced from a magnetic tape, magnetic disk, etc. in a RAM, which is a memory.

This device amplifies signals reproduced by reproduction heads 1a to 1n corresponding to the number of channels (generally one head has a reproduction gap equal to the number of channels) through reproduction amplifiers 2a to 2n, respectively. The demodulation circuits 3a to 3n demodulate the demodulated data, each address control circuit 4a to 4n converts the demodulated data into parallel data for each word, and generates an address for each channel.The reproduced data of each channel is transferred to a RAM 5a dedicated to each channel. ~
5n are stored sequentially.

By the way, when reproducing data from a magnetic tape or the like using a multi-head, the reproducing heads 1a to 1
If the gap position of n is shifted or the tape in motion fluctuates, "skew" occurs in which the playback data of each channel is shifted in time, but according to the device shown in Figure 1, Even in such cases, RAM for each channel corresponds, and each RAM
There is no problem because the data is stored independently.

However, in such conventional multi-channel data storage devices, as the number of channels increases, a correspondingly large number of RAMs and their control circuits are required, which is extremely uneconomical and increases costs.

Furthermore, as seen in Japanese Patent Application Laid-Open No. 56-120915, for example, multiple channels of input data are sequentially output in a time-division manner using a multiplexer, and sent to one memory (RAM) via a common data bus system. There is also a data storage device that inputs data and sequentially stores the data by addressing the area corresponding to each channel using the output of an address counter.

If such a data storage device is used, even if the number of channels increases, only one RAM and its control circuit can be used in common, which is economical, but the data storage order of each channel by time division is predetermined. Therefore, if the data of each channel is shifted in time and the order of occurrence is changed due to the occurrence of "skew" as described above, each channel's data is stored in the area corresponding to each channel in RAM. There was a problem that data could no longer be stored in order.

Purpose This invention was made by focusing on such a problem, and it is possible to store the input data of each channel in one common memory regardless of the number of channels, and also to avoid problems even if skew occurs. The purpose of the present invention is to provide a multi-channel data storage device.

Configuration Therefore, the data storage device according to the present invention has the following features:
Each channel is provided with a flip-flop circuit (hereinafter referred to as "FF circuit") that is set when digital data is input, and the output of each FF circuit is used as input, and the FF circuits are set in the order in which they were set. or an encoder that converts the address signal into a predetermined bit address signal for each channel according to a predetermined priority order, a decoder that receives the address signal and generates a channel selection signal for storing the corresponding data; a delay circuit that slightly delays the channel selection signal and uses it as a reset signal for the FF circuit of the corresponding channel;
a data selection circuit that selects the digital data input of each channel using the channel selection signal and inputs the selected data to the memory via a common data bus; The data of each channel inputted through the data selection circuit is sequentially stored in one memory having a data storage area for the data selection circuit by specifying the area by the address signal from the encoder.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2 to 4.

FIG. 2 is a block diagram showing one embodiment of the present invention, in which parts corresponding to those in FIG. 1 are given the same reference numerals, and their explanation will be omitted.

This embodiment shows an example in which data of 16 channels from 0ch to 15ch is reproduced and stored in memory. Each circuit dedicated to 0ch is marked with a, and each circuit dedicated to 15ch is Each circuit is shown with a suffix "n", and circuits dedicated to each of channels 1 to 14 are not shown.

6a to 6n are address control circuits for each channel.
As shown in FIG. 3, each of them is composed of a serial/parallel conversion circuit 61, a latch circuit 62, and an 8-bit counter 63.

7a to 7n are flip-flop circuits (FF circuits) that are provided for each channel and are set when 8-bit serial data is completed as 8-bit parallel data, and 8 inputs the output of each FF circuit, and An encoder that converts into a 4-bit address signal for each channel according to the order in which the circuits are set or when multiple FF circuits are set at the same time, according to a predetermined priority order (for example, ascending order of channel number). , 9 is a decoder which receives the address signal and generates a channel selection signal to store the data of the corresponding channel.

10 is one memory for data storage
The RAM has a data storage area for each channel (16 channels in this example).

11a to 11n are 3-state buffers inserted in the data output lines from the address control circuits 6a to 6n of each channel, respectively, and are connected to the decoder 9.
Each buffer 11a serves as a switch circuit whose opening/closing is controlled by a channel selection signal from
The output side of ~11n is connected by a common data bus.
Data is input to the RAM 10, and these constitute a data selection circuit.

12a to 12n are delay circuits provided between the output terminal corresponding to each channel of the decoder 9 and the reset terminal of the FF circuits 7a to 7n for each channel. To save time, the reset signal for the corresponding FF circuit is delayed slightly.

Next, the operation of this embodiment will be explained.

The reproduction data of each channel demodulated by the demodulation circuits 3a to 3n is serial digital data as shown in FIG. The data is inputted to the /parallel conversion circuit 61, where it is converted every 8 bits into parallel digital data as shown in FIG. 4D, and latched into the latch circuit 62 at the timing of the pulse p shown in FIG.

This pulse p is generated when 8 bits of data are complete, and is generated by counting the serial data reference clock kc shown in FIG. 4B obtained during demodulation by 8 bits by the counter 63. be.

When this pulse p is input to, for example, the FF circuit 7a, the FF circuit 7a is set and its output becomes "H" as shown in FIG. 4E.

When the input from the FF circuit 7a first becomes "H", the encoder 8 converts it into a 4-bit address signal "0000" specifying 0ch and outputs it to the RAM 10 and decoder 9.

When the decoder 9 receives this address signal "0000", it generates a channel selection signal indicating 0ch (sets only the output terminal 0 to "H"). As a result, the 3-state buffer 11a for 0ch is opened, and the 0ch data latched in the latch circuit 62 of the address control circuit 6a is input to the RAM 10.
It is stored in the area for 0ch designated by the address signal "0000" from the encoder 8.

The channel selection signal from the decoder 9 is also input to the delay circuits 12a to 12n, but at this time
Only the input of the delay circuit 12a of channel 0 becomes "H", the output is delayed and becomes "H", and the RAM
After data writing is completed, the FF circuit 7a is reset.

At this time, if only one of the other FF circuits 7b to 7n is set, the encoder 8
outputs the address signal for the channel of that FF circuit next, but if multiple FF circuits are set, the address signal for the channel with the highest priority among them is output next.

In this way, each time the encoder 8 outputs an address signal, the decoder generates a data storage signal for the corresponding channel, and stores the data for that channel in the area specified by the address signal from the encoder 8 in the RAM 10. Then, by resetting the FF circuit of that channel, the encoder 8 is caused to generate an address signal for the next channel.

By repeating such operations, all 16 channels of data are addressed and distributed and stored in each area of the RAM 10 during the period T of the pulse p shown in FIG. 4A.

Please note that the number of channels is not limited to 16 channels.
If you have a memory capacity of at most 10 RAM, you can store the playback data of all channels in one RAM.

Effects As described above with respect to the embodiments, the data storage device according to the present invention can store each multi-channel digital data input in one memory by specifying the address for each channel without being affected by skew. , even if the number of channels increases, the cost does not increase significantly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional multi-channel data storage device, FIG. 2 is a block diagram of a data storage device showing an embodiment of the present invention, and FIG. 3 is an address control circuit thereof. FIG. 4 is a time chart for explaining the operation of this embodiment. 1a-1n... Reproducing head, 2a-2n... Reproducing amplifier, 3a-3n... Demodulating circuit, 6a-6n... Address control circuit, 7a-7n... Flip-flop circuit, 8... Encoder, 9... Decoder, 10...
RAM (memory), 11a to 11n... 3-state buffer, 12a to 12n... delay circuit.

Claims (1)

[Scope of Claims] 1. In a data storage device that sequentially stores digital data input from each channel of a multi-channel in a memory, a flip-flop circuit is provided for each channel to be set when the digital data is input, and The output of each flip-flop circuit is inputted, and the output for each channel is input in the order in which each flip-flop circuit is set, or in accordance with a predetermined priority when multiple flip-flop circuits are set at the same time. an encoder that converts the address signal into a predetermined bit address signal, inputting the address signal from the encoder,
a decoder that generates a channel selection signal for storing corresponding data; and a delay circuit that slightly delays the channel selection signal generated by the decoder and uses it as a reset signal for the flip-flop circuit of the corresponding channel. , a data selection circuit for selecting the digital data input of each channel by the channel selection signal and inputting it to the memory via a common data bus, the memory having a data storage area for each channel. One memory, each time the decoder generates a channel selection signal, sequentially stores the data of each channel input through the data selection circuit in an area of the memory designated by the address signal from the encoder. A data storage device characterized by: