JPS6149741B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PCM (Pulse Code Modulation) reproducing device, and more specifically, a PCM (Pulse Code Modulation) reproducing device that automatically determines whether an M channel signal or an N channel signal is recorded on a recording medium. The present invention relates to a PCM playback device equipped with a channel detection circuit.

2. Description of the Related Art Devices for recording and reproducing PCM audio signals using a general-purpose VTR (video tape recorder) are already known. If this type of device is configured to record and reproduce 4-channel signals, if it is used to record and reproduce 2-channel signals, empty channels will be generated, which will be uneconomical. Therefore, double recording of 2 channel signals on an empty channel (however, since PCM recording is generally double recording, if 4 channel signals are double recorded, quadruple recording) is performed to avoid problems such as dropouts. It is possible to reduce errors. By the way, 4
When playing back using a recording medium on which channel signals are recorded, and when playing back using a recording medium on which channel signals are recorded,
The signal processing method in the reproducing device must be changed depending on the case of reproducing using a recording medium with overlapping recording. In such cases, it is possible to determine whether the medium is a 4-channel recording medium or a 2-channel recording medium and manually set the playback device to a 4-channel state or a 2-channel state, but it is difficult to operate. Become. Also, although I mentioned the cases of 4 channels and 2 channels, 8 channels,
Similar problems exist with channels such as 16.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a PCM playback device that is easy to handle despite being capable of playing back in various forms.

To achieve the above object, the present invention is capable of reproducing M channels using a recording medium on which signals of M channels (where M is an integer of 2 or more) are recorded a plurality of times. In a PCM playback device that is also capable of N-channel playback using a recording medium that has been made into a recording state similar to M-channel recording by recording N-channel signals of 2 channels or less multiple times, Whether the M-channel signal is being reproduced based on the M-channel recording medium or the N-channel signal is being reproduced based on the N-channel recording medium is determined by checking signals at multiple locations in the reproduced signal. A channel detection circuit detects by comparison, and compensates for errors in the reproduced signal, and the error compensation operation is switched between when reproducing the M channel signal and when reproducing the N channel signal. and an error compensation circuit configured to automatically switch the compensation operation in response to an output of the channel detection circuit. .

In the above invention, by comparing signals at a plurality of locations, it is detected whether it is M-channel playback or N-channel playback, and the compensation operation of the error compensation circuit is automatically switched to match M-channel playback or N-channel playback. Therefore, it is possible to provide a playback device that is easy to handle.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1 showing a recording section of a PCM recording and reproducing apparatus using a VTR according to the present invention, first, second,
First, second, third, and fourth input terminals 1a, 1b, 1 corresponding to the third and fourth channels
Terminals c and 1d are terminals into which analog signals such as audio signals are input. 2 is a sample hold circuit, which has first, second, third, and fourth input terminals 1a, 1 to process signals of 4 channels.
1st, 2nd, 3rd, connected to b, 1c, 1d,
and fourth sample and hold circuits 2a, 2b, 2
c, 2d. 3 is an analog-to-digital converter, that is, an A-D converter, and this part also includes first, second, third, and fourth sample-and-hold circuits 2a, 2 to process signals of 4 channels.
the first, second, third, connected to b, 2c, 2d;
and fourth A-D converters 3a, 3b, 3c, 3d
has. The data memory 4 at the output stage of the A-D converter 3 is composed of, for example, a scratch pad memory, and sequentially stores the output of the A-D converter 3 based on address designation by the write address circuit 5. The memory contents are sent out in accordance with address designation by the read address circuit 6. The clock signal generation circuit 7 provides clock signals to the sample hold circuit 2, the A/D converter 3, the write address circuit 5, the read address circuit 6, and the synchronization signal circuit 8.

The device has a readout switch 9 to process both 4-channel signals and 2-channel signals. When the changeover switch 9 is open, the read address circuit 6 performs a 4-channel read operation, and when it is closed, the read address circuit 6 performs a 2-channel read operation. 10 is a parallel-serial converter,
It converts parallel digital signals output from the memory 4 into serial digital signals. Reference numeral 11 is a parity bit generator which forms a parity bit with the output of the memory 4 and sends it to the parallel-to-serial converter 10 to add the parity bit. The synchronization signal circuit 8 generates a large section synchronization signal (hereinafter referred to as a vertical synchronization signal) and a small section synchronization signal (hereinafter referred to as a frame synchronization signal) that are generated every 1/60 seconds.
It is something that generates. The frame synchronization signal is generated every 112 bits, for example, and is used for extracting data, and is generated like a horizontal synchronization signal in a VTR. Serial digital signal output from parallel-serial converter 10 and synchronization signal circuit 8
The synchronization signals outputted from the sync signal are combined by an adder 12 to form a composite PCM signal with a three-value configuration consisting of, for example, "1", "0", and "-1". This composite PCM signal is
FM recording is performed on a magnetic tape 16 by a magnetic head 15 via an FM modulation circuit 13 and a recording amplifier circuit 14. That is, an FM signal formed by frequency modulating the composite PCM signal is recorded on the magnetic tape 16 by, for example, a VTR.

When recording four-channel signals with the apparatus shown in FIG. 1, the first, second, third, and fourth input terminals 1a, 1b, 1c, and 1d are The fourth channel signals are respectively inputted, and the sample and hold circuit 2 samples and holds the respective channel signals. Four channels of signals sampled and held at a predetermined sampling period are converted into four channels of digital signals by an AD converter 3, and written into a memory 4 in synchronization with a write clock signal. The readout of digital signals from the memory 4 is based on the readout clock signal given from the readout address circuit 6, and the data A ₁ of the first channel, the data B 1 of the second channel, and the data B ₁ of the third channel shown in FIG. data
C ₁ and data D ₁ of the fourth channel. Since the frequency of the read clock signal applied from the read address circuit 6 is set higher than the frequency of the write clock signal, it is possible to read the same data twice in the same time as the time required to write the data. . Therefore,
After the first reading is completed in the period t ₁ to _{t 2} in FIG. 4, the same data is read again in the period t ₂ to _{t 3} , and the data of A' ₁ , B' ₁ , C' ₁ , D' ₁ is Obtain signals for double recording. A dash is attached to the data for the period t ₂ to _{t 3} , but if there is no error, A ₁ = A′ ₁ , B ₁ =
B′ ₁ , C ₁ =C′ ₁ , D ₁ =D′ ₁ . After double reading of the first data is completed, the next data is read from t ₄ to _{t 5}
and during the period t ₅ to _{t 6} to obtain data A ₂ , B ₂ , C ₂ , D ₂ , A′ ₂ , B′ ₂ , C′ ₂ , D′ ₂ .

The signal read from the memory 4 is converted into a serial digital signal by a parallel-to-serial converter 10. The output of the memory 4 is also applied to a parity bit generator 11, where a parity bit is formed and applied to the parallel-to-serial converter 10. Therefore, from the parallel-to-serial converter 10, a serial digital signal with a parity bit added is [010110...
…] is output. A frame synchronization signal F and a vertical synchronization signal V are added to the serial digital signal output in the order shown in FIG. is recorded on FM. This makes it possible to obtain a recording medium on which four channel signals are recorded in duplicate.

When recording a two-channel signal with the apparatus shown in FIG. 1, the changeover switch 9 is closed to cause the read address circuit 6 to perform a two-channel read operation.
For example, the first channel signal is input to the first input terminal 1a, and the second input terminal 1b
input the second channel signal. As a result, the first and second channel signals are sampled and held and A/D converted, and then written into the memory 4, respectively. Since the read address circuit 6 is set to read the same data four times, the first channel data _{A 1} and the _second channel data B ₁ and After the data is read out, the same data is read out again during the period from t ₂ to _{t 3} to obtain data A' ₁ and B' ₁ . Furthermore, the same data is read out during the _t3 - _t4 period and the _t4 - _t5 period. Assuming that there are no errors in the repeatedly read data, A ₁ = A′ ₁ = A″ ₁ = A ₁ , B ₁ =
B′ ₁ =B″ ₁ =B ₁ , C ₁ =C″ ₁ =C ₁ , D ₁ =D′ ₁
=D″ ₁ =D _1.The read data is 1
As in the case of channel recording, the magnetic tape 16 is arranged between frame signals F as shown in FIG.
will be recorded four times.

Sequentially transmitted data array and magnetic tape 1
6, the first recording area on the magnetic tape 16 is A, the second recording area is B, the third recording area is C, and the fourth recording area is D.
Then, in the case of 4-channel recording, the first channel data (signal) is stored in the first recording area A.
A ₁ , second channel data in second recording area B
B ₁ , third channel data in third recording area C
C ₁ , 4th channel data in the 4th recording area D
D ₁ , is recorded. In the case of two-channel recording, the first channel data A ₁ is stored in the first recording area A, the second channel data B ₁ is stored in the second recording area B, and the first channel data A ₁ is stored in the third recording area C. The double recording data A' ₁ of the second channel data B 1 and the double recording data B' of the second channel data B ₁ are recorded in the fourth recording area D, respectively.

In FIG. 2 showing the reproduction system, the magnetic head 16
magnetic tape 16 with the same or different magnetic head 21
If a composite PCM signal recorded on FM is played back using a VTR, for example, a 5.4MHz frequency signal corresponding to "1" of the PCM signal can be obtained, and
A 4.6MHz frequency signal is obtained in response to the signal "0", and a 3.8MHz signal is obtained in response to the synchronization signal. The FM wave detected by the magnetic head 21 is amplified by a regenerative amplifier circuit 22 and then demodulated by an FM demodulation circuit 23 to become, for example, a ternary composite PCM signal. The dropout detection circuit 24 is connected to the front stage of the FM demodulation circuit 23, and is
Detects a drop in the level of FM waves as a dropout. The data separated by the signal separation circuit 25 connected to the FM demodulation circuit 23 is sent to the serial-parallel converter 2.
6, where it becomes a parallel digital signal.
Further, the vertical synchronization signal and frame synchronization signal separated by the synchronization signal separation circuit 27 connected to the FM demodulation circuit 23 are sent to the write address circuit 29 of the memory 28 and the 4-channel and 2-channel detection circuit 30.

The parity check circuit 31 performs a parity check on the data output from the serial-parallel converter 26, and sends out an output corresponding to the presence or absence of a parity error. That is, for example, a low level output is generated when there is no parity error, and a high level output is generated when there is a parity error. The dropout detection circuit 24 generates, for example, a high level output when a dropout is detected, and generates, for example, a low level output when a dropout is not detected. The output of the parity check circuit 31 and the output of the dropout circuit 24 are ORed respectively.
Since it is input to the circuit 32, when either a parity error or a dropout occurs,
An error output is generated from the OR circuit 32, and the data is not written to the memory 29, or the data is not written to the memory 29.
It is not read from 8. That is, data in which a parity error or dropout occurs is not used.

The double recording comparison circuit 33 compares the first recorded data and the second recorded data, and if they do not match, a check bit indicating an error is added. For example, data _A1 and data _A'1 in FIG. 4 are compared, and if they do not match, a check bit is added. Also, in Figure 5, A ₁ and
A ₁ '' is compared, and if they do not match, a check bit is added. In addition, in Fig. 5, A' ₁ and A ₁
are compared, and if they do not match, a check bit is added. However, in this embodiment, when there is an output from the OR circuit 32 for either the first data A ₁ or the second data A' ₁ of double recording, the output of the double recording comparison circuit 33 is A check bit is not added at the check bit, and the data for which no error is detected by the OR circuit 32 is output without the check bit. Also, the first double record
When the output of the OR circuit 32 is present for both the first data _A1 and the second data _A'1 , a check bit is added regardless of the output of the double recording comparator circuit 33. Reading of data from the memory 28 is controlled by a read address circuit 37.

The error compensation circuit 34 provided at the output stage of the memory 28 is a circuit that, when a data error occurs, inserts data close to actual data in place of the error data by interpolation or previous value hold to compensate for the error. The error compensated data is sent to the D-A converter 3.
5, where it is separated into four channels or two channels, forming independent first, second, third, and fourth channel digital signals in the case of fourth channel reproduction; , third and fourth DA converters 35a, 35b, 35c,
35d, it is converted into an analog signal. Therefore,
first, second, third, and fourth output terminals 36a,
Analog outputs of the first, second, third, and fourth channels are obtained from 36b, 36c, and 36d. That is, the input terminals 1a, 1b, 1c,
Outputs equivalent to the analog signal input to 1d are obtained from output terminals 36a, 36b, 36c, and 36d. That is, the first DA converter 35a converts the data A ₁ , A ₂ ... A _o shown in FIG. 6A, and the second DA converter 35b converts the data A 1 , A 2 . Data B ₁ , B ₂ . . . B _o is D-A converted, and the third
In the D-A converter 35c, the data shown in FIG.
C ₁ , C ₂ ...C _o is converted to DA, and the fourth DA is converted
The converter 35d receives data D ₁ and D ₂ shown in FIG. 6D.
...D _o is converted to DA. Then, four channels of analog signals obtained by DA conversion are sent to output terminals 36a, 36b, 36c, and 36d.

In the case of two-channel reproduction, the data A ₁ , A _{2 .} . . A _o of FIG.
are subjected to DA conversion, and the data B ₁ , B _{2 .} . . B _o in FIG. The two-channel analog signals obtained by this D-A conversion are output terminals 36a and 36b.
sent to.

In the device shown in FIG.
4 must perform different operations during 4-channel playback and 2-channel playback. Therefore, this device is provided with 4-channel and 2-channel detection circuits 30. This channel detection circuit 30 detects the first channel detected from the first recording area.
and a third signal read from the third recording area, and a comparison between the second signal read from the second recording area and the fourth signal read from the fourth recording area. The comparison output indicating a mismatch is used as a 4-channel detection signal, and the signal indicating a match is sent as a 2-channel detection signal.

FIG. 3 shows channel detection circuit 30 and error compensation circuit 34 in more detail. The channel detection circuit 30 is provided with a first memory 37 for channel detection and a second memory 38 for channel detection. The first memory 37 is controlled by the write address circuit 39 to store the 11th data CH1 read from the first recording area A provided every 4 data and the second data CH1 read from the second recording area B. Data CH2 is stored therein, and this stored data is supplied to the comparator 41 under the control of the read address circuit 40. The second memory 38 also stores third data read from the third recording area C under the control of the write address circuit 42.
The fourth data read from CH3 and fourth recording area D.
This stored data is supplied to the comparator 41 under the control of the read address circuit 43. The comparator 41 compares the first data CH1 and the third data CH3 and the second data CH2 and the fourth data CH4, and outputs a high level comparison when CH1=CH3 and CH2=C2. occurs and counter 4
4 inputs. The channel discrimination counter 44 and the flip-flop 45 at the next stage receive the vertical synchronizing signal from the synchronizing signal separation circuit 27, the counter 44 is cleared by this vertical synchronizing signal, and the flip-flop 45 is reset by this vertical synchronizing signal. Therefore, the counter 44 counts the coincidence outputs of the comparator 41 occurring between the vertical synchronization signals. The comparator 41 compares the vertical synchronizing signals, for example, 1536 times. The counter 44 has a predetermined count value M
For example, when counting larger than 1024,
Generates 2-channel detection output. That is, when the count number n becomes larger than M, a high level output is generated as the 2-channel detection output. Further, when the count of the counter 44 does not reach 1024, the output of the counter 44 is kept at a low level, and this becomes the 4-channel detection output. When playing 4 channels, in principle CH1 = CH3 and CH2 = CH4
do not become. This is because different data is recorded in the first recording area A and the third recording area C, and the second recording area
This is because different data is recorded in the recording area B and the fourth recording area D. However, even in the case of 4-channel playback, for example, A ₁ = C ₁ , B ₁
= D ₁ , so a threshold value is provided to clearly distinguish between 2 channels and 4 channels. In addition, in the case of 2-channel playback, unless an error occurs, CH1=CH3, CH2=CH
4. However, since there are cases where the condition is not satisfied due to an error, the threshold value has meaning in this case as well. When the 2-channel detection output is obtained from the counter 44, the flip-flop 45 is reset, and the output of the flip-flop 45 also enters the 2-channel detection state. This puts the control circuit 46 in a state where it performs error compensation on two channels. Further, when the counter 44 generates a 4-channel detection output, the flip-flop 45 is always in a reset state, and the control circuit 46 is in a state to compensate for errors in the 4 channels. Incidentally, such 4-channel and 2-channel detection is performed in units of vertical synchronization signals.

The error compensation circuit 34 has a first memory 47 and a second memory 48 for error compensation. Data including check bits obtained from the data memory 28 is first written into the first memory 47 under the control of the write address circuit 49, and then read out under the control of the read address circuit 50.
The signal is sent to a second memory 48 and a signal selection circuit 52 consisting of an arithmetic circuit 51 and a multiplexer or scanner. The second memory 48 is the write address circuit 5
3 to store the output of the first memory 47,
Under the control of the read address circuit 54, stored data is supplied to the arithmetic circuit 51 and the signal selection circuit 52. In addition, the first memory 47 and the control circuit 46
A first check bit detection line 55 is connected between the second memory 48 and the control circuit 4.
A second check bit detection line 56 between
is connected. Therefore, the control circuit 4
6 detects whether a check bit is attached to the data output from the first memory 47 and the second memory 48.

Next, error compensation in the case of 4-channel reproduction and 2-channel reproduction will be described in more detail with reference to the flowcharts of FIGS. 8 and 9. In Figures 8 and 9, CH represents data, and X represents 1 to
4, indicating that the data corresponds to the first, second, third, and fourth recording areas A, B, C, and D. Further, n indicates a frame synchronization signal section. First, in the case of 4-channel playback, first, at step 61 in FIG. 8, the first memory 47
Read data CHX _o from. Next, in step 62, the control circuit 46 determines whether a check bit is attached to the data CHX _o . If no check bit is attached, the read data CHX _o of the first memory 61 is read out as shown in step 63.
The control circuit 46 controls the write address circuit 53 to write into the second memory 48,
Further, the selection control circuit 57 is controlled by the output of the control circuit 46, and the selection control circuit 57 is further controlled by the selection circuit 52 to select the output data CHX _o of the first memory 47 as shown in step 64, Output this data CHX _o . That is, by connecting the first memory 47 to the DA converter 35, data without any compensation is output.

If a check bit is detected in step 62, the next data CHX _o+1 is read from the first memory 65 as shown in step 65. Then, in step 66, it is determined whether a check bit is attached to this data CHX _o+1 . As a result, if you find that the check bit is not attached,
Read address circuit 5 with control circuit 46
4 to control the second memory 4 as shown in step 67.
Read data CHX _o-1 from 8. This results in
The arithmetic circuit 51 receives data from the first memory 47.
CHX _o+1 is given and data CHX _o-1 is given from the second memory 48, where CHX _o+1 +CHX _o-1
An interpolation calculation of /2 is performed. That is, the average value of the data immediately before and after the dropout is calculated. Further, a signal for selecting the interpolation calculation output is generated from the selection control circuit 57, and the selection circuit 52
connects the arithmetic circuit 51 to the D/A converter 35, and the interpolation arithmetic output of step 68 becomes a signal for compensating for dropout.

If a check bit is detected in step 66, data is retrieved from second memory 48 as shown in step 69.
CHX _o-1 is read. The selection circuit 52 also connects the second memory 48 to the DA converter 35 at step 70 . Also, the control circuit 46 reads the address circuit 54 so as to hold CHX _o-1.
control. As a result, the dropout is compensated for by holding the data CHX _o-1 immediately before the dropout occurs.

Next, two-channel reproduction will be described with reference to the flowchart of FIG. First, in step 71, data CH1 _o (for example, A ₁ ) representing data in the first recording area A is read out from the first memory 47 . Next, in step 72, a check bit of data _CH1o is detected on line 55. If no check bit is attached to data _CH1o , it is output as is. That is, the first memory 47 is selected by the selection circuit 52.
is connected to the DA converter 35. When a check bit is detected in step 72, CH3 _o (for example, A' ₁ ) representing the data of the third recording area C is read out from the first memory 47 as shown in step 73. Next, as shown in step 74, the check bit of data _CH3o is determined. If no check bit is detected, the first memory 47 is connected to the DA converter 35 and data CH3 _o (for example, A' ₁ ) is output. That is, the data recorded in reserve is output.

If a check bit is detected in step 74, CH1 _o+1 is transferred from the first memory 47 as shown in step 75.
Read out. That is, the data immediately after the error data is read. Next, in step 76, the check bit of data CH1 _o+1 is determined. If there is no check bit, the second memory 4 is checked as shown in step 77.
Read data CH1 _o-1 from 8. That is, the data immediately before the error data is read. Thereafter, as shown in step 78, the arithmetic circuit 51 calculates the arithmetic output of CH1 _o+1 +CH1 _o-1 /2, connects the arithmetic circuit 51 to the D-A side converter 35, and performs error compensation using the interpolated arithmetic output. I do.

If a check bit is detected in step 76, data is retrieved from first memory 47, as shown in step 79.
Read CH3 _o+1 . Next, as shown in step 80, the check bit of data CH3 _o+1 is determined.
If no check bit is detected, the data is retrieved from second memory 48 as shown in step 77.
CH1 _o-1 is read out, and as shown in the next step 78, the arithmetic circuit 51 calculates CH3 _o+1 +CH1 _o-1 /2, and the arithmetic circuit 51 is connected to the D-A converter 35. The output is interpolated data.

When the check bit of data CH3 _o+1 is detected in step 80, data CH1 _o-1 is read from the second memory 48 as shown in step 81. That is, the data immediately before the error data is read. Then, as shown in step 82, the second memory 48 is connected to the DA converter 35, and error compensation is performed by holding data CH1 _o-1 .

As is clear from the above, this PCM recording and reproducing apparatus allows the channel detection circuit 30 to automatically detect whether 4-channel reproduction or 2-channel reproduction is being performed. Therefore, it is possible to provide a device that is easy to handle.

Further, since the playback device is automatically set to the 4-channel mode or the 2-channel mode based on the output of the channel detection circuit 30, it is possible to provide a device with good operability.

Furthermore, since the error compensation circuit 34 is controlled by the output of the channel detection circuit 30 to obtain both the error compensation state for 4-channel reproduction and the error compensation state for 2-channel reproduction, It is possible to perform optimal error compensation.

Furthermore, during two-channel recording/reproduction, data is recorded quadrupletly to compensate for dropouts, so high-precision recording/reproduction is possible.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-mentioned embodiment.
It is also deformable. For example, during two-channel recording, the first channel signal is input to the first and third input terminals 1a and 1c, the second channel signal is input to the second and fourth input terminals 1b and 1d, and the switch 9 is turned on. May be omitted. Further, the output of the channel detection circuit 30 may be used for channel switching or channel display other than the error compensation circuit 34. For example, a display may be connected to the channel detection circuit 30 to display whether the playback device is in a 4-channel playback state or a 2-channel playback state. Also, comparator 41
The configuration may be such that either one of CH1=CH3 and CH2=CH4 is detected. It is also applicable to recording and reproducing using recording media other than magnetic tape. Further, the present invention is not limited to the combination of 4 channels and 2 channels, but can also be applied to a combination of 8 channels and 4 channels, or a combination of 16 channels and 8 channels, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the recording section of a PCM recording and reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing the reproducing section, and FIG. 3 is the channel detection circuit and error compensation circuit of FIG. 2. FIG. 4 is a waveform diagram explanatory of the 4-channel recording signal and recording state, FIG. 5 is a waveform diagram explanatory of the 2-channel recording signal and recording state, and FIG. FIG. 7 is a waveform diagram that explains the reproduction output state of the two channels. FIG. 8 is a flowchart that explains the operation of the error compensation circuit in the reproduction of four channels. FIG. 9 is a flowchart for explaining the operation of the error compensation circuit in two-channel reproduction. In the symbols used in the drawings, 21 is a magnetic head, 23 is an FM demodulation circuit, 24 is a dropout detection circuit, 28 is a memory, 30 is a 4-channel and 2-channel detection circuit, 31 is a parity check circuit, 32 is an OR circuit, 33 is a double recording comparison circuit, 34 is an error compensation circuit, and 35 is a D-
It is an A converter.

Claims (1)

[Claims] 1. It is possible to reproduce M channels using a recording medium in which signals of M channels (where M is an integer of 2 or more) are recorded multiple times, and M/2
In a PCM playback device that is also capable of N-channel playback using a recording medium that has been made into a recording state similar to M-channel recording by recording an N-channel signal that is less than the M channel multiple times, M based on the recording medium of the channel
The signal of the channel is being regenerated or the N
a channel detection circuit that detects whether the N-channel signal is being reproduced based on the channel recording medium by comparing signals at multiple locations in the reproduced signal; and a circuit that compensates for errors in the reproduced signal. and is configured to switch the error compensation operation between when reproducing the M channel signal and when reproducing the N channel signal, and the switching of the compensation operation is automatically performed in response to the output of the channel detection circuit. 1. A PCM playback device comprising: an error compensation circuit configured to perform