JPS6135619B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal processing device used to arrange digital information signals in a different arrangement from the original arrangement. An object of the present invention is to make the device inexpensive and simple in structure by using a random access memory (hereinafter referred to as RAM) as a delay device without using a shift register. Furthermore, the RAM address control can be easily performed.

When it is necessary to delay n bit sequences H ₁ , H ₂ , H ₃ , . . . H _o by d, 2d, 3d, . , 2d, . . _. to obtain delayed bit sequences H _{1 -d} , H _2-2d , . . . H _o-od using shift registers SR 1 , SR _{2 ,} . I have to. Unit delay amount d and number of bits to be processed n
Although this is less of a problem when d is small, for example, if d is 16 words and n is 5, a maximum of 80 words of delay is required. If 1 word is 16 bits, (80 x 16 = 1280) bit shift register
SR ₅ , (4 x 16 x 16 = 1024) bit shift register SR ₄ , (3 x 16 x 16 = 768) bit shift register SR ₃ , and (2 x 16 x 16 = 512) bit shift register SR ₂ and 16-bit shift register
SR ₁ is required. Most commercially available shift registers are in 8-bit units;
100 shift registers to configure SR ₅
It is necessary to connect more than one in series, which causes an increase in cost and an increase in the size of the device. In addition, when compressing (or expanding) the time axis of a bit series, two or more shift registers must be used for each bit series, and the shift registers perform delay and time axis compression (or expansion). It is almost impossible to do both.

The present invention is intended to eliminate the above-mentioned problems when using a shift register.

In the present invention, a (2 ^l ×2 ^k ) word RAM having 2 ^l rows and 2 ^k columns as shown in FIG.
. These l and k
The value of is determined as follows in relation to the unit delay amount d, the number of bit sequences n, and α (word) required for time axis compression (or expansion) processing.

2 ^k-1 <nd+α≦2 ^k 2 ^l-1 <n≦2 ^lIn this way, the word address in the row direction (hereinafter referred to as the X address) and the word address in the column direction (hereinafter referred to as the Y address) are respectively (0,
1, 2, ...2 ^l -1) and (0, 1, 2, ...
2 ^k -1), and address control can be performed very easily. For the X address, the write address is sequentially advanced from address 0 to address (2 ^l -1), and for the Y address, it is advanced sequentially from address 0, d, etc.
Addresses are sequentially advanced from address 2d at intervals of d words, and addresses are designated diagonally as shown in FIG. Regarding the X address, the read address is sequentially advanced from address 0 to address (2 ^l -1), and regarding the Y address, the X address is advanced sequentially from address (2 l -1).
^l -1) After reaching the address, the next address is advanced, and the address is specified in the vertical direction as shown in FIG. In this case, reading is started with a delay of d words ((d+α) words when performing time axis compression processing) after writing is started. It is equivalent to reverse the relationship between the write address and the read address as described above. However, the amount of delay is also reversed as H ₁ =nd, . . . , H _o =d.

Generation of a write address code is realized by the configuration shown in FIG. 3A, and generation of a read address code is realized by the configuration shown in FIG. 3B. In FIG. 3, CB is a bit counter that counts bit clocks and generates word clocks. A word clock is supplied to an l-bit binary counter CW ₁ , to which an m-bit binary counter _{CW 2 and} a (km)-bit binary counter CW ₃ are connected in cascade, and the word clock is supplied to the counter CW ₃ . The write address counter is configured such that the carry output of counter CW ₁ resets counter CW ₃ . The 1-bit output of counter CW ₁ is used as the X address code, and the k-bit output of both counters CW ₂ and CW ₃ is used as the Y address code. These address codes are supplied to an address decoder via an address selector to form an address signal. According to such a write address counter, addresses from 0 to (2 ^l -1) are sequentially designated by the X address code from counter CW ₁ , and during this period, the output of counter CW ₂ does not change, and the output from counter CW ₃ Since only the output of changes,
The Y address changes at intervals of 2 ^m . X
When the address changes once from address 0 to address (2 ^l -1), the counter CW ₃ returns to the original address and the counter CW ₂ is incremented by one. This operation is repeated and counter CW ₂ becomes counter
Counting 2 ^m carries of CW ₁ , the counter CW ₂
One carry is given to the counter CW ₃ , and the counter CW ₃ returns to the one that is one address ahead of the original address. By repeating this action,
Input data is written as described above.

The read address counter is a bit counter.
For an l-bit binary counter _CR1 supplied with the word clock from CB, m-bit and (km)-bit binary counters _CR2 and
It is assumed that CR ₃ is connected in cascade. counter
The l-bit output of CR ₁ is used as the X address code, and the m-bit output of counter CR ₂ and the counter
The output of (km) bits of _CR3 is used as the Y address code.

The present invention will be explained more specifically. As an example, as shown in FIG. 4, one word is connected to 16-bit input serial data Di by an input gate Gi, which is represented as a switch whose connection position changes every word.
The present invention is applied when converting the data into four bit sequences H ₁ to _{H 4} and delaying each bit sequence by 4 words, 8 words, 12 words, and 16 words by shift registers SR ₁ to _{SR 4} . Let me explain the case. In this example, the force data Di that follows W ₁ , W ₂ , W ₃ , W ₄ ... (W indicates one word) becomes W ₁ , W ₅ , W ₉ ... as shown in Fig. 5. Continuing bit series
H ₁ and the bit series H ₂ that continues as W ₂ , W ₄ , W ₆ ...
Then, the series H ₃ continues as W ₃ , W ₇ , W ₁₁ ..., W ₄ ,
_{W 8 , W 12 . _} and one word from each bit series is extracted by output gate _G0 to obtain output serial data _D0 . That is, in this example, (d=
4) (n=4) (α=0), therefore, when applying the present invention, (k=4, l=2, m=
2), as shown in Figure 7 (2 ² × 2 ⁴ )
RAM is used. The X address is represented by X ₀ to X ₃ , the corresponding X address code is represented by 2 bits (x ₁ x ₀ ), and the Y address from Y ₀ to _{Y 15} is represented by 4 bits (y ₃ y ₂ y ₁ y ₀ ). To generate a write address code, a write address counter is configured as shown in FIG. 8A, and to generate a read address code, a read address counter is configured as shown in FIG. 8B. The generation of the address code from the read address counter is delayed by four words with respect to the write address.

The Y address code (y ₃ y ₂ y ₁ y ₀ ) and the X address code (x ₁ x ₀ ) generated by the write address counter change as shown in FIG. 9A with respect to the input data Di. 1 word of first data W ₁
is written to address (X ₀ , Y ₀ ), and the following data
W ₂ , W ₃ , W ₄ are (X ₁ , Y ₄ ) (X ₂ , Y ₈ ) (X ₃ , Y ₁₂ )
Written to addresses sequentially. data w ₅ counter
Since the carry from CW ₁ is given to counter CW ₂ , it is written to address (X ₀ , Y ₁ ). Thereafter, this operation is repeated and data W ₁₆ is written to address (X ₃ , Y ₁₅ ). Next, the carry from counter CW ₂ is given to counter CW ₃ , so the address code (y ₃ y ₂ ) does not return to (00) but becomes (01),
Therefore, data W ₁₇ is written to address (X ₀ , Y ₄ ). By such a write operation, data up to _W64 are written, and the same write address control as shown in FIG. 9A is performed again from data _W65 . Therefore, at the time when W ₆₅ , W ₆₆ . . . W ₇₂ are written, data has been written to each address of the RAM as shown in FIG.

The address code from the read address counter has an X address of X ₀ to X ₃ as shown in FIG. 9B.
When it advances to , the Y address advances by one,
Since the read address is four words behind the write address, _W65 is read when _W69 is written, _W50 is read when _W70 is written, and _W35 is written when _W71 is written. is read and W ₇₂
W ₂₀ is read when W 20 is written. accordingly
The output data D ₀ obtained from the RAM becomes serial data as shown in FIG. 10, and 16 (4d) words exist between one data W ₆₅ and the next data W ₆₆ .

As understood from the above description, according to the present invention, instead of using shift registers SR ₁ , SR ₂ , SR ₃ , SR ₄ and gates Gi and Go, a (4×16) RAM can be used. Thus, the four bit sequences can be delayed by a predetermined amount. The address control at this time is extremely simple and can be realized by a conventional address counter configuration.

Furthermore, according to the present invention, the capacity of RAM can be reduced. That is, the RAM capacity can be reduced by dividing the required capacity into RAM blocks divided into 1/2 ^x (x is any positive integer). As in the above example, (2 ² × 2 ⁴ )
The RAM is set to X address and Y address as shown in Figure 11.
Divide both addresses into two to create (2 ² = 4)
Form a block of RAM M ₁ M ₂ M ₃ M ₄ , this RAM
Of the blocks _M1 to _M4 , _M3 may be omitted and the data written to _M3 may be written to _M1 .
That is, when the X address code is [00] or [01] during a write operation, the Y address is specified in the lower three bits of the Y address code as shown by the broken line in FIG. 9A, and the X address code is 〔Ten〕
In the case of and [11], the Y address can be specified using the 4-bit Y address code as is. As the write address, a structure similar to that shown in FIG. 8A can be used. In the read operation, data may be read out alternately from M ₁ and M ₂ and from M ₁ and M ₄ by the same address control as described above.

The present invention described above allows stereo audio signals to be
It can be applied to the encoder of a device that performs PCM modulation and records and plays back via a VTR. like this
A PCM signal recording and reproducing apparatus is shown in FIG. In Fig. 12, 1 indicates a helical scan type VTR, and the video input terminal 2i has a signal format similar to that of a television signal.
A PCM signal is supplied and recorded on a magnetic tape via the recording system of the VTR 1, and the reproduction output of this magnetic tape appears at the video output terminal 2o via the reproduction system.

3L and 3R indicate terminals to which the left channel signal and right channel signal of the stereo audio signal are supplied, respectively, and 4L and 4R are low-pass filters. The left and right channel signals are sampled by sampling and holding circuits 5L and 5R, encoded by AD converters 6L and 6R, and their parallel outputs are supplied to encoder 7. The encoder 7 performs processing such as addition of parity bits and CRC codes and time-base compression, and the resulting data is added to the synchronous mixing circuit 8 as a serial code. Reference numeral 9 indicates a basic clock oscillator, and from this basic clock, sampling pulses, clock pulses for AD conversion, composite synchronization signals, and encoder 7
Control signals and the like are generated by the pulse generating circuit 10, and the output of the mixing circuit 8 is supplied to the video input terminal 2i of the VTR 1.

A PCM signal reproduced by the VTR 1 and taken out to the video output terminal 2o is supplied to the sync separation circuit 11. The composite synchronization signal separated by the synchronization separation circuit 11 is supplied to the pulse generation circuit 12, and the PCM
A signal is provided to a decoder 13. Decoder 13
Processing such as time axis expansion, error detection, and error correction is performed by AD converter 14 as a parallel code.
L and 14R, and its analog output is led to output terminals 16L and 16R via low-pass filters 15L and 15R. A control signal for the decoder 13, clock pulses for the DA converters 14L and 14R, timing pulses for synchronization separation, etc. are generated by the pulse generating circuit 12.
The time base in this case is the reproduced composite synchronization signal.

In the encoder 7, each of the left channel and right channel PCM signals is converted into three bit sequences, and parity bit sequences are formed for these six bit sequences, making a total of seven bit sequences to which the present invention is applied. Delay processing and time axis compression processing are performed by the RAM and its control circuit. As a result, the RAM readout output is as shown in Figure 13A.
It will be as shown below. In Figure 13, L and R
denotes one word of the PCM signal regarding the audio signals of the left and right channels, respectively, and P denotes one word of the parity bit. Equivalent 17H or 18H
A data missing period of length (H indicates one horizontal period) is formed by time axis compression processing. As shown in Figure 13B, CRC is applied every 7 words of this serial data.
A period is formed in which the code and horizontal synchronization pulse HD are inserted, and finally the synchronization signal and CRC code are added and recorded via the recording system of the VTR 1 as shown in FIG. .

One word of parity bit, for example P ₁ , is L ₁ ,
The corresponding bits of the six words R ₁ , L ₂ , R ₂ , L ₃ , and R ₃ are selected so that "1" is either an even number or an odd number. Therefore, if only one word out of the six words mentioned above is erroneous as a result of error detection using the CRC code, the erroneous word can be corrected using the parity bit. 1st
As shown in Figure 3A, if we ignore the data missing period corresponding to the CRC code and the blanking period, the 6 words related to the parity bit, which is the serialized data recorded and reproduced, are at least 6d. Since the arrays are located words apart, if a burst error caused by dropout or the like is within 6d words, it is possible to correct the error.

When the unit delay amount d is 16 words, the maximum delay amount 6d is 96 words, so the minimum necessary capacity of the RAM is (7×97). Also 18H
It is necessary to compress the time axis (expansion during playback), and as 7 words are inserted in 1H as shown in Figure 13C, the capacity of (7 x 18) words is allocated for time axis compression. It will be done. Furthermore, it was played
Since the PCM signal includes time axis fluctuations called jitter, a margin of ±6.5H is provided to remove the time axis fluctuations, and as a result, as shown in Figure 14, It has 7 X addresses from X ₀ to X ₆ and 128 Y addresses from Y ₀ to Y ₁₂₇ (7
×128) RAM is used. The same write operation as above is performed, and the input serial data ( _{X 0 , Y 0 )} (X ₁ , Y ₁₆ ) (X ₂ ,
Y ₃₂ ) (X ₃ , Y ₄₈ ) (X ₄ , Y ₆₄ ) (X ₅ , Y ₈₀ ) (X ₆ ,
Y ₉₆ )... are sequentially written as shown by diagonal arrows in FIG. The read operation is performed in the vertical direction, and when the X address goes through one cycle, the Y address advances by one. In order to compress the time axis when recording PCM signals, the read operation is performed with a delay of 18H (18×7=126 words) after the write operation is started. The read clock frequency is selected to be higher than the write clock frequency, so that when reading is performed for a period of 245H within one field period, the read operation is stopped for a period of 18H. For time axis expansion during PCM signal reproduction, conversely, the read clock frequency is selected to be lower than the write clock frequency. During playback, the read operation is started later than the write operation in consideration of time axis fluctuations. For these time axis compression and expansion processes, since the RAM cannot perform write and read operations at the same time, the write and read operations are controlled to be asynchronous.

FIG. 15A shows the configuration of a write address counter for realizing the above operation. The word clock formed by bit counter CB is 3
It is supplied to a 2-bit binary counter CW ₁ and a 2-bit binary counter CW ₃ . 3-bit output of binary counter CW ₁ (x ₂ x ₁ x ₀ )
is used as the X address code. A carry occurs when the X address code becomes (110) and the next word clock is given (000).
Back to the hexadecimal configuration and counter CW ₁ is there. The carry of counter CW ₁ is supplied to 4-bit binary counter CW ₂ , and counter CW ₂
A binary counter with a 2-bit carry
CW ₃ is supplied, and the carry of counter CW ₃ is 1.
A bit binary counter _CW4 is supplied with the bit. Counters CW ₃ and CW ₄ are reset by the carry of counter CW ₁ . The 7-bit output (y ₆ y ₅ y ₄ y ₃ y ₂ y ₁ y ₀ ) of these counters CW ₂ CW ₃ CW ₄ is used as the Y address code.

The read address counter is composed of counters CR ₁ , CR ₂ , CR ₃ and CR ₄ connected in cascade as shown in FIG. _15B , and the 3-bit output (x ₂ x ₁ x ₀ ) is taken as the X address code, and the 7-bit output of the other counter is taken as the Y address code. The operations of the write address counter and read address counter are an extension of the operations of both in the example described above.

According to the present invention described above, processing for changing the arrangement order of digital information signals such as PCM signals from the original can be performed using RAM instead of using shift registers. Therefore, there is no need to connect many shift registers in cascade, and the configuration of the device can be made inexpensive and simple. Furthermore, time axis compression (or expansion) processing can be performed simultaneously. Furthermore, by determining the X address and Y address of the RAM in relation to the number n of bit sequences to be processed and the unit delay amount d as described above, address control can be performed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional device, FIG. 2 is a schematic diagram used to explain RAM address control according to the present invention, and FIG. 3 is a block diagram of a write address counter and a read address counter, respectively.
FIG. 4 is a block diagram of a conventional device according to an embodiment of the present invention, FIGS. 5 and 6 are schematic diagrams used for explaining the same, and FIG. 7 is a schematic diagram showing a RAM according to an embodiment of the present invention. 8A and 8B are block diagrams of a write address counter and a read address counter in an embodiment of the present invention, FIG. 9 is a schematic diagram showing changes in address codes, and FIG. 10 is a diagram of read data. 11 is a schematic diagram used to explain another embodiment of the present invention; FIG. 12 is a block diagram of a PCM signal recording and reproducing apparatus to which the present invention is applied as an encoder and a decoder; 1st
Figure 3 is a schematic diagram showing the signal arrangement during recording.
Figure 4 is a schematic diagram showing RAM address control when the present invention is applied to an encoder and decoder of a PCM signal recording/reproducing device, and Figures 15A and 15B are block diagrams of a write address counter and a read address counter, respectively. be. M is RAM, SR ₁ SR ₂ ... SR _o is shift register, CB is bit counter, CW ₁ , CW ₂ , CW ₃ ,
CW ₄ is the write address counter, CR ₁ , CR ₂ ,
CR ₃ and CR ₄ are read address counters.

Claims (1)

[Claims] 1 Digital information signals input in a predetermined arrangement
In a digital signal processing device that provides a predetermined delay amount by writing to and reading from a RAM, a matrix of X and Y addresses is provided to the RAM, and each time the X address is sequentially advanced, the Y address is set to the predetermined delay amount. The writing (or reading) operation of the digital information signal is performed so as to advance the digital information signal by an amount corresponding to the amount, and the reading (or writing) operation of the digital information signal is performed so as to advance the X address sequentially.
A digital signal processing device configured to control a RAM and obtain a digital information signal having an arrangement different from the predetermined arrangement from the RAM.