JP2973731B2 - Digital video signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording / reproducing or transmitting a digitized video signal, for example, an apparatus for processing a digital video signal in an apparatus such as a digital VTR.

[0002]

2. Description of the Related Art As a VTR for recording and reproducing a component digital video signal, a so-called D-1 has been commercialized ("SMPTE D-1 DVTR").
1986). This is a digital VTR that quantizes a 4: 2: 2 signal shown in CCIR recommendation 601 into 8 bits and records and reproduces it. Here, the 4: 2: 2 signal is
This is a signal obtained by sampling a luminance signal and two color difference signals at 13.5 MHz and 6.75 MHz, respectively. The present television signal has an aspect ratio of 4: 3 and a scanning method of 525 lines / 60 Hz or 625 lines / 50 Hz. It follows.

On the other hand, there has been a movement to keep the aspect ratio 16: 9 horizontally while keeping the scanning method as it is. EDTV-II in Japan, ATV in the United States, Clean PAL, PAL Plus, Extended 4: 2 in Europe. : 2, etc. are being studied. Here, we consider the following method and extend it to Extended 4:
Let's call it 2: 2.

In the extended 4: 2: 2, the horizontal length of the screen is 4: 4 in order to make the number of scanning lines in the vertical direction the same as 4: 2: 2 and the aspect ratio to 16: 9.
Make 2/3 4/3 times. Therefore, if the sampling frequency of the A / D conversion is set to 4/3 times D-1, the interval between the sampling points on the screen becomes the same as D-1.

Therefore, the sampling frequency of the luminance signal and the two color difference signals in the extended 4: 2: 2 is set to 18 MHz and 9 MHz at 4/3 times the sampling frequency of D-1, respectively, and the number of quantization bits is set to 8 bits. And Assuming that the digital video signal obtained by such sampling is a first digital video signal, the data rate required for a digital VTR for recording the digital video signal is represented by a bit rate, which is (18 + 9 × 2).
× 8 = 288 Mbit / sec. On the other hand, the data rate of D-1 is (13.5 + 6.75 × 2) × 8 = 216
Since the bit rate is M bits / sec, it is necessary to use a recording / reproducing device having a higher data rate than D-1 as a digital VTR for recording the first digital video signal.

Accordingly, a new digital VTR for recording and reproducing the above-mentioned first digital video signal is newly considered, and is hereinafter referred to as DX.

At this time, the 4: 2: 2 signal corresponding to the current television signal having the aspect ratio of 4: 3 will be used in the future, so that the DX can record the 4: 2: 2 signal. Is desirable. So 4: 2:
Consider a digital video signal obtained by quantizing two signals with 10 bits, and use this as a second digital video signal. The data rate in this case is (13.5 + 6.75 × 2)
× 10 = 270 Mbit / sec, which is lower than the data rate of the first digital video signal and is relatively close.

[0008] Therefore, the data consisting of 10-bit words of the second digital video signal is encoded into data consisting of 8-bit words and recorded on DX, thereby extending the extended 4: 2: 2 and 4: 2. : 2, a digital VTR capable of recording both.

In order to encode such a 10-bit sample into a word composed of 8 bits, conventionally, each 10-bit sample is divided into upper 8 bits and lower 2 bits, and four consecutive samples are divided. The lower two bits are combined and converted into one 8-bit word (for example, JP-A-60-262279).

[0010]

However, in such a conventional system, when an error occurs during the recording / reproducing or transmission process, the error is usually corrected in units of one word, so that the lower two bits are grouped. When an error occurs in a word, all the lower two bits of four consecutive samples become erroneous, resulting in four consecutive sample errors. Therefore, there is a disadvantage that the image quality deteriorates greatly because the error occurs close to the screen.

In view of the above, the present invention provides a digital video signal processing apparatus for preventing the four lower 2 bits forming one word to be recorded or reproduced or transmitted from becoming four consecutive samples.

[0012]

According to the present invention, m bits (m
> 0 of the first clock rate quantized by
For one digital signal, n bits (n> m
), The second clock of the second clock rate quantized by
A digital signal processing device, wherein m is (nm)
Divided, its quotient is f, and the second digital video signal
The upper m bits of each sample of the signal are the upper sample, the lower
(N−m) bits as lower-order samples and upper-order samples as words consisting of m bits are stored for one horizontal scanning period, written at a second clock rate,
A high-order memory read at a first clock rate ;
Then , while storing for one horizontal period , the second clock
Write at the crate and read at the first clock rate <br/> Write the lower memory and the upper sample to the upper memory
The upper write address and the lower sample
Lower the write address generating circuit for generating a write address, from the memory and a lower memory superordinate for reading the word consisting of m bits each, the readout for generating an upper read address and the lower read address for writing to use the memory includes an address generating circuit, an upper lower selecting circuit for selecting either the output of the output or the lower level memory of the memory for the upper, writing to the lower memory
The writing is performed by using an m-bit word and a predetermined (n-
m) bits and consecutive f lower samples
Lower write address indicating different words for
And reading from the lower memory is performed by f
Indicates an m-bit word consisting of
This is performed according to the lower read address, and
The route is the output type from the upper memory and the lower memory.
Switching in synchronization with the
Obtain data word sequence of m-bit connection was, of digital video signal processing apparatus, and, the digital video
The first clock rate sequence obtained by the signal processing device
Device that processes m-bit word string data
The upper memory for selectively storing only the word composed of the upper sample of the data of the word string for one horizontal scanning period, and selectively storing only the word composed of the lower sample of the data of the word string for 1 A lower memory for storing the horizontal scanning period, a write address generating circuit for generating an m-bit word write address to the upper memory and the lower memory, and reading of an upper sample from the upper memory Bei a read address generating circuit for generating a read address of the lower sample from the address and the lower memory
The upper sample read from the upper memory is
And bits, the lower sample read from the lower memory as a lower (n-m) bits, form one n-bit samples, a processing apparatus in a digital video signal for decoding the second digital video signal.

[0013]

In the encoding process, the lower samples are written into the lower memory in units of (nm) bits at the clock rate of the second digital video signal in accordance with the lower write address generated by the write address generating circuit.
You. At this time, the lower write address is the second digital address.
F lower-order samples in the horizontal video signal
Different m-bit words in the lower memory
Is generated, one of the lower-order memories is generated.
From f (nm) bits forming an m-bit word
Subsampled into the second digital video signal.
Does not include those that are continuous in the horizontal direction. Then, after one horizontal scanning period, at the clock rate of the first digital video signal, according to the lower read address generated by the read address generating circuit, f lower samples are combined and m bits are added at a rate of one word to the f + 1 clock at m bits. Read out intermittently. Thus, one word of data read from the lower-order memory can be constituted by f lower-order samples that are not continuous in the second digital video signal. During this time, the upper samples are written into the upper memory at the clock rate of the second digital video signal in the order of samples, and after one horizontal scanning period,
F + 1 at the clock rate of the first digital video signal
The data is read out intermittently again in the same order at the rate of f words for the clock.

Further, f + 1 is selected by the upper / lower selection circuit.
By selecting the output from the upper memory at the rate of f words for the clock and the output from the lower memory at the rate of 1 word for the f + 1 clock, m bit words continuous at the clock rate of the first digital video signal You can get columns.

In the decoding process, from the data of m-bit words transmitted at the clock rate of the first digital video signal, only the data coded from the lower samples originally present at a rate of 1 word at f + 1 clock Is selected and stored in the lower memory according to the lower write address generated by the write address generating circuit. This is read out after one horizontal scanning period at the clock rate of the second digital video signal according to the lower readout address generated by the readout address generation circuit. At this time, by selecting any (nm) bits in the m-bit word in the same order as in the encoding process, a lower sample consisting of the original (nm) bits can be configured. On the other hand, the m-bit data, which is originally an upper sample at the rate of f words in the remaining f + 1 clocks, is written in the upper memory in accordance with the write address, and after one horizontal scanning period, is read in the same order as the write in accordance with the read address. By
An upper sample of the second digital video signal corresponding to the lower sample is obtained. By combining the upper sample and the lower sample thus obtained into one n-bit word, the original second digital video signal is obtained.

As described above, an m-bit lower word can be formed from lower (nm) bits of an arbitrary f sample in one line by using the lower memory.

[0017]

FIG. 1 is a block diagram showing the configuration of a digital video signal encoding apparatus according to a first embodiment of the present invention.

In this embodiment, the first digital video signal is a luminance component of the analog component video signal,
The sampling frequency is 18 MHz, the quantization bit number is 8 bits, and the color difference component is sampled at a sampling frequency of 9 MHz.
z, which is quantized with a quantization bit number of 8 bits.
In the second digital video signal, the luminance component is quantized at a sampling frequency of 13.5 MHz and the number of quantization bits is 10 bits, and the color difference component is quantized at a sampling frequency of 6.75.
MHz and 10 bits of quantization bits.

The luminance signal of the second digital video signal is subjected to the encoding of the present invention, and the two color difference signals are time-division multiplexed into one channel to have the same clock rate as the luminance signal. By performing the encoding according to the present invention, each of the luminance signal and the color difference signal is converted and output as the same 18 MHz, 8 bit digital signal as the first digital video signal.

At this time, the number of effective samples per line is 9 luminance components in the first digital video signal.
In the second digital video signal, the luminance component is 720 samples, and the two color difference signal components are 360 samples, respectively.
Make a sample. Therefore, the effective data after encoding the second digital video signal is (720 × 10)
/ 8 = 900 words, which is converted into a data amount slightly smaller than 960 words of valid data of the first digital video signal. Therefore, the second digital component video signal can be recorded by using the encoding device of the present invention in a digital VTR for recording and reproducing the first digital component video signal.

In FIG. 1, reference numeral 101 denotes a low-pass filter (abbreviated as LPF in the figure; the same applies hereinafter) for removing aliasing distortion from the luminance signal 151 of the analog component video signal, and reference numerals 102 and 103 denote analog component video. A low-pass filter for removing aliasing distortion of each of the two color difference signals 152 and 153 of the signal. An A / D converter 104 converts an analog luminance signal into an analog signal.
/ D conversion circuit (abbreviated as AD in the figure; the same applies hereinafter), 10
5 and 106 respectively convert two analog color difference signals into A / D signals.
A / D conversion circuit for converting, 107 is A / D converted 2
A multiplexer 108 for alternately selecting and time-division multiplexing one digital chrominance signal, and 108 is an upper 8 bits 155 of the digital luminance signal 154 sampled by 10 bits.
, 109 is a lower-order memory that stores the lower 2 bits 156 of the digital luminance signal 154 sampled by 10 bits, 110 is an upper 8 bits of the digital color difference signal 157 sampled by 10 bits.
Upper-order memory for storing bits 158, lower-order memory 111 for storing lower two bits 159 of digital color difference signal 157 sampled by 10 bits, and 112 for writing data to conversion memories 108, 109, 110, and 111 A write address generating circuit 113 for generating an address, 113 is a conversion memory 108, 109, 110,
A read address generating circuit for generating a read address of data from 111; a video synchronization signal extracted from a luminance signal of the analog component video signal;
13.5 MHz, 6.75 MHz, 18
A synchronous control circuit that generates a clock of MHz and outputs a reset signal 160 that matches the timing of the write data and a reset signal 161 that matches the timing of the read data. A selection circuit 116 for switching and outputting read data from the memory 109 at a ratio of 4: 1, 116
Is a selection circuit for switching and outputting read data from the upper memory 110 and read data from the lower memory 111 at a ratio of 4: 1.

Hereinafter, the operation of the encoding circuit according to the first embodiment of the present invention will be described. The luminance signal 151 of the analog component video signal has a pass frequency band of about 5.7.
The band is limited through a low-pass filter 101 of MHz, and then input to an A / D converter 104. At the same time, the band-limited analog luminance signal 162 is supplied to the synchronization control circuit 114. The synchronization control circuit 114 separates the video synchronization signal from the analog luminance signal,
13.5M synchronized with horizontal video sync signal by L circuit
A sampling clock 163 of 1 Hz is generated. The sampling clock 163 allows the A / D converter 10
4, the analog luminance signal is 10 bits 13.5 MH
Sample at z.

With respect to the luminance signal 154 of the second digital video signal obtained in this way, the upper 8 bits 15
5 is written to the upper memory 108 and the lower 2 bits 156 are written to the lower memory 109 in synchronization with a 13.5 MHz clock.

At this time, the write address generation circuit 11
2 is a reset signal 16 obtained from the synchronization control circuit 114.
Based on 0, a 10-bit write address 164 described later is synchronized with a 13.5 MHz clock so that valid samples are written to the upper memory 108 in the same order as the sample in the memory and in the same order on the memory. Occur. As for the write address 165 of the lower-order memory 109, the lower-order sample 156 is written into any two bits of the encoded 8-bit word, bit 0, bit 1, bit 2, 3, bit 4, 5, and bit 6, 7. , And an 8-bit address indicating the reading order within one line after encoding. The lower order memory 109 is arranged in a different order from the order in which the effective samples are sampled. So that the write address 165 described later is set to 1
It is generated in synchronization with a 3.5 MHz clock.

After the data for one line is written in the upper memory 108 and the lower memory 109 in this manner, the data is read out in 8-bit units in synchronization with the 18 MHz clock in the next one line period. At this time, based on the reset signal 161 obtained from the synchronization control circuit 114, the read address generation circuit 113 is read from the upper memory 108 in the same order as the sampled valid samples in synchronization with the 18 MHz clock. Thus, a read address 166 as described later is generated. Also, the read address 16 of the lower-order memory 109
With respect to 7, a read address 167, which will be described later, is generated so as to be read from the lower-order memory 109 as 8 bits each of 4 samples in an order different from the order in which valid samples were written.

At this time, the selection circuit 115 time-division multiplexes the output from the upper memory 108 and the output from the lower memory 109 by 4: 1. For example, in five clock cycles, four clocks select the output from the upper memory 108 and the remaining one clock selects the output from the lower memory 109. Alternatively, in 10 clock cycles, 8 clocks select the output from the upper memory 108 and the remaining 2 clocks select the output from the lower memory 109. Alternatively, in the 20 clock cycle, 16 clocks select the output from the upper memory 108, and the remaining 4 clocks select the output 109 from the lower memory.

On the other hand, two analog color difference signals 152, 1
53 is a low-pass filter 1 having a pass band of about 2.7 MHz.
After being band-limited by 02 and 103, the A / D converters 105 and 106 respectively have 10 bits 6.75.
Sampled at MHz. At this time, 6.75 MHz
The sampling clock 168 of the synchronization control circuit 114
Accordingly, it is generated in synchronization with the horizontal video synchronization signal included in the analog luminance signal 162.

In the multiplexer 107, two digital color difference signal samples 169 and 170 are alternately 13.5.
13.5M which is twice the frequency of the sampling clock 168 by selecting in synchronization with the MHz clock.
One color difference signal sample synchronized with the Hz clock is constructed and output. As a result, a 10-bit color difference signal 157 at 13.5 MHz is obtained in the same manner as the luminance signal 154.

This 10-bit color difference signal sample 157
The lower 8 bits 158 are written in the upper memory 110 so that they are read out in the same order as the luminance signal, and the lower 2 bits 159 are read out in the same order as the luminance signal. Write to.
Further, reading from the upper-level memory 110 and the lower-level memory 111 is performed in the same manner as the luminance signal.
4: 1 time-division multiplexing and the subsequent digital V
Send to TR.

FIG. 2 shows an example of a signal of each section in the first embodiment. This figure shows a process of encoding a luminance signal, and shows a case where 4 clocks are encoded into a word composed of upper 8 bits and a clock is encoded into a word composed of lower 2 bits in a 5-clock cycle.

Now, when the sample number of the valid sample is represented by S, the write address of the upper 8 bits is represented by Wu, the read address is represented by Ru, the write address of the lower 2 bits is represented by Wl, and the read address is represented by R1, for example, the write of the upper 8 bits is performed. Wu = S for the address 164, and Wl = 4 × (S mod 180) + int (S / 180) (1) for the lower two bits of the write address 165. Here, mod represents a remainder operation, and int represents an operation for rounding down decimals or less. Here, a 2-bit address indicating which pair of bits 0, 1, bit 2, 3, bit 4, 5, and bit 6, 7 of an 8-bit word forming the memory is to be written is the lower 2 bits of the above-mentioned Wl. And the remaining upper 8 bits of Wl are used as the address of an 8-bit word constituting the memory. As a result, only the two bits of the lower-order memory 109 can be selected and the lower two-bit data 156 can be written.

That is, the upper 8-bit write address 16
4 are generated in the order of 0, 1, 2, 3,... As shown in FIG.
Write 0, U1, U2, U3,... To the upper memory 108 in the same order. On the other hand, as shown in FIG.
,..., L0, L1, L2, L3,... Of the lower two-bit data 156 are written to two bits of discrete addresses in the lower memory 109.

When the data written in the above order is read out, the read addresses 166 and 167 are read intermittently in order from the youngest memory address, as shown in FIG. Bit (L0, L180, L360, L54
0), (L1, L181, L361, L541), ...
Can constitute one 8-bit word. Also, by making the above equation (1) an appropriate equation, one 8-bit word can be configured using the lower 2 bits of an arbitrary sample in one line.

Next, the output from the upper memory 108 and the effective output portion of the output from the lower memory 109 are selected by a selection circuit 115, thereby forming one 8-bit 18 MHz signal as shown in FIG. The output is obtained.

As described above, when the clock rate is 1
A second digital video signal having 3.5 MHz and 10 bits can be encoded into a signal having the same clock rate of 18 MHz and 8 bits as the first digital video signal.

The detailed configuration of each block will be described below. First, a detailed configuration of the upper memory 108 is shown in FIG. The upper-level memory 108 is composed of two RAMs 301 and 302 each having a 1-line × 8-bit configuration.
In accordance with the write / read switching signal 171 obtained from, writing / reading is alternately switched for each line. The write address 164 and the read address 166 are RA-addressed by the address selection circuits 303 and 304 controlled by the write / read switching signal 171.
M301 and RAM302 are supplied alternately for each line. For example, when a write address is supplied to the RAM 301 through the D flip-flop 305, the write data 155 consisting of the upper 8 bits of the video sample is supplied to the RAM 301 through the D flip-flop 306.
The data 155 is supplied to the AM 301 and written to the address of the RAM 301 indicated by the write address 164. At this time, the output of the D flip-flop 307 that supplies write data to the RAM 302 is set to high impedance. On the other hand, a read address is supplied to the RAM 302 through the D flip-flop 308, and read data 351 which is an output thereof is selected by the output selection circuit 309. In this way, after writing the upper 8 bits of the valid samples for one line into the RAM 301,
After the horizontal scanning period, the write / read is switched by the write / read switch signal 171 to RA
Data is read from M301 and written to RAM 302. The operation at this time is just the opposite operation.

As described above, in the upper memory 108, the upper word 155 is alternately written to and read from the RAM 301 and the RAM 302 line by line in accordance with the order indicated by the write address 164 and the read address 166, thereby reducing the one-line delay. Constitute.

The same applies to the configuration and operation of the upper memory 110. Next, a detailed configuration of the lower-level memory 109 is shown in FIG. As shown in FIG.
09 is eight RAMs 401, 402, 403, 404,
405, 406, 407, and 408.
These eight RAMs are RAMs 401, 402, 403,
404 groups and RAMs 405, 406, 407, 4
08 groups constitute two groups. Each RAM has a configuration of 1 line × 2 bits and a data bus 4
RAMs 401 and 405 correspond to bits 0 and 1 respectively, RAMs 402 and 406 correspond to bits 2 and 3 respectively, RAMs 403 and 407 correspond to bits 4 and 5 respectively, and RAMs 404 and 408 correspond to bits 6 and 51 respectively. , Bit 7. RAM4
01, 402, 403, 404 group and RAM 40
For the groups of 5, 406, 407, and 408, writing and reading are performed alternately for each line in accordance with the write / read switching signal 171 and exchanged. At this time, the writing is performed in synchronization with the 13.5 MHz clock, and the reading is performed in synchronization with the 18 MHz clock, so that the clock rate is converted.

When writing to the RAMs 401, 402, 403, and 404 and reading from the RAMs 405, 406, 407, and 408, a 10-bit write address 16
5 is selected by the address selection circuit 409, and the upper 8 bits of the write address 165 are selected via the D flip-flop 410.
The bits are supplied to the RAMs 401, 402, 403, and 404, and the lower two bits are supplied to the address decoder 411. The address decoder 411 has four RAMs 401, 402, 403, and 4 according to the lower two bits of the write address.
04, which RAM is to be used for writing data. On the other hand, the 8-bit read address 167 is selected by the address selection circuit 412 and is transmitted via the D flip-flop 413 to the RAMs 405, 406, 407, and 40.
8 is supplied. At this time, by supplying the write / read switching signal 171 to the address decoder 414, all the four RAMs 405, 406, 407, and 408 are selected at the same time, and reading is performed simultaneously from the same address of the four RAMs. At this time, the output of the D flip-flop 420 is set to high impedance.

The write data 156, which is the lower two bits of the digital video sample, is input to the 8-bit D flip-flops 419 and 420 by two bits, bit 0 and bit 1, bit 2 and bit 3, bit 4 and bit 5, bit 4 6 is connected to bit 7 in parallel, thereby expanding to 8 bits. The 8-bit word consisting of the lower 2 bits expanded to 8 bits is written in the RAMs 401, 402, 403, and 4 by the address decoder 411 in the order indicated by the write address 165.
The data is written to one address of one RAM selected from 04. Therefore, data to be written simultaneously is only two bits at one address of one RAM.

On the other hand, in the read side group, the RAM
By simultaneously reading the same addresses 405, 406, 407, and 408, an 8-bit word consisting of the lower two bits of four separate video samples written at different timings at the time of writing can be formed and read.

In this manner, the lower 2 bits of the effective samples for one line are stored in the RAMs 401, 402, 403,
After writing to the 404 and one horizontal scanning period later, the writing / reading switching signal 171 causes the writing / reading.
By switching the reading, the RAM 401, 402, 403,
The data is read from the RAM 405,
Data is written to 407 and 408. The operation at this time is just the opposite operation.

As described above, writing and reading are alternately performed on two RAM groups line by line.
The read data is selected by the multiplexer 421 according to the write / read switching signal 171. As a result, the lower-order memory 109 is configured, and one-line delay and conversion from 2 bits to 8 bits can be performed.

The same applies to the configuration and operation of the lower-order memory 111. On the other hand, the write address generation circuit 112 and the read address generation circuit 113 which generate the write address 165, the read address 167, and the write / read switching signal 171 as shown in FIG.
It can be easily configured by using a counter and a decoder that are reset every two lines. At this time, by appropriately selecting the logic of the decoder, it is possible to generate an arbitrary address sequence as shown, for example, in equation (1). As a result, one 8-bit word can be formed from the lower 2 bits of an arbitrary sample in one line.

Next, a specific configuration of the synchronization control circuit 114 is shown in FIG. Analog luminance signal 1 including video synchronization signal
62, the horizontal synchronizing signal 5
50 and the vertical synchronization signal 551 are extracted. The PLL 502 generates a 13.5 MHz clock 552 synchronized with the horizontal synchronizing signal 550 as a reference. PLL
In 503, 18M synchronized with the horizontal synchronization signal 550 is also used.
An Hz clock 553 and other necessary control signals are generated. In the first timing generation circuit 503, 18M
Based on the Hz clock 553, the horizontal synchronizing signal 550, and the vertical synchronizing signal 551, a reset signal 161 of the read address generating circuit synchronized with the 18 MHz clock is generated. In the second timing generation circuit 504, 13.5M
Hz clock, horizontal synchronization signal 550, vertical synchronization signal 55
1, the reset signal 160 of the write address generation circuit synchronized with the 13.5 MHz clock, the sampling clocks 163 and 168, and other necessary control signals are generated. These timing generation circuits 503,
504 can be easily configured by using a frame counter and a decoder.

As described above, 13.5 MHz 10
Bits of the second digital video signal,
It can be encoded into a bit signal.

Next, as a second embodiment of the present invention, a circuit for decoding the 8-bit data encoded by the encoding circuit shown in the first embodiment into the original second digital video signal will be described. explain.

FIG. 6 is a block diagram showing a configuration of a decoding apparatus according to the second embodiment of the present invention. In FIG.
01 is a synchronization control circuit that generates a clock and a control signal in synchronization with the external analog reference signal 650, 602 is a write address generation circuit that generates a write address to each conversion memory, and 603 is a write address generation circuit that 604 is a read address generation circuit for generating a read address, 604 is an upper memory for storing one line of a word 657 which was originally the upper 8 bits of the video sample among the 8-bit luminance words 651 reproduced from the digital VTR, and 605 is Similarly, of the 8-bit luminance word 651, the lower-order memory for storing one line of the word 658 which was originally the lower 2 bits of the video sample, and 606 is the video sample of the 8-bit color difference word 652 reproduced from the digital VTR. The upper 8 bits of Upper memory for word 659 one line memory has, 607 also 8-bit chrominance words 65
2, a lower-order memory for storing one line of the word 660, which was originally the lower 2 bits of the video sample,
A dividing circuit 608 alternately divides a 10-bit chrominance signal sample and outputs two chrominance signal components 655, 656, and 609, 610, 611 denote a 10-bit luminance sample 654 and a chrominance sample 655, 656 by D, respectively.
D / A conversion circuits (abbreviated as DA in the figure) for performing A / A conversion and converting them into an analog luminance signal and two analog color difference signals, respectively.
This is a low-pass filter for removing aliasing distortion from two color difference signals.

The operation of the decoding circuit will be described below. First
Reproduced digital luminance signal 65 encoded into the same 8-bit 18 MHz data of a digital video signal of
1 indicates that a word originally consisting of the upper 8 bits of the digital luminance sample of the second digital video signal and a word originally consisting of four lower 2 bits of the digital luminance sample of the second digital video signal. It is divided and multiplexed.

Of the reproduced digital luminance signal 651,
Only the word that was originally the upper 8 bits of the digital luminance sample of the second digital video signal is written into the upper memory 604 in synchronization with the 18 MHz clock, and the lower 2 bits of the digital luminance sample of the first digital video signal are originally written. Only the word composed of four bits is written to the lower memory 605 in synchronization with the 18 MHz clock. At this time, the write address 6 generated by the write address generation circuit 602 is generated.
60 and 662 are addresses in the same order as the read addresses 166 and 167 in the first embodiment, as described later.

The reproduced data thus written is
After one horizontal scanning period, the read address generation circuit 603
According to the read addresses 665 and 666 where
The data is read out from the memories 604 and 605 in synchronization with the 13.5 MHz clock. At this time, the read address 6
65 and 666 are addresses in the same order as the read addresses 166 and 167 in the first embodiment, as described later.

The output of the upper memory 604 obtained as described above is set to the upper 8 bits, and the output of the lower memory 605 is set to the lower 2 bits.
The luminance signal 654 of the second digital video signal is obtained. The D / A converter 609 converts the luminance signal 654 of the second digital video signal into an analog signal, and removes unnecessary components of the analog signal by the low-pass filter 612 to obtain an analog luminance signal.

On the other hand, the reproduced digital color difference signal 652 encoded into the same 8-bit 18 MHz data as the first digital video signal is a word which was originally the upper 8 bits of the digital color difference sample of the second digital video signal. And a word which is originally composed of four low-order 2 bits each of the digital chrominance samples of the second digital video signal is time-division multiplexed.

Of the reproduced digital color difference signal 652,
Only the word that was originally the upper 8 bits of the digital chrominance sample of the second digital video signal is written into the upper memory 606 in synchronization with the 18 MHz clock, and the lower 2 bits of the digital luminance sample of the first digital video signal are originally written. Only the word composed of four bits is written to the lower memory 607 in synchronization with the clock of 18 MHz. At this time, the write address 6 generated by the write address generation circuit 602 is generated.
63 and 664 are addresses in the same order as the read addresses 166 and 167 in the first embodiment, as described later.

The reproduced data thus written is
After one horizontal scanning period, the read address generation circuit 603
According to the read addresses 667 and 668 where
The data is read from the memories 606 and 607 in synchronization with the 13.5 MHz clock. At this time, the read address 6
67 and 668 are addresses in the same order as the write addresses 164 and 165 in the first embodiment, as described later.

By setting the output of the upper memory 606 obtained as described above to the upper 8 bits and the output of the lower memory 607 to the lower 2 bits, a 10-bit 13.5 MHz signal is obtained.
A signal 669 obtained by time-division multiplexing two color difference signals of the second digital video signal is obtained. The division circuit 608 alternately divides the time-division multiplexed signal 669 for each clock, thereby obtaining 6.75 signals of 10 bits each.
Two digital color difference signals 655 and 656 of MHz are obtained. These two digital color difference signals 655,656
Are converted into analog signals by D / A converters 610 and 611, respectively, and unnecessary components are removed through low-pass filters 613 and 614 to obtain two analog luminance signals.

The write address generation circuit 602 and the read address generation circuit 603 use the reset signal 6 from the synchronization control circuit 601 to synchronize the video signal.
It is reset by 71,672. Synchronous control circuit 6
Reference numeral 01 uses the external video synchronization signal 650 as a reference to generate 13.5 MHz and 18 MHz clocks synchronized with the horizontal synchronization signal of the external video synchronization signal 650 and other necessary control signals. As a result, the entire decoding processing circuit is connected to the video synchronization signal 6 from the outside.
Synchronize with 50.

FIG. 9 shows an example of the operation timing of each section. This figure shows the process of decoding the luminance signal. As shown in FIG. 2, four clocks are encoded into a word composed of upper 8 bits and a clock is composed of words composed of lower 2 bits in a period of 5 clocks. 7 illustrates a case where a signal is decoded by the decoding circuit illustrated in FIG. 6. As shown in FIG. 9, the encoded reproduced data 651 is composed of words U0, U1, U2, U3 composed of upper 8 bits, and lower 2 bits L
Assume that a word consisting of 0, L180, L360, and L540 comes. This is the same order as the encoded output data of FIG. Therefore, words U0, U1, U2, U3. . . To write only the upper word, an upper word write address 660 as shown in FIG. 9 may be generated. This address is in the same order as the upper 8-bit read address in FIG.
To write only a word consisting of the lower 2 bits into the lower memory 605, the lower word write address 6
62 may be generated. This address is the lower 2 in FIG.
The order is the same as the bit read address.

In this manner, one line of valid data is stored in the upper memory 604 and the lower memory 605.
After writing in synchronization with the clock of 1 MHz, the written data is read out in synchronization with the clock of 13.5 MHz after one horizontal scanning period. At this time, data is read from the upper memory 604 in the order indicated by the upper 8-bit read address 665 as shown in FIG. This is the top 8
The order is the same as the bit write address. Data is read from the lower memory 605 in the order indicated by the lower 2-bit read address 666 as shown in FIG. The lower 2 bits read address 666 has the upper 8 bits indicating the address of an 8-bit word of the lower memory 605, and the lower 2 bits indicating which pair of the 2-bit pair in the 8-bit word is to be output. I have. This is the same order as the lower 2-bit write address in FIG. By reading as described above, the output of the upper memory 604 and the output of the lower memory 605 return to the original sample order of the second digital video signal as shown in FIG. Therefore, the luminance signal 654 of the second digital video signal can be obtained by setting the output of the upper memory 604 to the upper 8 bits and the output of the lower memory 605 to the lower 2 bits.

The operation of the upper memory 606 and the lower memory 607 for decoding the encoded reproduced color difference signal 652 is the same as described above.

FIG. 7 shows the detailed configuration of the upper memory 604. In the figure, a write address 660 and a read address 665 are alternately supplied to RAMs 707 and 708 line by line by address selection circuits 701 and 702. Each of the RAMs 707 and 708 has a capacity capable of storing one line of 8-bit data as in FIG.
By alternately switching between writing and reading for each line, a one-line delay is configured. Write 1
The sampling rate is converted by performing reading with a clock of 8 MHz and a clock of 13.5 MHz.

The same applies to the color difference signal upper memory 606. FIG. 8 shows a detailed configuration of the lower-order memory 605. In the figure, a write address 662 and a read address 666 correspond to address selection circuits 801 and 8.
02 is supplied alternately to the RAMs 807 and 808 line by line. RAMs 807 and 808 are each 1
It has the capacity to store 8 bits of data for one line.
By alternately switching between writing and reading for each line, a one-line delay is configured. 18 writes
Read at 13.5 MHz at a clock rate of 1 MHz
The conversion of the sampling rate is performed by using this clock.

The output data selected by the output selection circuit 809 is one of four sets of bit 0 and bit 1, bit 2 and bit 3, bit 4 and bit 5, and bit 6 and bit 7 by the selection circuit 810. By choosing
The lower two bits of the original digital sample are obtained.

The same applies to the lower-order memory 607 for the color difference signal.

[0065]

As described above, according to the present invention, the lower order (n-n) of an arbitrary sample in one line is obtained by using the lower order memory.
m) bits to form an m-bit word,
Even if an error of one word occurs in the process of recording / reproduction or transmission, it can be dispersed to discontinuous samples in one line after performing the decoding of the present invention. As a result, image quality degradation due to errors can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital video signal encoding processing device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a digital video signal encoding process according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a higher-order memory of the digital video signal encoding processor according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing the configuration of a lower-order memory of the digital video signal encoding apparatus according to the first embodiment of the present invention;

FIG. 5 is a block diagram illustrating a configuration of a synchronization control circuit of the digital video signal encoding apparatus according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a digital video signal decoding apparatus according to a second embodiment of the present invention;

FIG. 7 is a block diagram showing the configuration of an upper memory of a digital video signal decoding processor according to a second embodiment of the present invention;

FIG. 8 is a block diagram showing a configuration of a lower-order memory of a digital video signal decoding processor according to a second embodiment of the present invention;

FIG. 9 is a timing chart showing the operation of a digital video signal decoding process according to the second embodiment of the present invention;

[Explanation of symbols]

 108, 110, 604, 606 Upper memory 109, 111, 605, 607 Lower memory 112, 602 Write address generator 113, 603 Read address generator

Continuation of front page (58) Fields investigated (Int.Cl. ⁶ , DB name) G11B 20/12 H04N 5/92

Claims (2)

(57) [Claims] 1. Quantization with m bits (m> 0 integer)
For a first digital signal at a first clock rate
And a second clock quantized by n bits (an integer of n> m).
A device for processing the second digital signal at the lock rate
There, m is divisible by (n-m), and the quotient is f, the second
Upper m bits of each sample of the digital video signal
Is the upper sample, and the lower (nm) bits are the lower sample.
And the upper sample is a word composed of m bits,
While storing during the horizontal scanning period , the second clock
Write at the first clock rate and read at the first clock rate.
An upper memory to be output, and m lower bits each of which is composed of f lower samples.
As word stores for one horizontal period, the
Writing at a second clock rate, the first clock
A lower memory for reading at a rate, and a memory for writing the upper sample to the upper memory.
An upper write address and the lower sample
A write address generating circuit for generating a low-order write address for writing to use the memory, for reading a word consisting of m bits each memory for the upper from the lower memory and an upper read address and a lower read address generator A read address generating circuit to perform an output from the upper memory or an output from the lower memory.
And a higher order selection circuit for selecting either one, writing to the lower level memory, the m-bit words
Predetermined (nm) bits among them, and
Different words for each of the f lower samples
The reading from the lower-level memory is performed in accordance with the lower-order write addresses shown in FIG.
Lower read indicating an m-bit word consisting of
Address, and the upper and lower selection circuit
Output timing from the memory for
Switching at the first clock rate
A digital video signal processing device that obtains data of a word sequence of bits . 2. A digital video signal processing apparatus according to claim 1, wherein the first clock rate and the continuous clock rate are obtained.
An apparatus for processing data of a word string of bits , comprising: an upper memory for selectively storing only a word formed of an upper sample from the data of the word string for one horizontal scanning period ; And a lower memory for selectively storing only a word composed of lower samples for one horizontal scanning period, and a write address of an m-bit word to the upper memory and the lower memory. a write address generating circuit for, and a read address generating circuit for generating a read address of the lower sample from the upper sample of the read address and the lower memory from the memory for the upper, read from the memory for the higher The upper sample is defined as upper m bits, and the lower sample read from the lower memory is defined as lower (nm) bits. As the door, one of the n
Configure bit samples, processing apparatus in a digital video signal for decoding the second digital video signal.