JPH0437592B2 - - Google Patents

Info

Publication number
JPH0437592B2
JPH0437592B2 JP58027052A JP2705283A JPH0437592B2 JP H0437592 B2 JPH0437592 B2 JP H0437592B2 JP 58027052 A JP58027052 A JP 58027052A JP 2705283 A JP2705283 A JP 2705283A JP H0437592 B2 JPH0437592 B2 JP H0437592B2
Authority
JP
Japan
Prior art keywords
layer
amorphous silicon
doped amorphous
silicon layer
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58027052A
Other languages
Japanese (ja)
Other versions
JPS59154082A (en
Inventor
Tsutomu Nomoto
Akira Uchama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58027052A priority Critical patent/JPS59154082A/en
Publication of JPS59154082A publication Critical patent/JPS59154082A/en
Publication of JPH0437592B2 publication Critical patent/JPH0437592B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation

Description

【発明の詳細な説明】 (技術分野) 本発明は非晶質シリコン半導体より形成された
PIN型ホトダイオードの光感度向上に好適な光セ
ンサに関するものである。
[Detailed Description of the Invention] (Technical Field) The present invention relates to a semiconductor device formed from an amorphous silicon semiconductor.
The present invention relates to an optical sensor suitable for improving the photosensitivity of PIN type photodiodes.

(従来技術) 従来、この種光センサとして第1図に示すもの
があつた。第1図aは上記光センサの要部縦断面
図、同図bは第1図aのX−X線平面断面図であ
つて、図中、1はガラス基板又は石英基板から成
る透明絶縁基板、2は上記透明絶縁基板1上に、
例えば電子ビーム蒸着法により被着し、その後所
定のパターンにエツチング加工して成る透明電極
層で、例えばITO(In2O3+SnO2)などが用いら
れる。3は上記透明電極層2上に形成されたボロ
ン(B)ドーピング非晶質シリコン層(P型層)、
4は上記透明絶縁基板1及び上記Bドーピング非
晶質シリコン層(P型層)上に一段階状に形成さ
れたノンドープ非晶質シリコン層(I型層)、5
は上記ノンドープ非晶質シリコン層(I型層)4
上にその上面形状通りに形成されたPドーピング
非晶質シリコン層(N型層)、6は上記透明絶縁
基板1及び上記ドーピング非晶質シリコン層(N
型層)上に二段階状に形成された金属電極層(上
部電極)である。
(Prior Art) Conventionally, there has been a photo sensor of this type as shown in FIG. FIG. 1a is a longitudinal cross-sectional view of the main part of the optical sensor, and FIG. 1b is a cross-sectional view taken along the line X-X of FIG. , 2 are on the transparent insulating substrate 1,
For example, it is a transparent electrode layer formed by depositing by electron beam evaporation and then etching into a predetermined pattern. For example, ITO (In 2 O 3 +SnO 2 ) is used. 3 is a boron (B)-doped amorphous silicon layer (P-type layer) formed on the transparent electrode layer 2;
4 is a non-doped amorphous silicon layer (I-type layer) formed in one step on the transparent insulating substrate 1 and the B-doped amorphous silicon layer (P-type layer); 5;
is the above non-doped amorphous silicon layer (I-type layer) 4
6 is a P-doped amorphous silicon layer (N-type layer) formed on the transparent insulating substrate 1 and the doped amorphous silicon layer (N-type layer) formed according to the shape of its upper surface;
This is a metal electrode layer (upper electrode) formed in two stages on the mold layer).

上記構成を備えた従来の光センサの場合、その
製造過程において、まず透明絶縁基板1上に下部
電極として透明電極層2を電子ビーム蒸着法によ
り被着形成し、次に該透明電極層2上に風
100ppm程度の不純物としてポロン(B)のドー
ピングで数100〓程度の膜厚にBドーピング非晶
質シリコン膜3(P型層)を形成し、更に該P型
層3の上にノンドープの非晶質シリコン半導体層
4(I型層)を、そして更に該I型層4の上に数
100ppm程度の不純物としてリン(P)のドーピ
ングで膜厚が数100〓程度の非晶質シリコン層5
(N型層)を被着形成し、最後に上記N型層5の
上にAl,NiCr−Au等の金属より成る電極膜を上
部電極6として被着加工することにより下部電極
(ITO層)2−P型層3−I型層4−N型層5−
上部電極6なる構造を有する光センサが完成す
る。なお、上記P型層3、I型層4及びN型層5
は、それぞれ主成分ガスをシラン(SiH4)とし、
グロー放電法により連続あるいは分離して被着形
成される。
In the case of a conventional optical sensor with the above configuration, in the manufacturing process, first a transparent electrode layer 2 is formed as a lower electrode on a transparent insulating substrate 1 by electron beam evaporation, and then the transparent electrode layer 2 is deposited on the transparent insulating substrate 1 as a lower electrode. ni wind
A B-doped amorphous silicon film 3 (P-type layer) is formed to a thickness of about 100 μm by doping with poron (B) as an impurity of about 100 ppm, and then a non-doped amorphous silicon film 3 is formed on the P-type layer 3. a high quality silicon semiconductor layer 4 (I-type layer), and further on the I-type layer 4 several layers.
The amorphous silicon layer 5 is doped with phosphorus (P) as an impurity of about 100 ppm and has a thickness of about 100 mm.
(N-type layer), and finally, an electrode film made of metal such as Al, NiCr-Au, etc. is deposited on top of the N-type layer 5 as the upper electrode 6 to form a lower electrode (ITO layer). 2-P type layer 3-I type layer 4-N type layer 5-
An optical sensor having the structure of the upper electrode 6 is completed. Note that the P-type layer 3, I-type layer 4 and N-type layer 5
The main component gas is silane (SiH 4 ), and
It can be deposited continuously or separately by glow discharge method.

次に、動作について説明する。 Next, the operation will be explained.

この光センサは第1図aの矢符で示すごとく、
基板1側からの入射光強度に比例して上記PIN層
3,4,5の上記P型層3及びI型層4の間に形
成されたPI膜界面での空乏層幅が変化し、これ
に対して逆バイアスを印加することでのその変化
分を出力信号として係止するものである。しかし
ながら、上記の如き従来技術では、入射光が上記
Bドーピング非晶質シリコン層(P型層)3のB
ドーピング層中を通過する時に吸収されて弱くな
る為、上記PI膜界面に到達して上述の空乏層変
化に寄与する光量は、入射光のうちの微少な量で
あり、その結果この光センサの出力信号は微弱な
ものとなつて検出しずらいという問題点があつ
た。このような問題点を解決するためには、一般
にゲインの高い増幅器を必要とするものの、増幅
器のゲインを上げると周波数帯域を狭めることに
なり、今度は高速の光検出が不可能となるという
技術的な欠点があつた。
As shown by the arrow in Figure 1a, this optical sensor is
The width of the depletion layer at the PI film interface formed between the P-type layer 3 and I-type layer 4 of the PIN layers 3, 4, and 5 changes in proportion to the intensity of incident light from the substrate 1 side. The amount of change caused by applying a reverse bias to the output signal is fixed as an output signal. However, in the conventional technology as described above, the incident light is transmitted to the B-doped amorphous silicon layer (P-type layer) 3.
Since it is absorbed and weakened when passing through the doped layer, the amount of light that reaches the PI film interface and contributes to the above-mentioned depletion layer change is a minute amount of the incident light, and as a result, the There was a problem in that the output signal was weak and difficult to detect. To solve these problems, a high-gain amplifier is generally required, but increasing the gain of the amplifier narrows the frequency band, making high-speed optical detection impossible. There were some shortcomings.

(発明の目的) 本発明は上記の如き欠点を解除するためになさ
れたもので、入射光を効率よく上記PI膜界面に
到達させ、効率よく出力信号を得ることが出来る
光センサを提供することを目的としている。
(Object of the Invention) The present invention has been made in order to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide an optical sensor that allows incident light to efficiently reach the PI film interface and efficiently obtains an output signal. It is an object.

(実施例) 以下、本発明の二実施例を第2図及び第3図を
用いて説明する。
(Embodiments) Two embodiments of the present invention will be described below with reference to FIGS. 2 and 3.

第2図は本発明の第1の実施例を示すものであ
つて、同図aは光センサの平面図、同図bは第1
図aのY−Y線縦断面図である。
FIG. 2 shows a first embodiment of the present invention, in which FIG. 2a is a plan view of the optical sensor, and FIG.
FIG.

図において、7はSiH4とN2O、SiH4とNH3
主成分とする混合ガスをグロー放電法により被着
せしめたSiO、SiNより成る透明絶縁層であり、
この層を格子状にホトリソエツチングすることで
部分的欠陥部3a〜3pを形成する。そして、こ
れらの欠陥部3a〜3pにはボロンBドーピング
非晶質シリコン膜をグロー放電法により全面被着
した後、ホトリソエツチングにより加工する。こ
れにより、上記透明絶縁層7の部分的欠陥部3a
〜3pにBドーピング非晶質シリコン層(P型
層)が選択的に形成される。
In the figure, 7 is a transparent insulating layer made of SiO and SiN, which is coated with a mixed gas mainly composed of SiH 4 and N 2 O, and SiH 4 and NH 3 by a glow discharge method.
By photolithographically etching this layer in a lattice pattern, partial defects 3a to 3p are formed. Then, a boron B-doped amorphous silicon film is entirely deposited on these defective parts 3a to 3p by a glow discharge method, and then processed by photolithography. As a result, the partially defective portion 3a of the transparent insulating layer 7
A B-doped amorphous silicon layer (P-type layer) is selectively formed at ~3p.

以上のように構成された本発明の第1の実施例
によれば、第2図に示す如く、微小間隔の格子状
配置でBドーピング層を有する部分的欠陥部3a
〜3pを構成したことにより、該Bドーピング層
による光の吸収量を減少させてI型層4に到達す
る光量を増加させることが可能となり、その結
果、透明絶縁層7を通過した光により上記I型層
4で発生した電子一正孔対は、該I型層4の抵抗
値を減少させると共に、上記PI膜界面へも移動
し、PI膜界面の空乏層幅を好適に大きく変化さ
せることが出来るので、本光センサの出力信号は
従来のものよりも著しく大にすることが出来る。
According to the first embodiment of the present invention configured as described above, as shown in FIG.
By configuring . The electron-hole pair generated in the I-type layer 4 reduces the resistance value of the I-type layer 4, and also moves to the PI film interface, suitably greatly changing the depletion layer width at the PI film interface. Therefore, the output signal of this optical sensor can be made significantly larger than that of the conventional optical sensor.

次に、第3図は本発明の第2の実施例を示すも
のであつて、同図aは光センサの平面図、同図b
は第1図aのZ−Z線縦断面図である。
Next, FIG. 3 shows a second embodiment of the present invention, in which figure a is a plan view of the optical sensor and figure b is a plan view of the optical sensor.
1 is a longitudinal sectional view taken along the line Z-Z in FIG. 1a.

図において、8a〜3dは微小間隔の帯状にB
ドーピング層を有する透明絶縁層7の部分的欠陥
部である。
In the figure, 8a to 3d are B in the form of bands at minute intervals.
This is a partial defect in the transparent insulating layer 7 having a doped layer.

以上のように構成された本発明の第2の実施例
によれば、第3図に示す如く、Bドーピング層8
a〜8dが微小間隔の帯状に形成されたことによ
り、上述の第1の実施例と同様の効果をもたらす
ことが可能である。すなわち、PIN構造に逆バイ
アスを印加することで、入射光強度により変化す
る上記空乏層幅の変化分を出力信号として従来の
ものよりも大きく検出することが出来る。
According to the second embodiment of the present invention configured as described above, as shown in FIG.
Since a to 8d are formed in a strip shape with minute intervals, it is possible to bring about the same effect as in the first embodiment described above. That is, by applying a reverse bias to the PIN structure, the change in the width of the depletion layer, which changes depending on the intensity of the incident light, can be detected as an output signal in a larger amount than in the conventional case.

なお、本発明の第1及び第2の実施例において
開示された透明絶縁層7の部分的欠陥部にBドー
ピング層を設ける技術は、CF4+O2(5%)混合
ガスによるプラズマエツチングにより余分な部分
を除去することで、容易に上記部分的欠陥にBド
ーピング層3a〜3p、8a〜8dを形成するこ
とが可能であり、構造上特に問題となることはな
いのである。
Note that the technique of providing a B-doped layer in the partially defective portion of the transparent insulating layer 7 disclosed in the first and second embodiments of the present invention is to remove excess by plasma etching using a mixed gas of CF 4 +O 2 (5%). By removing such portions, the B-doped layers 3a to 3p and 8a to 8d can be easily formed in the partial defects, and there is no particular problem in terms of the structure.

(発明の効果) 以上説明した通り、本発明によれば、PIN構造
において透明電極層とノンドープの非晶質シリコ
ン層(I型層)との間にあつて透明絶縁層の部分
的欠陥部にBドーピング非晶質シリコン層(P型
層)を部分的に形成したので、光感度が著しく向
上するという利点が得られ、従つてゲインの高い
増幅器を必要とせずに高速の光検出が可能となる
ため、高速光センサ用として、また製造方法も容
易であることから大型のラインセンサ用として大
なる実用的効果を奏する。
(Effects of the Invention) As explained above, according to the present invention, in the PIN structure, a partial defect in the transparent insulating layer is formed between the transparent electrode layer and the non-doped amorphous silicon layer (I-type layer). Since the B-doped amorphous silicon layer (P-type layer) is partially formed, the advantage is that the photosensitivity is significantly improved, and therefore high-speed photodetection is possible without the need for a high-gain amplifier. Therefore, it has a great practical effect as a high-speed optical sensor, and because it is easy to manufacture, it can be used as a large line sensor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは従来例を示す光センサの要部縦断面
図、同図bは第1図aのX−X線平面断面図、第
2図aは本発明の第1の実施例による光センサの
平面図、同図bは第2図aのY−Y線縦断面図、
第3図aは本発明の第2の実施例による光センサ
の平面図、同図bは第3図aのZ−Z線縦断面図
である。 1……透明絶縁基板、2……透明電極層(下部
電極)、3……Bドーピング非晶質シリコン層
(P型層)、3a〜3p,8a〜8d……Bドーピ
ング非晶質シリコン層(P型層)が形成された透
明絶縁層の部分的欠陥部、4……ノンドープの非
晶質シリコン層(I型層)、5……Pドーピング
非晶質シリコン層(N型層)、6……金属電極層
(上部電極)、7……透明絶縁層。なお、図中、同
一符号は同一部分又は相当部分を示す。
FIG. 1a is a longitudinal cross-sectional view of a main part of a conventional optical sensor, FIG. 1b is a cross-sectional view taken along the line X-X of FIG. 1a, and FIG. A plan view of the sensor; FIG.
FIG. 3a is a plan view of an optical sensor according to a second embodiment of the present invention, and FIG. 3b is a vertical sectional view taken along the line Z--Z in FIG. 3a. 1... Transparent insulating substrate, 2... Transparent electrode layer (lower electrode), 3... B-doped amorphous silicon layer (P-type layer), 3a to 3p, 8a to 8d... B-doped amorphous silicon layer (P-type layer) is formed in the transparent insulating layer, 4... non-doped amorphous silicon layer (I-type layer), 5... P-doped amorphous silicon layer (N-type layer), 6...Metal electrode layer (upper electrode), 7...Transparent insulating layer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 1 透明電極層と、該透明電極層上に形成された
ボロン(B)ドーピング非晶質シリコン層と、該
Bドーピング非晶質シリコン層上に形成されたノ
ンドープの非晶質シリコン層と、該非晶質シリコ
ン層上に形成されたリン(P)ドーピング非晶質
シリコン層と、該Pドーピング非晶質シリコン層
上に形成された金属電極層とを少なくとも有する
光センサにおいて、部分的欠陥部を有する透明絶
縁層と該部分的欠陥部にBドーピング層を形成し
て成る層とを上記透明電極層と上記非晶質シリコ
ン層の間に設けたことを特徴とする光センサ。
1 a transparent electrode layer, a boron (B)-doped amorphous silicon layer formed on the transparent electrode layer, a non-doped amorphous silicon layer formed on the B-doped amorphous silicon layer, and a non-doped amorphous silicon layer formed on the B-doped amorphous silicon layer; In an optical sensor having at least a phosphorus (P)-doped amorphous silicon layer formed on a crystalline silicon layer and a metal electrode layer formed on the P-doped amorphous silicon layer, a partial defect portion is formed. A photosensor characterized in that a transparent insulating layer having the above-mentioned structure and a layer formed by forming a B-doped layer in the partially defective portion are provided between the transparent electrode layer and the amorphous silicon layer.
JP58027052A 1983-02-22 1983-02-22 Photosensor Granted JPS59154082A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58027052A JPS59154082A (en) 1983-02-22 1983-02-22 Photosensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58027052A JPS59154082A (en) 1983-02-22 1983-02-22 Photosensor

Publications (2)

Publication Number Publication Date
JPS59154082A JPS59154082A (en) 1984-09-03
JPH0437592B2 true JPH0437592B2 (en) 1992-06-19

Family

ID=12210296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58027052A Granted JPS59154082A (en) 1983-02-22 1983-02-22 Photosensor

Country Status (1)

Country Link
JP (1) JPS59154082A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61196570A (en) * 1985-02-25 1986-08-30 Hitachi Zosen Corp Amorphous silicon x-ray sensor
JPS61196572A (en) * 1985-02-25 1986-08-30 Hitachi Zosen Corp Amorphous silicon x-ray sensor
JP3213889B2 (en) 1998-11-13 2001-10-02 株式会社麻美亜 Tableware container

Also Published As

Publication number Publication date
JPS59154082A (en) 1984-09-03

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