JPH04373263A - Field compensation circuit for image processor - Google Patents

Abstract

PURPOSE:To prevent the fixation of field detection by the video signal at the time of inputting the video signal of nonstandard signal. CONSTITUTION:An input video signal detects a field and outputs the same field signal(FIELD). At the same time, a video processor provided with an IC circuit 1 dedicated to field discrimination, which outputs a vertical synchronizing signal(V.SYNC) is provided with an abnormal field detection part 2 detecting the fixation of field detection(detecting field abnormality) with the field signal and the vertical synchronizing signal, a self-running output part 3 generating an artificial field signal and a selector part 4 switching the field signal to the artificial signal by the detection of field abnormality. The signal switched by the selector part 4 is set to be the field detection of the image video processor. Thus, when the input video signal is a nonstandard signal, even if the field signal from the IC circuit 1 comes to fixation, the non-fixed artificial field signal can be set to be the field detection of the image processor and the fixation of field detection can be prevented.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] When converting an input video signal into a digital signal and writing it to a video memory, the present invention is capable of converting the digital video data to the odd field side and the even field side of the memory even if the input video signal is a non-standard signal. The present invention relates to a field compensation circuit for an image processing apparatus that allows writing to be performed separately.

0002

[Conventional example] Conventionally, in this type of image processing device, in order to write a digital video signal of an input video signal (video signal) into an odd field and an even field, a field detection circuit is provided to detect the field of the video signal. There is.

On the other hand, from the viewpoint of miniaturization of equipment or reliability of products, equipment circuits have become integrated into ICs, and even in the above-mentioned field detection circuit, the input video signal (
An IC circuit dedicated to field discrimination has been proposed, which detects the field of the video signal when a video signal is input, and outputs a vertical synchronization signal (V.SYNC) and a field signal (FIELD) at a predetermined timing.

0004

[Problems to be Solved by the Invention] Incidentally, in the above image processing apparatus equipped with an IC circuit dedicated to field discrimination, there is no problem when the input video signal is a standard signal, but when the input video signal is a non-standard signal, such as a VTR device. CUE/RE
In the case of a video signal during V operation, an abnormal field may be detected, that is, an IC circuit dedicated to determining the field may malfunction, and the output field signal (FIELD) may be fixed.

[0005] Then, a problem arises in that the input video signal is written only into either the memory on the odd field side or the memory on the even field side of the video memory.

The present invention was made in view of the above problems, and its purpose is to obtain a field signal that allows the input video signal to be written to the odd field side and the even field side even if the input video signal is a non-standard signal. It is an object of the present invention to provide a field compensation circuit for an image processing device that is capable of performing the following steps.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention detects a field based on the video signal when writing digital video data of an input video signal into a video memory, and by this detection, the field signal ( FI
ELD) and also outputs a vertical synchronization signal (V.SY
In an image processing device equipped with an IC circuit dedicated to field discrimination that outputs NC), the level of the field signal is fixed at least for two pulses of the vertical synchronization signal due to the timing of the field signal and the vertical synchronization signal. At this time, an abnormal field detection unit detects an abnormality in the detection of the field, a free-running field output unit generates a pseudo field signal based on the vertical synchronization signal, and a detection signal from the abnormal field detection unit detects the field signal and its value. A selector section is provided for switching between the pseudo field signal from the free-running field output section, and the video signal can be written into the odd field and even field of the video memory by the field signal or pseudo field signal switched by the selector section. The summary is what was done.

[0008]

[Operation] With the above configuration, when the input video signal is a non-standard signal and the field detection based on the video signal is not fixed, that is, when the abnormal field detection section does not detect a field abnormality, the above The selector section is switched to the IC circuit side dedicated to field discrimination. Normal field signal (FIE) from that IC circuit
LD) is set to field detection of the image processing device.

By the way, when the input video signal is a non-standard signal and field detection based on the video signal becomes fixed, the selector section is switched from the IC circuit side to the free-running field output section side. At this time, since a pseudo field signal is generated in the free-running field output section, this pseudo field signal is used for field detection by the image processing apparatus.

[0010] This makes it possible to prevent the field detection of the image processing device from becoming fixed when a non-standard video signal is input. It becomes possible to write to the field.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be explained based on FIGS. 1 and 2. In FIG. 1, the field compensation circuit of this image processing device includes an IC circuit 1 dedicated to field discrimination similar to the conventional one, and an IC circuit 1 dedicated to field discrimination.
The clock is the vertical synchronization signal (V.SYNC) from
An abnormal field detection section 2 that detects an abnormality in the field signal (FIELD) from the IC circuit 1, a free-running field output section 3 that generates a pseudo field signal based on the vertical synchronization signal, and an abnormal field detection section 2 that detects abnormality in the field signal (FIELD) from the IC circuit 1; A selector section (switching means) 4 is provided which switches between the field signal from the IC circuit 1 and the pseudo field signal from the free-running field output section 3 in response to a field abnormality detection signal, and outputs a new field signal.

Note that the vertical synchronization signal (V.SYNC) and field signal (FIEL) output from the IC circuit 1
D) has the timing shown in FIGS. 2(a) and 2(b).

Further, the test point TP1 is for extracting the above-mentioned field abnormality detection signal, and the test point TP2 is for extracting the above-mentioned pseudo field signal.

[0014] The abnormal field detection section 2 detects the
A first flip-flop (D-type F/F) circuit 2 that uses the vertical synchronization signal from the circuit 1 as a clock and latches the field signal (FIELD) from the IC circuit 1.
a, the signal from the inverted Q output of this first F/F circuit, and the field signal.
R circuit 2b and a second flip-flop (D type F/F) which uses its vertical synchronization signal as a clock, latches the output of its exclusive 2OR circuit 2b, and uses its Q output as an abnormality detection signal for the above field. It is equipped with a circuit 2c.

[0015] The self-propelled field output unit 2 is connected to the IC
A third flip-flop (D-type FF
) is a circuit.

Next, the operation of the image processing apparatus equipped with the field compensation circuit configured as described above will be explained with reference to the time chart shown in FIG.

First, a video signal (video signal) to be processed is input to the image processing device, and this video signal is input to the IC circuit 1 dedicated to field discrimination. It is assumed that a synchronization signal (V.SYNC) and a field signal (FIELD) have been obtained.

At this time, if the input video signal is a standard signal, a normal field signal is output from the IC circuit 1, and this field signal is sent to the first F/F circuit 2a at the rising edge of the vertical synchronizing signal. Latched. and,
At the time of the next vertical synchronization signal, the inverted Q output of the first F/F circuit 2a and the current output field signal are at the same level (“H”).
or “L”), exclusive 2OR circuit 2
b is at the "L" level, and the second F.F circuit 2c
The "L" level is latched.

When the "L" level detection signal is output, the selector section 4 selects the field signal (FIELD).
) side, the field signal output from the IC circuit 1 is detected by the field of the image processing device (shown in (e) of the same figure), and by this field detection, the digital video data of the input video signal is are written to the odd field side and even field side of the video memory.

Here, if the input video signal is a non-standard signal, the IC circuit 1 may malfunction due to the malfunction of the IC circuit 1.
When the field output of is fixed, for example, the field signal is fixed at the "L" level (as shown in FIG. The "L" level is also latched at the timing of the next vertical synchronization signal.

Therefore, at the time of the vertical synchronization signal, the output of the exclusive 2OR circuit 2b becomes "H" due to the "H" level of the inverted Q output of the first F/F circuit 2a and the "L" level of the current field signal. Since this "H" level is latched by the second F/F circuit 2c at the rising edge of the vertical synchronizing signal, a field abnormality is detected.

When the "H" level abnormality detection signal is output, the selector section 4 outputs the free-running field output section 3.
Can be switched to the side. At this time, as shown in FIG. 4(d), in the free-running field output unit 3, a pseudo field signal is generated according to the output vertical synchronization signal (V.SYNC) of the IC circuit 1. The pseudo field signal is sent to the selector section 4 for field detection in the image processing apparatus (as shown in FIG. 4(e)).

As is clear from the figure (d), the timing of the pseudo field signal generated in the free-running field output unit 3 is different from that from the IC circuit 1 when the standard video signal is input. Output field signal (FI
ELD). Therefore, even if the pseudo field signal is detected as a field by the image processing apparatus, no problem will arise.

[0024] Furthermore, when the field signal (FIELD) from the IC circuit 1 dedicated to field discrimination returns to normal, the same operation as when the video signal of the above-mentioned standard signal is input is performed. The explanation will be omitted.

In this way, by using the output vertical synchronization signal of the IC circuit 1 dedicated to field discrimination, a pseudo field signal having the same timing as the output field signal (FIELD) of the IC circuit 1 is generated, and the output field signal It detects whether or not the field signal is fixed, that is, whether or not the field signal is abnormal. Based on this detection result, the output field signal of the IC circuit 1 and the pseudo field signal are switched to switch the output field signal and the pseudo field signal of the image processing device. Since it uses field detection, even if the input video signal is a non-standard signal,
Field detection can be prevented from becoming fixed,
In other words, since abnormal field output is prevented, it becomes possible to reliably write the non-standard video signal to the odd field side and the even field side of the video memory.

Although the above embodiment has a hardware circuit configuration, at least the abnormal field detection section 2
It is also possible to perform the self-propelled field output section 3 by software processing of a microcomputer.

In this case, for example, the output vertical synchronizing signal (V.SYNC) and the output field signal (FIELD) of the IC circuit 1 dedicated to field discrimination are input to the input port of the microcomputer, and the vertical synchronizing signal and field signal are input to the input port of the microcomputer. What is necessary is to detect the pulses, generate a pseudo field signal based on their timing, and detect an abnormality in the field signal.

In the above embodiment, the fall of the output vertical synchronization signal (V.SYNC) of the IC circuit 1 dedicated to field discrimination coincides with the fall and rise timings of the output field signal (FIELD).
They don't have to match.

[0029]

As described above, the field compensation circuit of the present invention detects a field based on an input video signal, and outputs the detected field signal as well as a field discrimination circuit that outputs a vertical synchronization signal. An image processing device equipped with an IC circuit includes an abnormal field detection section that detects fixation of the field detection, that is, detects field abnormality, using a field signal from the IC circuit, and a pseudo field signal using the vertical synchronization signal. The present invention includes a free-running field output section that generates a field, and a selector section that switches the field signal from the IC circuit to the pseudo field signal based on the abnormality detection signal of the field, so that if the input video signal is a non-standard signal, Since the pseudo field signal is used for field detection in the image processing device instead of the field signal from the IC circuit, it is possible to prevent the field detection from being fixed, and the video signal is transferred to the odd field side of the video memory.
This has the effect that it is possible to write to both fields on the even field side.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a field compensation circuit of an image processing device showing an embodiment of the present invention.

FIG. 2 is a time chart diagram explaining the operation of the field compensation circuit of the image processing device shown in FIG. 1;

[Explanation of symbols]

1 IC circuit dedicated to field discrimination 2 Abnormal field detection section 2a First flip-flop circuit 2b Exclusive 2-OR circuit 2c Second flip-flop circuit 3 Free-running field output section 4 Selector section (switching means)

Claims (1)

[Claims] Claim 1: When writing digital video data of an input video signal to a video memory, a field is detected based on the video signal, and this detection causes the field signal (F
IELD) and the vertical synchronization signal (V.SYN
In the image processing apparatus that obtains C), an abnormality in the detection of the field is detected when the level of the field signal is fixed at least for two pulses of the vertical synchronization signal based on the timing of the field signal and the vertical synchronization signal. an abnormal field detection means, a free running field output means for generating a pseudo field signal based on the vertical synchronization signal, and a detection signal from the abnormal field detection means to generate the field signal and the pseudo field signal from the free running field output means. A field of an image processing device, comprising a switching means for switching between the two, and the video signal can be written into an odd field or an even field of the video memory by a field signal or a pseudo field signal switched by the switching means. Compensation circuit.