JPH04372219A - Cmos output circuit - Google Patents

Abstract

PURPOSE:To reduce unwanted radiation by eliminating a through-current in the CMOS output circuit. CONSTITUTION:The output circuit employs two inverters 1, 2 and a delay circuit 4 whose delay time differs from each other with respect to an input signal from an internal circuit. Output signals of the two inverters is inputted to gates of output transistors(TRs) 5, 6 through a selector 3 employing a control signal obtained by the delay circuit. Either of the output TRs keeps OFF state at all times at the switching and no through-current is caused. Thus, the output circuit without any through-current at the switching is formed and spurious radiation is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to a CMOS output circuit that eliminates through-current and reduces unnecessary radiation.

0002

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional CMOS output circuit. In the figure, 7 is an inverting element that inverts the input signal from the internal circuit, and 5 and 6 are inverting elements. The signal output from the inverting element 7 is input to the gate, and depending on the level of the input signal, one of them turns ON. These are a P-channel output transistor and an N-channel output transistor that perform external driving. FIG. 4 shows a timing chart of the circuit shown in FIG. M is an input signal, I is an inverted signal obtained by inverting the input signal M by the inverting element 7, J is an output signal when either of the output transistors 5 and 6 is driven by inputting the inverted signal 7 to the gate, K is a through current that flows when the drive state of the output transistors 5 and 6 is switched from one output transistor to the other.

Next, the operation will be explained. First, when the input signal M from the internal circuit is at the L level, an H level signal is input to the gate of the output transistor via the inverting element 7. At this time, P-channel output transistor 5 is in an off state, and N-channel output transistor 6 is in an on state. Therefore, an L level signal is output. Here, when the input signal M changes from L level to H level, the inverted signal I changes from H level to L level, P channel output transistor 5 changes from off state to on state, and at the same time, N channel output transistor 6 also turns on. state to off state. Output signal J is driven by P-channel output transistor 5 and changes from L level to H level. A through current K flows in the transition state of these two output transistors 5 and 6. Further, a similar process is followed when the input signal M changes from the H level to the L level.

0004

[Problems to be Solved by the Invention] Since the conventional output circuit is configured as described above, during switching, the P-channel output transistor and the N-channel output transistor are simultaneously in a transition state, and a very large through current flows. There was a problem that radiation occurred.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a CMOS output circuit that can eliminate through current during switching and reduce unnecessary radiation.

[0006]

[Means for solving the problem] CMOS according to the present invention
The output circuit consists of two inverters with different operating speeds, the signal lines of the internal circuits being connected to the input terminals, the outputs of the two inverters being connected to the input terminals, and the two outputs being selected depending on the signal level of the internal circuits. A selector means, a delay circuit that delays a signal of an internal circuit and outputs the delayed signal to the selector means as a control signal, two output terminals of the selector means are each connected to an input gate, and a cascade connection is made. The device is equipped with a P-channel output transistor and an N-channel output transistor.

[0007]

[Operation] The CMOS output circuit according to the present invention generates two signals with different timings using inverter means having different operating speeds for one input signal, and outputs these two signals using selector means as a P-channel output. Since input is made to the gates of the transistor and the N-channel output transistor at a timing when both transistors are not in a transition state at the same time, it is possible to eliminate through current when outputting a signal and reduce unnecessary radiation.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is an inverter that inverts an input signal after a delay time D1 and outputs an inverted signal, 2 is an inverter that inverts an input signal after a delay time D2 that is greater than the delay time D1, and outputs an inverted signal, and 3 is an inverter that outputs an inverted signal after a delay time D2 greater than the delay time D1. A selector connects the output signals of two inverters 1 and 2 to two output terminals according to a control signal, and 4 connects the input signal to the two output terminals by a delay time D
2 a delay circuit that outputs with a larger delay time D4 and creates a control signal for the selector 3; 5 is the output signal 1 of the selector;
6 inputs the other output signal of the selector to the gate, and 6 inputs the other output signal of the selector to the gate, and turns off when this output signal is H level, and drives and outputs the H output level when it is L level. , this output signal is L
It is an N-channel output transistor that is turned off when the level is high, and drives an L output when the level is high. The selector 3 has input terminals a, b, output terminals c, d, and a control terminal e. When the input to the control terminal e is at L level, the input terminal a becomes the output terminal c, and the input terminal b is selected to be connected to the output terminal d, and when the input to the control terminal e is at H level, the input terminal a is connected to the output terminal d.
Assume that the element is selected so that the input terminal b is connected to the output terminal c.

FIG. 2 shows a timing chart of signals from point A to point G shown in FIG. By the way, in Figure 2, A
is an input signal from the internal circuit, B is an inverted signal obtained by inverting the input signal A by inverter 1 having the characteristic of delay time D1, and C is the inverter 2 having the characteristic of delay time D2.
D is the inverted signal obtained by inverting the input signal A, and D is the delay circuit 4.
Therefore, input signal A becomes D4, a delayed control signal to selector 3, E is a signal output from output terminal c of selector 3, F is a signal output from output terminal d of selector 3, G
is a signal output from the output transistor 5 or 6 when E or F is input to the gate of the output transistor 5 or 6, respectively.

Next, the operation will be explained. H level input signal A is sent from the internal circuit to inverter 1, inverter 2,
When input to the delay circuit 4, an inverted L level signal is output from the two inverters 1 and 2, and the signal is input to the delay circuit 4.
Also outputs an L level signal. At this time, the control signal D of the selector 3 is at the L level, so the L level of the signal C is outputted to the output terminal c of the selector 3, and the L level of the signal B is outputted to the output terminal d. Therefore, in this state, N
Channel output transistor 6 is turned off, P-channel output transistor 5 is turned on, and an H level is output.

[0011] Here, the internal circuit signal changes from H level to L level.
When the level changes, after delay time D1, inverter 1
The output signal B changes from L level to H level, and the input signal E input to the gate of P channel output transistor 5 through selector 3 similarly changes from L level to H level. Therefore, the output transistor 5 transitions from the drive state to the off state. At this time, N-channel output transistor 6
Since the output signal G also maintains the off state, the output signal G changes from the H level to the high impedance state. Eventually, after a delay time D2, the output signal of inverter 2 also changes from L level to H level.
The input signal to the gate of the N-channel output transistor 6 through the selector 3 also changes from the L level to the H level, and the output transistor 6 changes from the OFF state to the ON state. Here, the output signal G changes from a high impedance state to an L level. In this way, while the input signal A from the internal circuit changes from the H level to the L level and the output signal G changes from the H level to the L level, one of the two output transistors is always in the off state. Therefore, no through current will flow. Next, after a delay time D4 after the input signal A from the internal circuit changes from the H level to the L level, the output signal of the delay circuit 4, that is, the control signal D of the selector 3 changes from the L level to the H level.
Change to level. Therefore, the output signal E of the selector 3 is selected to be connected to the output C of the inverter 2, and the output signal F is selected to be connected to the output B of the inverter 1. At this time, the output signals E and F of the selector both remain at the H level and do not change. In this state, when the input signal from the internal circuit changes from L level to H level, the delay time D1
Thereafter, the output signal of the inverter 1 changes from the H level to the L level, and the input signal F of the N-channel output transistor 6 similarly changes from the H level to the L level through the selector. Therefore, the output transistor 6 transitions from the drive state to the off state. During this transition, P-channel output transistor 5 maintains an off state. Here, the output signal G changes from the L level to a high impedance state. Furthermore, after delay time D2, the output signal of inverter 2 also changes from H level to L level, and passes through the selector to P
The input signal to the gate of channel output transistor 5 is also high.
The level changes from the level to the L level, and the output transistor 5 changes from the off state to the on state. Therefore, the output signal G is high.
Changes from impedance to H level. even here,
While the input signal A from the internal circuit changes from L level to H level and the output signal G changes from L level to H level, one of the two output transistors is always in the off state. Therefore, no through current flows.

Regarding the timing of circuit delay times in this output circuit, the delay times of the output transistors are τp for transistor 5 and τ for transistor 6.
n, then under the conditions of τp < D2 - D1 τn < D2 - D1, there is no through current during switching of the output transistor. Further, under the conditions of τp <D4 −D2 τn <D4 −D2, the influence of noise due to switching of the selector 3 can be almost ignored.

[0013]

[Effects of the Invention] As described above, according to the present invention, by always keeping either the P-channel output transistor or the N-channel output transistor in the OFF state, it is possible to eliminate unnecessary through current during switching. This has the effect of providing a CMOS output circuit with less radiation.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an output circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a circuit configuration diagram of a conventional output circuit.

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

[Explanation of symbols]

1 Inverter 2 Inverter 3 Selector 4 Delay circuit 5 P-channel output transistor 6 N-channel output transistor

Claims (1)

[Claims] 1. In a CMOS output circuit, two inverters with different operating speeds are connected to input terminals of internal circuit signal lines, outputs of the two inverters are connected to respective input terminals, and the two outputs are connected to the internal circuit. a delay circuit that delays a signal in an internal circuit and outputs the delayed signal to the selector means as a control signal; 1. A CMOS output circuit comprising a P-channel output transistor and an N-channel output transistor connected in cascade.