JPH04371020A - Output circuit - Google Patents

Abstract

PURPOSE:To eliminate a through current from a high power source to a low power source, to reduce the power consumption and to reduce the noise. CONSTITUTION:PMOS and NMOS transistors TRs 1 and 2 are connected in series between the high power source VCC and to low power source GND, and an output terminal 3 is provided between both TRs 1 and 2. An input signal IN and the signal obtained by inverting the output signal SG 4 of a NOR circuit 12 by a NOT circuit 14 are inputted to a HAND circuit 11, and an output signal SG3 is supplied to the gate terminal of the PMOS TR 1. The input signal IN and the signal obtained by inverting the output signal SG3 of the NAND circuit 11 by a NOT circuit 13 are inputted to the NOR circuit 12, and an output signal, SG4 is supplied to the gate terminal of the NMOS TR 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to an output circuit including PMOS and NMOS transistors connected in series as final stage transistors. In recent years, semiconductor integrated circuits are required to have lower power consumption and lower noise. Therefore, it is necessary to eliminate the through current in the output circuit.

0002

2. Description of the Related Art A conventional output circuit is shown in FIG. Power supply VC
PMOS and NMOS transistor 1 are connected between C and GND.
, 2 are connected in series, and an output terminal 3 is provided between the PMOS and NMOS transistors 1 and 2. NAN
The D circuit 4 inputs an external input signal IN and a control signal C bar inverted by the NOT circuit 6, and outputs both signals IN,
An output signal SG1 based on the level of C bar is supplied to the gate terminal of the PMOS transistor 1. Further, the NOR circuit 5 receives the input signal IN and the control signal C.
is input, and an output signal SG2 based on the levels of both signals IN and C is supplied to the gate terminal of the NMOS transistor 2.

In this output circuit, when the control signal C is at a high level, the output signal SG1 is at a high level and the output signal SG2 is at a low level.
Both OS transistors 1 and 2 are turned off, and the output terminal 3 enters a high impedance state. Furthermore, when the control signal C is at a low level, the control signal C bar of the NOT circuit 6 is at a high level, so the output signal SG1 of the NAND circuit 4 is at a level that is the inversion of the input signal IN, and the output signal SG2 of the NOR circuit 5 is The level also becomes the inverted level of the input signal IN. Therefore, when the level of the input signal IN is fixed, only one of the MOS transistors is turned on, the output terminal 3 becomes an output state, and a high or low level output signal OUT is output.

0004

However, in the output circuit shown in FIG. 6, when the level of the input signal IN changes while the control signal C is in a low level output state, the output signals SG1 and SG2 change at the same timing. , P.M.
There is a period in which the OS and NMOS transistors 1 and 2 are turned on simultaneously, and a through current flows from the high power supply VCC to the low power supply GND via both transistors 1 and 2. There is a problem that power consumption increases due to this through current, and there is also a problem that noise is generated due to the through current.

The present invention has been made to solve the above-mentioned problems, and it is possible to reduce power consumption by eliminating the through current from a high power source to a low power source, and also to reduce noise. The purpose is to be able to

[0006]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the first invention. PMO between high power supply VCC and low power supply GND
S and NMOS transistors 1 and 2 are connected in series,
An output terminal 3 is provided between the PMOS and NMOS transistors 1 and 2.

[0007] An input signal IN from the outside is input to the NAND circuit 11, and the output signal SG4 of the NOR circuit 12 is inverted and input by the second NOT circuit 14, and the NAND circuit 11 receives the output signal SG3. PMOS
Supplied to the gate terminal of transistor 1. NOR circuit 1
2 receives the input signal IN, and the first NO.
The T circuit 13 inverts and inputs the output signal SG3 of the NAND circuit 11, and the NOR circuit 12 receives the output signal S.
G4 is supplied to the gate terminal of NMOS transistor 2.

Further, in the second invention, a control signal for setting the output terminal in an output state or a high impedance state is input to the NOR circuit, and the same control signal is input to the NAND circuit via the third NOT circuit. did. Furthermore, the third
In the invention, a control signal C for setting an output terminal in an output state or a high impedance state is input to the NAND circuit, and the same control signal is input to the NOR circuit via the fourth NOT circuit.

[0009]

[Operation] Therefore, according to the first invention, after the output signal SG4 of the NOR circuit 12 changes from high level to low level based on the change of the input signal IN from low level to high level, as shown in FIG. , the output signal SG3 of the NAND circuit 11 changes from high level to low level. or,
After the output signal SG3 of the NAND circuit 11 changes from low level to high level based on the change of the input signal IN from high level to low level, the output signal SG4 of NOR circuit 12 changes from low level to high level. Therefore, the PMOS and NMOS transistors 1 and 2 are not turned on at the same time, and a through current between the high power supply VCC and the low power supply GND is prevented.

Further, according to the second invention, when the control signal is set to high level, the output signal of the NOR circuit becomes low level regardless of the input signal, and the third NOT
A low level control signal is input to the circuit, and its output signal becomes high level regardless of the input signal. Therefore, both the PMOS and NMOS transistors are turned off, and the output terminal becomes a high impedance state.

Furthermore, according to the third invention, when the control signal is set to low level, the output signal of the NAND circuit becomes high level regardless of the input signal, and the NOR circuit has a fourth NAND signal.
A high-level control signal is input to the T circuit, and its output signal becomes a low level regardless of the input signal. Therefore, both the PMOS and NMOS transistors are turned off, and the output terminal becomes a high impedance state.

0012

[Example] Hereinafter, a third example embodying the present invention will be described.
This will be explained according to Figure 4. For convenience of explanation, the same components as in FIGS. 1 and 2 will be described with the same reference numerals. As shown in Figure 3, P is connected between the high power supply VCC and the low power supply GND.
MOS and NMOS transistors 1 and 2 are connected in series, and an output terminal 3 is provided between the PMOS and NMOS transistors 1 and 2.

The NAND circuit 11 receives an input signal IN from the outside and an output signal SG4 of the NOR circuit 12.
A signal SG4 bar which is inverted by the T circuit 14 and a control signal C bar which is the control signal C which is inverted by the third NOT circuit 15 are input. Then, the NAND circuit 11 outputs an output signal SG3 based on the levels of these three signals as PM.
Supplied to the gate terminal of OS transistor 1.

The NOR circuit 12 also receives the input signal IN.
and output signal SG3 of the NAND circuit 11 to the first NOT
The signal SG3 bar inverted by the circuit 13 and the control signal C
is entered. Then, the NOR circuit 12 outputs an output signal SG4 based on the levels of these three signals to the NMOS
Supplied to the gate terminal of transistor 2. Therefore, in the output circuit configured as described above, when the control signal C is at a low level as shown in FIG. 4, the control signal C bar of the third NOT circuit 15 is at a high level, so that the NAN
The level of the output signal SG3 of the D circuit 11 is equal to the level of the three signals IN
, SG4 bar, and C bar levels. Further, when the control signal C is at a low level, the level of the output signal SG4 of the NOR circuit 12 is determined by the levels of the signals IN and SG3.

That is, as shown in FIG. 4, in a steady state where the control signal C is at a low level and the input signal IN is fixed at a low level, the output signal SG3 is at a high level, and the signals IN, SG3 and C are at a high level. Since the bar is at a low level, the output signal SG4 is also at a high level. As a result, the PMOS transistor 1 is turned off and the NMOS transistor 2 is turned on, so that the output terminal 3 outputs a low-level output signal OUT.

Next, when the input signal IN changes from a low level to a high level, first, the output signal SG4 of the NOR circuit 12 changes from a high level to a low level only by this change in the input signal IN, and the NMOS transistor 2 changes from a high level to a low level. Turn off. On the other hand, the output signal SG3 of the NAND circuit 11 does not change only when the input signal IN changes from low level to high level, and is held at high level, and the PMOS transistor 1 remains off.

Then, as the output signal SG4 changes from high level to low level, that is, the signal SG4 bar changes from low level to high level, the output signal SG3 changes from high level to low level, and the PMOS transistor 1 In order to turn it on, a high level output signal OUT is output from the output terminal 3. After this, when the input signal IN changes from high level to low level, first, the output signal SG3 of the NAND circuit 11 changes from low level to high level only by this change in input signal IN, and the PMOS
Transistor 1 turns off. On the other hand, the output signal SG4 of the NOR circuit 12 does not change only when the input signal IN changes from high level to low level, and is held at low level.
NMOS transistor 2 remains off.

Then, as the output signal SG3 changes from low level to high level, that is, the signal SG3 bar changes from high level to low level, output signal SG4 changes from low level to high level, and the NMOS transistor 2 In order to turn it on, the output terminal 3 outputs a low level output signal OUT again. Further, as shown in FIG. 4, when the control signal C is at high level, the low level signal C bar is input to the NAND circuit 11, so the output signal S
G3 becomes a high level regardless of other signals IN and SG4, and the NOR circuit 12 receives a high level control signal C.
is input, so the output signal SG4 is different from other signals IN and S
It becomes a low level regardless of the G4 bar. For this reason, PM
Both the OS and NMOS transistors 1 and 2 are turned off, and the output terminal 3 enters a high impedance state.

As described above, according to this embodiment, since there is no period in which the PMOS transistor 1 and the NMOS transistor 2 are simultaneously turned on, a through current flows from the high power supply VCC to the low power supply GND via the PMOS and NMOS transistors 1 and 2. does not flow, making it possible to reduce power consumption and reduce noise. Further, according to this embodiment, the output terminal 3 can be switched to the output state by setting the control signal C to a low level, and the output terminal 3 can be switched to a high impedance state by setting the control signal C to a high level.

FIG. 5 shows another example of the output circuit, in which the NA
This embodiment differs from the embodiment shown in FIG. 3 in that the control signal C is supplied to the ND circuit 11 as is, and the control signal C is supplied to the NOR circuit 12 via the fourth NOT circuit 16.
Other configurations are the same. Therefore, in this example, the output terminal 3 can be switched to an output state by setting the control signal C to a high level, and the output terminal 3 can be switched to a high impedance state by setting the control signal C to a low level.

[0021]

[Effects of the Invention] As detailed above, according to the first invention,
By eliminating the through current from the high power source to the low power source, it is possible to reduce power consumption and also to reduce noise. Further, according to the second and third aspects of the invention, the output circuit can be switched between the output state and the high impedance state using the control signal.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a diagram explaining the principle of the present invention.

FIG. 3 is a circuit diagram showing one embodiment.

FIG. 4 is a waveform diagram showing the operation of one embodiment.

FIG. 5 is a circuit diagram showing another example.

FIG. 6 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1 PMOS transistor 2 NMOS transistor 3 Output terminal 11 NAND circuit 12 NOR circuit 13-16 1st-4th NOT circuit C control signal GND Low power supply IN Input signal SG3, SG4 output signal VCC high power supply

Claims (3)

[Claims] [Claim 1] High power supply (VCC) and low power supply (GND)
), and an output terminal (3) provided between the PMOS and NMOS transistors (1, 2), and an external input signal (IN). , the PMOS transistor (
NA that supplies the output signal (SG3) to the gate terminal of 1)
Inputting the ND circuit (11) and the input signal (IN),
a NOR circuit (12) that supplies an output signal (SG4) to the gate terminal of the NMOS transistor (2);
a first NOT circuit (
13) and the output signal (SG4) of the NOR circuit (12)
) and a second NOT circuit (14) that inverts the signal and inputs the inverted signal to the NAND circuit (11). 2. A control signal (C) for setting the output terminal (3) in an output state or a high impedance state is applied to the NO
In addition to inputting the R circuit (12), the same control signal (C)
2. The output circuit according to claim 1, wherein the output signal is input to the NAND circuit (11) via a third NOT circuit (15). 3. A control signal (C) for setting the output terminal (3) in an output state or a high impedance state is transmitted to the NA
In addition to inputting the ND circuit (11), the same control signal (C
) is input to the NOR circuit (12) via a fourth NOT circuit (16).