JPH04372169A - Master slice lsi - Google Patents

Abstract

PURPOSE:To eliminate a timing error generated after disposing and wiring without new disposing and wiring in a flip-flop of a master slice LSI. CONSTITUTION:Macro cells 4, 5, 6 respectively have flip-flops 2a, 2b, 2c and delay elements 3a, 3b, 3c. The delay values of the elements 3a, 3b, 3c are different. The positions of terminals of the cells 4, 5, 6 are the same, and formed of the same number of basic cells. Accordingly, even if not newly disposed and wired, a timing error can be easily eliminated by replacing with a macro cell having a delay element of a suitable delay value.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention applies to master slice LSI
In particular, it relates to circuits that require timing adjustment.

0002

2. Description of the Related Art FIG. 2 is a block diagram showing a flip-flop 1, which is a macro cell constituting a conventional master slice LSI, and is provided with a data input terminal D, a clock input terminal T, and an output terminal Q. Conventional master slice LS
In I, such a macro cell is composed of the minimum necessary number of transistors and has a unique layout pattern.

0003

[Problems to be Solved by the Invention] Conventional master slice LSIs are composed of such macrocells, and if a timing error is discovered by simulation after placement and routing and timing adjustment needs to be performed, each macrocell must be has a unique layout pattern, which poses problems such as the need to perform placement and wiring again and insert new delay elements.

The present invention was made to solve the above-mentioned problems, and its purpose is to obtain a master slice LSI that can eliminate timing errors discovered after placement and routing without performing placement and routing again. do.

[0005]

A master slice LSI according to the present invention includes a plurality of macro cells, and each macro cell includes an output terminal and a plurality of terminals including the output terminal. The plurality of terminals are located at the same position in each macro cell, and each macro cell has the same number of basic cells. Furthermore, each macrocell has a delay element provided on the signal propagation path between the input terminal and the output terminal and having one of a plurality of different delay values.

[0006]

[Operation] Since the delay element according to the present invention has one of a plurality of different delay values, and each macro cell has terminals located at the same position and the same number of basic cells, the desired delay value can be set. It is possible to easily replace a macro cell with a selected one.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a master slice LSI 100 which is an embodiment of the present invention. The master slice LSI 100 includes macro cells 4, 5, and 6. These macro cells 4, 5, and 6 each have an input terminal A. Furthermore, the macro cells 4, 5, and 6 each include flip-flops 2a, 2b, and 2c, and each of the flip-flops 2a, 2b, and 2c includes a data input terminal D, a clock input terminal T, and an output terminal Q, respectively. Furthermore, the positions of the respective terminals of the macro cells 4, 5, and 6 are the same, and the number of basic cells constituting the macro cells 4, 5, and 6 is the same.

On the other hand, macro cells 4, 5, and 6 have delay element sections 3a and 3 between input terminal A and data input terminal D, respectively.
3b and 3c, and these delay values are different. In particular, the delay value of the delay element section 3a is 0. Therefore, even if a timing error is discovered after wiring placement, it can be replaced with a macro cell equipped with a delay element having an appropriate delay value, and the timing error can be easily resolved.

[0009]

As described above, according to the present invention, a macro cell has terminals located at the same position, basic cells of the same number, and a plurality of terminals provided on the signal propagation path between the input terminal and the output terminal. Since the macrocell has a delay element having one of different delay values, it is possible to easily select a macrocell having a desired delay value and replace it, and there is no need to re-place and route and insert a new delay element. A master slice LSI that easily eliminates timing errors can be obtained.

[Brief explanation of the drawing]

FIG. 1: Master slice LS according to an embodiment of the present invention.
It is a block diagram showing I.

FIG. 2 is a block diagram showing a flip-flop 1, which is a macro cell constituting a conventional master slice LSI.

[Explanation of symbols]

4, 5, 6 Macro cells 2a, 2b, 2c Flip-flops 3a, 3b, 3
c Delay element section 100 Master slice LSI D Data input terminal Q Output terminal

Claims (1)

[Claims] 1. A plurality of terminals including an input terminal and an output terminal, located at the same position, the same number of basic cells, and provided on a signal propagation path between the input terminal and the output terminal, A master slice LSI comprising a plurality of macro cells having a delay element having one of a plurality of different delay values.