JPH02249254A - Layout design support method for large scale integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a design support method which facilitates reduction of the time for layout design and reduction of a circuit area after the layout by a method wherein the layouts of some elements of a macro-cell are variable and the layouts of the other elements and the interconnections in the whole macro-cell are fixed. CONSTITUTION:A macro-cell prepared in a circuit library is used for the support of layout design. The macro-cell used for the purpose is such that the layouts of some elements of it are variable and the layouts of the other elements and the interconnections in the whole macro-cell are fixed. If the macro-cell is, for instance, composed of an AND-gate 30, an input buffer 32 and an output buffer 34, the input buffer 32 and the output buffer 34 are used as soft parts 22 whose layouts can be varied independently and the layout of the other part, i.e., the AND-gate 30, is fixed and the AND-gate is used as a hard part 24 and, further, the whole interconnections, i.e., the input buffer 32 - the AND gate 30 - the output buffer 34 are fixed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method for supporting the layout design of a large-scale integrated circuit using macro cells prepared in a circuit library, and in particular, the present invention can shorten the layout design time, and
The present invention relates to a layout design support method for large-scale integrated circuits that has a small circuit area after layout.

[Conventional technology]

For specific applications, when designing large-scale integrated circuits (LSIs) such as integrated circuits (ASICs), already designed small-scale circuits (macrocells) are registered in the memory of a computer-aided design (CAD) device as a circuit library. , a method is used in which a macro cell is called as needed and used as a part of the overall circuit in the design. The macro cells include so-called hard macros in which the circuit layout and connections within the cell are all fixed, and soft macros in which the layout within the cell is undetermined but only the circuit connections are determined and the layout is free.

[Task B that the invention seeks to achieve]

As shown in FIG. 10, when designing the entire circuit 10 using the hard macro 12, since the circuit layout within the cell is fixed, there is no need to consider the circuit layout within the cell; Although the layout design is relatively easy, the overall circuit 10 has the problem of wasted area. On the other hand, the soft macro 14, as shown in FIG.
When designing the overall layout, the soft macro 14
Since it is decomposed into each element 16 (for example, the minimum unit of NAND gate, etc.) constituting the circuit, a free layout is possible, and the area of the entire circuit 10 can be reduced.
On the other hand, it is necessary for the computer to find the optimal layout using a very large number of elements 16, and it takes a lot of processing time to determine the optimal layout. Furthermore, the layout determined by the computer is not necessarily the optimal layout. However, there is a problem in that there are cases where the In particular, in programmable logic devices (PLDs), if the entire small circuit consisting of a logic circuit that can be fixed as a hard macro and the input/output interface circuit that you want to place around it is used as a hard macro, there is a lot of wasted area. On the other hand, if the entire small-scale circuit is made into a soft macro, the layout problem becomes extremely complicated. In order to solve these problems, as shown in FIG. 12, it is also considered to design the entire circuit 10 by combining a small-scale circuit defined as a hard macro 12 and a small-scale circuit defined as a soft macro 14. However, regarding the small-scale circuit as the soft macro 14, it still has the problem that it takes a very long time to determine the layout of many elements within the small-scale circuit. The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an LSI layout design support method that can shorten the layout design time and reduce the circuit area after layout. .

[Means to achieve the task]

The present invention provides a method for supporting LSI layout design using macro cells prepared in a circuit library.
The above problem has been achieved by using a macro cell in which the layout of some elements is variable and the layout and overall connections of the remaining parts are fixed. Further, the elements that make the layout variable can be changed. Further, the element whose layout is variable is an input/output element or/and a storage element.

[Action and effect]

When supporting LSI layout design using macro cells prepared in a circuit library, the present invention provides a layout of some elements (referred to as software parts) 22 as the macro cells 20, as shown in FIG. 1(A). is variable, and the layout and overall connections of the remaining portion (referred to as the hard portion) 24 are fixed. Therefore, as shown in FIG. 1(B), the software part 22 whose layout is variable can be used to adjust the arrangement of other macro cells, etc.
According to the present invention, depending on the shape and the connection relationship with other macro cells, it is possible to lay out, for example, either above or below the hard part 24, on the left or right, or in another remote location. , soft part 2 of macrocell 20
Since the layout of 2 is variable, as shown in Figure 2,
Each macro cell 20 can be arranged within the entire circuit 10 without waste, and as in the case where the entire circuit is a hard macro,
There is no waste in the overall area, and the circuit area after layout can be reduced. Furthermore, since there is no need to consider the internal layout of the hard part 24 whose layout is fixed, the time required for layout design is also shortened. In addition, the elements that make the layout variable (soft part)
If it is possible to change, for example, by incorporating only specific input/output elements that are not input/output at high speed into the hardware part, it becomes possible to input or output the corresponding input/output at high speed. In addition, when the element whose layout is variable (soft part) is used as an input/output element, the input/output element is set in relation to other macro cells and pin positions (undefined) that are input/output partners. , can be laid out in the optimal position. Note that it is desirable that the logic block, which is the center of the logic circuit, be placed in the hardware part in order to enable high-speed operation and to prevent synchronization delays when separated. In addition, when the element (soft part) whose layout is variable is used as a memory element, the memory element has less adverse effects such as operation delay than when the central block of the logic circuit has a variable layout. Examples of these include flip-flops and latches.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. In the first embodiment of the present invention, as shown in FIG. 3, in a macro cell consisting of an AND gate 30, an input buffer 32, and an output buffer 34, the layouts of the input buffer 32 and the output buffer 34 are independent of each other. The layout of the remaining AND gate 30 is fixed to form a hard part 24, and the overall connection of input buffer 32, AND gate 30, output, and buffer 34 is fixed. When designing the layout of the entire circuit using this macrocell, depending on the shape and arrangement of other macrocells and the connections with them, for example, as shown in FIG. 4(A),
The input buffer 32 and the output buffer 34 may be arranged horizontally on the left and right sides of the ND gate 30, or the input buffer 32 and the output buffer 34 may be arranged vertically above and below the AND gate 30, as shown in FIG. 4(B). be able to. Also, although not shown, for example, the input buffer 32 and the output buffer 34 are connected to the L center around the AND gate 30.
It is also possible to arrange them in a letter shape. Next, a second embodiment of the present invention will be described in detail. As shown in FIG. 5, this embodiment includes a central circuit 40, a first peripheral circuit 42 including, for example, four circuit elements 42A to 42D, and a second peripheral circuit including, for example, three circuit elements 44A to 44C. 44, each of the circuit elements 42A to 42D and 44A to 44C of the peripheral circuits 42 and 44 is made into a soft part whose layout can be changed independently of each other, and the layout of the remaining central circuit 40 is fixed and made into a hard part. In addition to making it a part, the connection of the whole is fixed. When designing the overall circuit layout using this macro cell, depending on the shape, arrangement, and connection relationship with other macro cells, for example, as shown in FIG. The circuit element 42 of the first peripheral circuit 42
A to 42D may be placed together, and circuit elements 44A to 44C of the second peripheral circuit 44 may be placed on the right side of the central circuit 40, or the central circuit 40 may be placed as shown in FIG. 6(B). The circuit elements 42A, 42B, and 42C can be placed above, the circuit elements 44C542D and 44A can be placed on the left, and the circuit element 44B can be placed on the right. Next, a third embodiment of the present invention will be described in detail. This third embodiment applies the present invention to a large-scale PLD (HPLD).
), as shown in FIG. 7, there is a central circuit 50 constituting a logic circuit, expansion circuits 52 and 54 for expanding the number of product terms of the central circuit 50, and expansion circuits 52 and 54 for expanding the number of inputs. expansion circuits 56, 58 for example, and six input/output block (IOB) 60A, 60B, 60C160D,
In the macrocell having input/output blocks 60E and 60F, the input/output blocks 60A to 60F are made into software parts whose layouts can be varied independently of each other, and the layout of the remaining logic circuits consisting of the central circuit 50 and expansion circuits 52 to 58 is fixed. This is the hard part 24, and the overall connection is fixed. When designing the layout of the entire circuit using this macro cell, depending on the shape and arrangement of other macro cells, and the connection relationship with them, the left and right sides of the hard part 24 are designed, for example, as shown in FIG. 8(A). Input/output block 60A~60
F is placed, or as shown in Figure 8 (B),
Input/output cover block 6<)A~ on the upper and lower sides of the hard part 24
60F can be placed. Next, a fourth embodiment of the present invention will be described in detail. This fourth embodiment allows the designer to change the elements that make the layout variable in a macro cell similar to the third embodiment. For example, as shown in FIG. It is designed so that it can be incorporated into the hard part 24. In this way, for example, by incorporating the input/output block 60B into the hardware part 24, the layout of the input/output block 60B and other hardware parts (logic circuits) is fixed. Therefore, for example, by incorporating an input/output block that you want to input/output at high speed in close proximity to a logic circuit into the hardware part 24, it becomes possible to input/output only a specific input/output with a small amount of delay, that is, at high speed. . In the above description, the present invention was mainly explained using PLD as an example, but the scope of application of the present invention is not limited thereto.

[Brief explanation of drawings]

1 is a suggested plan view showing an example of the configuration and arrangement of a macro cell used in the present invention; FIG. 2 is a suggested plan view showing an example layout of an overall circuit using the macro cell; FIG. 3 is a suggested plan view showing an example of the layout of a macro cell used in the present invention FIGS. 4A and 4B are implicit plan views showing an example of the layout of the macro cell used in the first embodiment, and FIG. Second aspect of the present invention
FIGS. 6(A) and 6(B) are implicit plan views showing an example of the configuration of the macrocell used in the embodiment. FIG. 7 is an implicit plan view showing an example of the layout of the macrocell of the second embodiment. Third
FIGS. 8(A) and 8(B) are implicit plan views showing an example of the configuration of a macro cell used in the embodiment. FIGS. Fourth
FIG. 10 is an implicit plan view showing a configuration example of a macro cell used in the embodiment; FIG. FIG. 12 is an implicit plan view for explaining the method of determining the layout of the entire circuit using soft macros. FIG. 3 is an implicit plan view for explanation. 20... Macro cell, 22... Partial element (soft part), 24... Remainder (hard part), 30... AND gate, 32... Input buffer, 34... Output buffer, 40 .50... Central circuit, 42.44... Peripheral circuit, 42A to 42D, 44A to 44C... Circuit element, 52
．． 54.56.58... Expansion circuit, 60A to 60F.
...Input/output block (IOB).

Claims (4)

[Claims] (1) In a method for supporting the layout design of large-scale integrated circuits using macrocells prepared in a circuit library, the layout of some elements of the macrocell is variable, and the layout and overall connections of the remaining parts are fixed. A method for supporting layout design of a large-scale integrated circuit, characterized by using a method for supporting layout design of a large-scale integrated circuit. (2) A layout design support method for a large-scale integrated circuit according to claim 1, characterized in that the elements that make the layout variable are changeable. (3) A layout design support method for a large-scale integrated circuit according to claim 1, wherein the element whose layout is variable is an input/output element. (4) A layout design support method for a large-scale integrated circuit according to claim 1, wherein the element that makes the layout variable is a storage element.