JPH0437059A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0437059A JPH0437059A JP14482190A JP14482190A JPH0437059A JP H0437059 A JPH0437059 A JP H0437059A JP 14482190 A JP14482190 A JP 14482190A JP 14482190 A JP14482190 A JP 14482190A JP H0437059 A JPH0437059 A JP H0437059A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- signals
- buffer
- input
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 239000000872 buffer Substances 0.000 claims abstract description 37
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にマイクロプロセッサの
ような高速に信号を入出力するような半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device such as a microprocessor that inputs and outputs signals at high speed.
従来の半導体装置の一例を第2図を用いて説明する。同
図において、1は半導体装置、2はバッファ群、3は第
1電源、4は第2電源、5は第3電源、6は第4電源、
7は内部回路、8は入力信号のバッファ群、9は出力信
号と入出力信号のバッファ群である。An example of a conventional semiconductor device will be explained using FIG. 2. In the figure, 1 is a semiconductor device, 2 is a buffer group, 3 is a first power supply, 4 is a second power supply, 5 is a third power supply, 6 is a fourth power supply,
7 is an internal circuit, 8 is a buffer group for input signals, and 9 is a buffer group for output signals and input/output signals.
第2図に示す半導体装置1では、電位をより安定させる
ため、複数の電源(VKIDとvss)3〜6を入力し
ている。そしてこの半導体装置1の内部では、複数に入
力した電源3〜6を1つにまとめて、半導体装置全体に
供給している。In the semiconductor device 1 shown in FIG. 2, a plurality of power supplies (VKID and vss) 3 to 6 are input in order to further stabilize the potential. Inside this semiconductor device 1, the plurality of input power supplies 3 to 6 are combined into one power source and supplied to the entire semiconductor device.
この場合、電源を内部で1つに接続しているため、半導
体装置の場所によって電位が異なるということはないが
、少くとも1つの出力信号の値が変化したとき、その電
流量が大きいため、電源(■。と■8.)の値が変化す
ると、他の信号や内部回路にまで影響してしまう。In this case, since the power supplies are connected internally, the potential does not vary depending on the location of the semiconductor device, but when the value of at least one output signal changes, the amount of current is large, so If the value of the power supply (■. and ■8.) changes, it will affect other signals and internal circuits.
以上のように、出力信号の変化時に電源の値が大きく変
化するので、半導体装置全体で同じ電源を使用している
と、他の信号や内部回路の電源の値が変化することにな
り、引いては誤動作してしまうという問題があった。As mentioned above, the power supply value changes greatly when the output signal changes, so if the same power supply is used for the entire semiconductor device, the power supply value of other signals and internal circuits will change, resulting in However, there was a problem that it would malfunction.
本発明は以上の点に鑑みてなされたもので、出力信号の
変化時に電源の値が大きく変化することによって他の信
号や内部回路に与える影響を少なくすることを目的とす
る。The present invention has been made in view of the above points, and an object of the present invention is to reduce the influence on other signals and internal circuits due to a large change in the power supply value when the output signal changes.
本発明に係る半導体装置は、内部回路、入力信号のバッ
ファ、同じタイミングで出力する出力信号及び入出力信
号のバッファに独立に電源(VlとV8.)を供給する
ようにしたものである。The semiconductor device according to the present invention is configured to independently supply power (Vl and V8.) to an internal circuit, an input signal buffer, an output signal outputted at the same timing, and an input/output signal buffer.
また、本発明の別の発明に係る半導体装置は、内部回路
、出力信号のバッファ1同じタイミングで入力する入力
信号及び入出力信号のバッファに独立に電源(VDII
IとV8.)を供給するようにしたものである。In addition, in the semiconductor device according to another aspect of the present invention, the internal circuit, the output signal buffer 1, and the input signal and input/output signal buffers input at the same timing are provided with an independent power supply (VDII).
I and V8. ).
本発明おいては、内部回路、入力信号または出力信号の
バッファ、同じタイミングで出力または入力する信号及
び入出力信号のバッファに独立に電源信号を供給するこ
とによって、お互いの電源に対する影響を少なくする。In the present invention, by independently supplying power signals to internal circuits, input signal or output signal buffers, signals that are output or input at the same timing, and input/output signal buffers, the influence on each other's power supplies is reduced. .
以下、本発明を図に示す実施例によって詳細に説明する
。Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings.
第1図は本発明の一実施例による半導体装置の模式的な
構成図である。同図において、1は半導体装置、2はバ
ッファ群、3は第1電源、4は第2電源、5は第3電源
、6は第4電源、7は内部回路、8は入力信号のバッフ
ァ群、9.は出力信号の第1グループをなすバッファ、
9tは出力信号の第2グループをなすバッファである。FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a semiconductor device, 2 is a buffer group, 3 is a first power supply, 4 is a second power supply, 5 is a third power supply, 6 is a fourth power supply, 7 is an internal circuit, and 8 is a buffer group for input signals. ,9. are buffers forming the first group of output signals,
9t is a buffer forming the second group of output signals.
すなわち、この実施例は、第1電源3を内部回路7に接
続するとともに、第2電源4を入力信号のバッファ群2
に接続し、さらに第3電源5.第4電源6をそれぞれ出
力信号の第1及び第2グループのバッファ91,9□に
接続することにより、これら電源3〜6の電源信号を各
部に独立して供給するものとなっている。なお、図中同
一符号は同一または相当部分を示している。That is, in this embodiment, the first power supply 3 is connected to the internal circuit 7, and the second power supply 4 is connected to the input signal buffer group 2.
and further connect to the third power supply 5. By connecting the fourth power supply 6 to the buffers 91, 9□ of the first and second groups of output signals, respectively, the power signals of these power supplies 3 to 6 are independently supplied to each section. Note that the same reference numerals in the figures indicate the same or corresponding parts.
第1図に示す半導体装置1において、出力信号と入出力
信号を同じタイミングで出力する信号に分類する。この
場合、2つのグループつまり第1グループのバッファ9
.と第2グループのバッファ9tに分割できるとする。In the semiconductor device 1 shown in FIG. 1, output signals and input/output signals are classified into signals that are output at the same timing. In this case, two groups, namely the first group of buffers 9
.. Assume that it can be divided into a second group of buffers 9t.
これにより、内部回路7.入力信号のバンファ群8.出
力信号の第1グループのバッファ95.出力信号の第2
グループのバッファ9.の各々に、第1電源3.第2電
源4.第3電源5.第4電源6を独立に供給することに
よって、各電源に対する影響を少なくすることができる
。As a result, internal circuit 7. Bumper group of input signals8. Buffer 95 for the first group of output signals. The second output signal
Group buffer9. A first power source 3. 2nd power supply 4. Third power supply 5. By supplying the fourth power source 6 independently, the influence on each power source can be reduced.
なお、本発明は第1図の実施例に限定されるものではな
く、内部回路、出力信号の出力バッファ。Note that the present invention is not limited to the embodiment shown in FIG. 1, but includes an internal circuit and an output buffer for output signals.
同じタイミングで入力する入力信号及び入出力信号のバ
ッファに独立に電源を供給するようにしてもよく、上記
実施例と同様の効果を有する。Power may be supplied independently to the buffers for input signals and input/output signals that are input at the same timing, and the same effect as in the above embodiment can be obtained.
以上説明したように本発明によれば、内部回路入力信号
または出力信号のバッファ、同じタイミングで出力また
は入力する信号と入出力信号のグループの各々に独立し
た電源を供給することにより、お互いに影響されること
のない電源を持つので、他の電源のグループの信号によ
る電源の変動を抑えることができ、これによって、ノイ
ズが乗りにくい半導体装置が得られる。As explained above, according to the present invention, by supplying independent power to each of the internal circuit input signal or output signal buffer, the signal output or input at the same timing, and the input/output signal group, they can influence each other. Since the semiconductor device has a power source that is never affected by noise, it is possible to suppress fluctuations in the power source caused by signals from other power source groups, thereby providing a semiconductor device that is less susceptible to noise.
第1図は本発明の一実施例の半導体装置を示す概略構成
図、第2図は従来の半導体装置を示す概略構成図である
。
1・・・半導体装置、2・・・バッファ群、3・・・第
1電源、4・・・第21を源・5・・・第3電源、6・
・・第4電源、7・・・内部回路、8・・・入力信号の
バッファ群、9I ・・・出力信号の第1グループのバ
ッファ、9.・・・出力信号の第2グループのバッファ
。
第1図FIG. 1 is a schematic configuration diagram showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic configuration diagram showing a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Buffer group, 3... First power supply, 4... 21st source, 5... Third power supply, 6...
... Fourth power supply, 7. Internal circuit, 8. Buffer group for input signals, 9I.. Buffer for first group of output signals, 9. ...buffer for the second group of output signals. Figure 1
Claims (2)
とも1つの出力信号と少くとも1つの入出力信号を持つ
半導体装置において、前記複数の電源信号の一部を内部
回路に接続するとともに、この複数の電源信号の一部を
少くとも1つの入力信号の入力バッファに接続し、少く
とも1つの出力信号と入出力信号を同じタイミングで出
力する信号にグルーピングして、そのグループごとのバ
ッファに前記電源信号の一部を接続し、各々に接続する
電源信号は独立していることを特徴とする半導体装置。(1) In a semiconductor device having a plurality of power supply signals, at least one input signal, at least one output signal, and at least one input/output signal, a part of the plurality of power supply signals is connected to an internal circuit, and , connect a part of the plurality of power supply signals to the input buffer of at least one input signal, group at least one output signal and input/output signal into signals that are output at the same timing, and create a buffer for each group. A semiconductor device characterized in that a part of the power supply signal is connected to the power supply signals, and the power supply signals connected to each of the power supply signals are independent.
とも1つの出力信号と少くとも1つの入出力信号を持つ
半導体装置において、前記複数の電源信号の一部を内部
回路に接続するとともに、この複数の電源信号の一部を
少くとも1つの出力信号の出力バッファに接続し、少く
とも1つの入力信号と入出力信号を同じタイミングで入
力する信号にグルーピングして、そのグループごとのバ
ッファに前記複数の電源信号の一部を接続し、各々に接
続する電源信号は独立していることを特徴とする半導体
装置。(2) In a semiconductor device having a plurality of power supply signals, at least one input signal, at least one output signal, and at least one input/output signal, a part of the plurality of power supply signals is connected to an internal circuit, and , connect a part of the plurality of power supply signals to the output buffer of at least one output signal, group at least one input signal and input/output signal into signals that are input at the same timing, and create a buffer for each group. A part of the plurality of power supply signals is connected to the semiconductor device, and the power supply signals connected to each of the power supply signals are independent.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14482190A JPH0437059A (en) | 1990-05-31 | 1990-05-31 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14482190A JPH0437059A (en) | 1990-05-31 | 1990-05-31 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0437059A true JPH0437059A (en) | 1992-02-07 |
Family
ID=15371242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14482190A Pending JPH0437059A (en) | 1990-05-31 | 1990-05-31 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0437059A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0750348A1 (en) * | 1995-06-22 | 1996-12-27 | Nec Corporation | Semiconductor device with electromagnetic radiation reduced |
-
1990
- 1990-05-31 JP JP14482190A patent/JPH0437059A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0750348A1 (en) * | 1995-06-22 | 1996-12-27 | Nec Corporation | Semiconductor device with electromagnetic radiation reduced |
US5708372A (en) * | 1995-06-22 | 1998-01-13 | Nec Corporation | Semiconductor device with electromagnetic radiation reduced |
KR100233186B1 (en) * | 1995-06-22 | 1999-12-01 | 가네꼬 히사시 | Semiconductor device with electromagnetic radiation reduced |
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