JPH0436660U

JPH0436660U -

Info

Publication number: JPH0436660U
Application number: JP7745590U
Authority: JP
Priority date: 1990-07-23
Filing date: 1990-07-23
Publication date: 1992-03-27

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の構成ブロツク図、
第２図は同実施例の作用説明図、第３図は同実施
例の判定回路のアルゴリズム説明図、第４図は従
来例の構成ブロツク図、第５図は同従来例の作用
説明図である。１，１ａ……アドレスカウンタ、２……ラベル
メモリ、３……第１の２値化画像メモリ、４……
第２の２値化画像メモリ、５……第３の２値化画
像メモリ、６……第４の２値化画像メモリ、７，
７ａ……判定回路、８……アドレス、１１……ラ
ベル指示信号（カウンタコントロール信号）、１
２……座標（Ｘ，Ｙ）注目画素の座標、１３……
上方向画素の座標、１４……下方向画素の座標、
１５……左方向画素の座標、１６……右方向画素
の座標、１７……現在注目画素、１８……２値化
されている画素、１９……２値化の有無に依存し
ない画素、２０……１つ前注目していた画素から
現在注目している画素への移動方向、２１……次
の注目する画素への移動方向、２２……２値化さ
れていない画素、２３……２値化されている画素
、２４……境界に沿つてラベリングしてきた軌跡
。 FIG. 1 is a block diagram of an embodiment of the present invention.
Fig. 2 is an explanatory diagram of the operation of the same embodiment, Fig. 3 is an explanatory diagram of the algorithm of the judgment circuit of the embodiment, Fig. 4 is a block diagram of the configuration of the conventional example, and Fig. 5 is an explanatory diagram of the operation of the conventional example. be. 1, 1a... Address counter, 2... Label memory, 3... First binarized image memory, 4...
Second binarized image memory, 5...Third binarized image memory, 6... Fourth binarized image memory, 7,
7a...Judgment circuit, 8...Address, 11...Label instruction signal (counter control signal), 1
2... Coordinates (X, Y) Coordinates of the pixel of interest, 13...
Coordinates of the upper pixel, 14... Coordinates of the lower pixel,
15... Coordinates of a pixel in the left direction, 16... Coordinates of a pixel in the right direction, 17... Current pixel of interest, 18... Pixel being binarized, 19... Pixel that does not depend on the presence or absence of binarization, 20 ...Movement direction from the previous pixel of interest to the current pixel of interest, 21...Movement direction to the next pixel of interest, 22...Pixels that have not been binarized, 23...2 Valued pixels, 24...Trajectory of labeling along the boundary.

Claims

[Scope of utility model registration request]

an address counter that outputs a designated address;
First, second, third, and fourth binarized image memories that store images to be labeled, and a predetermined priority order based on the pixel of interest currently received from the output of each of the binarized image memories. a determination circuit that determines the input and outputs the next address of interest to the address counter and outputs the pixel currently being focused on; a label memory that inputs the determination result of the determination circuit; 2. An image processing apparatus, wherein the converted image memory and the label memory are each connected to receive an output from the address counter.