JPS6087055U

JPS6087055U - Pattern edge removing device

Info

Publication number: JPS6087055U
Application number: JP17772683U
Authority: JP
Inventors: 磯部　勝芳
Original assignee: 日本電気株式会社
Priority date: 1983-11-17
Filing date: 1983-11-17
Publication date: 1985-06-15

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案および従来の絵柄ぶち取り装置における
絵柄部とふち取り部との関係を説明するための絵柄模式
図、第２図は本考案の一実施例を示すブロック図、第３
図ａ、　ｂはそれぞれ第２図に示すマスク処理部と論理
ゲート部との一例の詳細を示すブロック図、第４図は第
３図ａに示すマスク処理部からの画素信号とラスク上の
画素位置との関係を説明する模式図である。３００・・・・・・マスク処理部、３０１・・・・・・
論理ゲート部、３０２，３０３・・・・・・ＯＲ回路、
３１０〜３１８・・・・・・遅延回路、３２０〜３２８
・・・・・・シフトレジスタ、ＡＩ、　Ａ２・・・・・
・絵柄部、Ｂｌ、Ｂ２１゜Ｂ２２・・・・・・ふち取り
部、Ｃ・・・・・・ラスタ、Ｄ・・・・・・走査線、１
００・・・・・・図形信号、１０１・・・・・・基本ク
ロック、２００〜２０６・・・・・・画素信号、４００
・・・・・・ふち取り図形信号。Fig. 1 is a pattern diagram for explaining the relationship between the pattern part and the bordering part in the present invention and a conventional pattern removing device; Fig. 2 is a block diagram showing an embodiment of the invention;
Figures a and b are block diagrams showing details of examples of the mask processing unit and logic gate unit shown in Figure 2, respectively, and Figure 4 shows pixel signals from the mask processing unit and pixels on the rask shown in Figure 3a. It is a schematic diagram explaining the relationship with position. 300...Mask processing section, 301...
Logic gate section, 302, 303...OR circuit,
310-318...Delay circuit, 320-328
...Shift register, AI, A2...
・Picture section, Bl, B21°B22...Edging section, C...Raster, D...Scanning line, 1
00...Graphic signal, 101...Basic clock, 200-206...Pixel signal, 400
...Fringed figure signal.

Claims

[Scope of utility model registration request]

A binary quantized graphic signal obtained by scanning a pattern in a rask shape is stored, and for each determination position, the graphic signals at all pixel positions within M pixels from this determination position are converted into pixel signals. and a logic gate that outputs, for each of the determination positions, a edging figure signal according to whether or not one pixel signal is a pixel signal corresponding to the picture, in small increments of the pixel signals. A pattern removing device characterized by including a part.