JPH04364043A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a step difference caused by self-aligning process, connect both intrinsic and external bases and stably supply an extremely shallow base transistor which has sufficient pressure resistivity by the production of the silicon bipolar transistor which has a thin base produced by extremely low energy ion implantation. CONSTITUTION:For window opening in an intrinsic base area 7 by anisotropical etching on a polycrystal silicon film 4 and a silicon dioxide film 3 on a semiconductor substrate 1, a thin silicon nitride film 2 is formed on the surface of the semiconductor substrate 1 as a protecting film and a process of preventing a level difference caused by excessive etching of the semiconductor substrate 1 is provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing thin base silicon bipolar transistors by ultra-low energy ion implantation.

In order to improve the performance of semiconductor integrated circuits, it is required to form semiconductor elements with excellent high-speed performance. To achieve this, it is necessary to make the base shallower by lowering the energy of base ion implantation, improving the cutoff frequency, and reducing parasitics by introducing a self-alignment process, thereby increasing the overall device speed. be.

0003

2. Description of the Related Art FIG. 5 is an explanatory diagram of a conventional example. In the figure, 38 is a silicon (Si) substrate, 39 is a first polycrystalline silicon (poly-Si) film, 40 is a first silicon dioxide (SiO2) film, 41 is a window, 42 is an impurity ion, and 43 is an intrinsic base. region, 44 is the second SiO
2 film, 45 is the second poly-Si film, 46 is the emitter region,
47 is an external base area.

Conventionally, in order to reduce the parasitic element portion, the method shown in FIG.
As shown in the schematic cross-sectional diagram of the process, a self-alignment process called double poly-self alignment has been developed and used.

That is, in this process, as shown in FIG. 5(b), a first poly-Si film 3 for leading out the base electrode is formed.
In order to open the window 41 in the intrinsic transistor region at 9, anisotropic etching is performed, but at this time, it is difficult to control the etching and a part of the bulk Si substrate 38 may also be removed.

As a result, as shown in FIG. 5(d), the intrinsic base region 43 and the first poly S which is the base extraction electrode are
A step is created between the i-film 39 and the external base region 47 that connects the two, resulting in insufficient connection between the two and causing punch-through.

In the case of a base formed by low-energy ion implantation, this effect is a serious problem because the base is extremely thin.

[0008]

[Problem to be Solved by the Invention] Therefore, in the conventional technology, it is necessary to achieve sufficient connection between both the intrinsic and external bases and to achieve sufficient breakdown voltage in ultra-shallow base transistors using low-energy ion implantation using a self-aligned process. The problem had arisen that it was not possible to stably supply transistors.

In view of the above points, the present invention uses a thin nitride film as a stopper for anisotropic etching to prevent the generation of steps due to the self-alignment process and realize sufficient connection between both the intrinsic and external bases. The aim is to stably supply ultra-shallow base transistors with sufficient breakdown voltage.

0010

[Means for Solving the Problems] FIGS. 1 and 2 are diagrams explaining the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a first silicon nitride (Si3N4) film, 3 is a first SiO2 film, 4 is a first poly-Si film, 5 is a first window, and 6 is a first silicon nitride (Si3N4) film.
are impurity ions, 7 is an intrinsic base region, 8 is a second poly-Si film, 9 is a second Si3N4 film, 10 is a transistor region, 11 is a second SiO2 film, 12 is a third poly-S
i film, 13 is the third Si3N4 film, 14 is the second window,
15 is the fourth poly-Si film, 16 is the emitter region, 17
is the external base area.

Regarding the present invention that solves the above problems,
The principle of the present invention will be explained in order of steps with reference to FIGS. 1 and 2. As shown in FIG. 1(a), a first Si3N4 film 2 and a first SiO2 film 3 are formed on a semiconductor substrate 1 made of single crystal Si.
, a first poly-Si film 4 are sequentially deposited.

As shown in FIG. 1B, using a resist film (not shown) as a mask, the first poly-Si film 4 and the first SiO film on the intrinsic transistor region are etched by anisotropic etching.
A first window 5 for forming the intrinsic base region 7 is opened in the two films 3,
Furthermore, impurity ions 6 are implanted into the intrinsic base region 7.

As shown in FIG. 1(c), the second polySi
After the film 8 is deposited over the entire surface, sidewalls made of the second poly-Si film 8 are formed by anisotropic etching. As shown in FIG. 1(d), a second layer is formed on the entire surface of the semiconductor substrate 1.
A Si3N4 film 9 is deposited.

As shown in FIG. 1E, a resist film (not shown) is applied, a transistor region 10 wider than the intrinsic transistor is patterned, and the second Si3N4 film 9 and the first poly-Si film are etched by anisotropic etching. membrane 4
remove. After that, the first SiO2 film 3 is etched by isotropic etching.
Also removes.

As shown in FIG. 1(f), the first poly-Si film 4 and the second poly-Si film 8 are all oxidized by thermal oxidation to form a second SiO2 film 11. As shown in FIG. 2(g), the first Si3N4 film 2 and the second Si3N4 film 9 are removed by isotropic etching.

At this time, only on the intrinsic base region 7, the first Si3N4 film 2 and the second Si3N4 film 9 overlap, and the second Si3N4 film 9, which is the sidewall,
By being protected by the O2 film 11, the first
A portion of the Si3N4 film 2 remains.

As shown in FIG. 2(h), the third poly-Si
A film 12 is deposited by selective growth only on the exposed portions of the semiconductor substrate 1. At this time, when the third poly-Si film 12 is grown, it is doped with an impurity of the same type as the base, and if necessary, an external base region is formed by heat treatment.

As shown in FIG. 2(i), a third Si3N4 film 13 is deposited on the entire surface of the Si substrate 1. Figure 2 (j
), a second window 14 is opened inside the second SiO2 film 11, and a third S window is formed by isotropic etching.
The i3N4 film 13 is removed.

However, compared to the thickness of the sidewall,
Since the first Si3N4 film 2 is sufficiently thin, a portion of the first Si3N4 film 2 remains below the sidewall. Figure 2
As shown in (k), the fourth polyS is used as the emitter electrode.
An i-film 15 is deposited on the semiconductor substrate 1 exposed within the sidewall by selective growth.

At this time, emitter impurities are mixed into the fourth poly-Si film 15 by doping during growth or by ion implantation, and quick annealing is performed to form the emitter region 16, the intrinsic base region 7, and the extrinsic base region. form 17.

[0021]

[Operation] In the present invention, when opening the window of the intrinsic transistor region by anisotropic etching, the surface of the semiconductor substrate becomes Si3.
Since it is protected by the N4 film, no steps are caused by excessive etching of the semiconductor substrate.

Therefore, it is possible to achieve sufficient connection between both the intrinsic and external bases and to stably supply ultra-thin base transistors with sufficient withstand voltage.

[0023]

Embodiment FIGS. 3 and 4 are schematic sectional views in order of steps of an embodiment of the present invention. In the figure, 18 is a Si substrate, 19
20 is As+, 21 is an epitaxial layer, 22 is the first Si3N4 film, 23 is the first
24 is the first poly-Si film, 25 is the first window, 26 is B+, 27 is the intrinsic base region, 28 is the second poly-Si film, 29 is the second Si3N4 film, 30 is the transistor 31 is the second SiO2 film, 32 is the third poly-Si film, 33 is the third Si3N4 film, 34 is the second window, 35 is the fourth poly-Si film, 36 is the emitter region, and 37 is the emitter region. This is an external base area.

An embodiment of the present invention will be explained in order of steps. As shown in Figure 3(a), p-type 15~20Ωcm
Arsenic ions (As+) 20 are implanted into the single-crystal Si substrate 18 by ion implantation at an acceleration voltage of 70 keV and a dose of 5.5×10 15 /cm 2 to form a buried layer 19 .

As shown in FIG. 3(b), an epitaxial layer 21 of 0.3 Ωcm and a thickness of 1 μm is formed on the Si substrate 18. For convenience, from FIG. 2(c), the Si substrate 1 on which the buried layer 19 and epitaxial layer 20 are formed is shown.
8 are collectively referred to as a Si substrate 18.

As shown in FIG. 3(c), a first Si3N4 film 22 with a thickness of 200 Å and a first SiO2 film 23 with a thickness of 3.0 Å are deposited on the Si substrate 18 by the CVD method.
The first poly-Si film 24 is sequentially deposited to a thickness of 500 Å.

As shown in FIG. 3(d), a resist film (not shown) is applied, a first window 25 with a width of 0.8 μm is opened on the intrinsic transistor region, and the first window 25 on the intrinsic transistor region is anisotropically etched. The Si3N4 film 22, first SiO2 film 23, and first poly-Si film 24 are removed. Furthermore, boron ions (B+) 26 are implanted through the first Si3N4 film 22 by an ion implantation method at an acceleration voltage of 10 keV and a dose of 3 x 1013/cm2 to form an intrinsic base region 27.

[0028] As an etchant for anisotropic etching, for example, oxygen (02),
Carbon tetrafluoride and methane trifluoride (CF4+CHF3) for Si3N4 film, carbon tetrafluoride and methane (CF4+CH4) for SiO2 film, chlorine and silicon tetrachloride (Cl2+SiCl4) for polySi film. Use.

As shown in FIG. 3(e), the second polySi
After depositing the film 28 over the entire surface, sidewalls are formed by anisotropic etching. As shown in Figure 3(f),
A second Si3N4 film 29 is deposited over the entire surface of the substrate.

As shown in FIG. 4(g), a resist film (not shown) is applied and patterned to form a transistor region 30 having a width of 4 μm, which is wider than the intrinsic transistor, and anisotropic etching is performed to form the second Si3N4 film 29 and the first The poly-Si film 24 is removed. Thereafter, the first SiO2 film 23 is removed by isotropic etching.

For example, a hydrofluoric acid buffer is used as an etchant for isotropic etching of the SiO2 film. Figure 4(h)
As shown in FIG. 2, the first poly-Si film 24 is
, the second poly-Si film 28 is completely oxidized, and the second poly-Si film 28 is completely oxidized.
A film 31 is used.

As shown in FIG. 4(i), the first Si3N4 film 22 and the second Si
The 3N4 film 29 is removed. For example, phosphoric acid is used as an etchant for isotropic etching of the Si3N4 film.

As shown in FIG. 4(j), the third poly-Si film 32, which will become the base extraction electrode, is grown by selective growth.
It is deposited only on the exposed parts of the substrate 1. At this time, when growing the poly-Si film 32, boron ions (B+) are dosed at 1 x 1020/cm3 by ion implantation.

As shown in FIG. 4(k), a third Si3N4 film 33 is deposited on the entire surface of the Si substrate 18 to a thickness of 200 Å. As shown in Figure 4(l), the second SiO2
A second window 34 with a width of 3 μm is opened inside the film 11, and the third Si3N4 film 33 is removed by isotropic etching. At this time, the third Si3N inside the sidewall
4 films 33 are also removed at the same time.

As shown in FIG. 4(m), a fourth poly-Si film 35, which will become an emitter electrode, is deposited on the exposed Si substrate 1 within the sidewall by selective growth. At this time, the poly-Si film is doped with arsenic ions (As+) at 1 x 1020/cm3 by ion implantation.

The emitter region 36 and the intrinsic base region 27 are formed by quick annealing at 1,000° C. for 10 seconds.
, an external base region 37 is formed at the same time, and an emitter, base,
Form each collector electrode and complete the bipolar transistor.

[0037]

[Effects of the Invention] As explained above, according to the present invention, a bipolar transistor with sufficient breakdown voltage can be stably manufactured without creating a step between the intrinsic and external bases in the self-alignment process, and can be manufactured at high speed. It greatly contributes to the manufacture of transistor circuits.

[Brief explanation of the drawing]

[Figure 1] Diagram explaining the principle of the present invention (Part 1)

[Figure 2]
Diagram explaining the principle of the present invention (Part 2)

[Fig. 3] Schematic cross-sectional view of the process order of one embodiment of the present invention (Part 1)

[Fig. 4] Schematic sectional view of the process order of one embodiment of the present invention (Part 2)

[Figure 5] Explanatory diagram of conventional example

[Explanation of symbols]

1 Semiconductor substrate 2 First Si3N4 film 3 First SiO2 film 4 First poly-Si film 5 First window 6 Impurity ions 7 Intrinsic base region 8 Second poly-Si film 9 Second Si3N4 film 10 Transistor area 11 Second SiO2 film 12 Third poly-Si film 13 Third Si3N4 film 14 Second window 15 Fourth poly-Si film 16 Emitter area 17 External base area 18 Si substrate 19 Embedded layer 20 As+ 21 Epitaxial layer 22 First Si3N4 film 23 First SiO2 film 24 First poly-Si film 25 First window 26 B+ 27 Intrinsic base region 28 Second poly-Si film 29 Second Si3N4 film 30 Transistor area 31 Second SiO2 film 32 Third poly-Si film 33 Third Si3N4 film 34 Second window 35 Fourth poly-Si film 36 Emitter area 37 External base area

Claims (1)

[Claims] 1. A step of sequentially depositing a first silicon nitride film (2), a first silicon dioxide film (3), and a first polycrystalline silicon film (4) on a semiconductor substrate (1), The first polycrystalline silicon film (
4), and the first silicon dioxide film (3),
By anisotropic etching, the intrinsic base region (7)
A first window (5) for formation is opened, and the first polycrystalline silicon film (4) and the first silicon dioxide film (3) are opened.
) is used as a mask to implant impurity ions (6) into the semiconductor substrate (1), and
A second polycrystalline silicon film (8) is deposited on top, and the second polycrystalline silicon film (8) is etched by anisotropic etching.
) on the side walls of the first window (5), depositing a second silicon nitride film (9) on the semiconductor substrate (1), and depositing a second silicon nitride film (9) on the semiconductor substrate (1). ), the second silicon nitride film (9) and the second polycrystalline silicon film (4) are removed, and the first silicon dioxide film (3) is completely removed; The first polycrystalline silicon film (4) and the second polycrystalline silicon film (8) are oxidized to form a second polycrystalline silicon film (4) and the second polycrystalline silicon film (8).
The second silicon nitride film (9) is formed by forming a silicon dioxide film (11) and isotropic etching.
a step of removing all of the first silicon nitride film (2) and a part of the first silicon nitride film (2);
A step of selectively growing a third polycrystalline silicon film (12) and a step of selectively growing a third silicon nitride film (12) on the semiconductor substrate (1).
13) and depositing the third layer on the transistor region.
a step of removing the silicon nitride film (13) and the exposed first silicon nitride film (2), selectively growing a fourth polycrystalline silicon film (15), and forming an emitter region (16).
) A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor device.