JPH043638A - Method and device for demodulating transmitted signal - Google Patents

Abstract

PURPOSE:To eliminate the signal distortion to accurately de modulate a transmitted signal by distributing clock pulses in accordance with a digital signal and averaging distributed clock pulses. CONSTITUTION:In a correcting circuit, an averaging start signal P1, a level discrimination signal P2, and a signal discrimina tion reference pulse P3 are generated independently of a demodulated digital signal D1 based on a power signal S3 completely synchronized with an input signal S1. The digital signal D1 is corrected in a correcting circuit 1 independently of the timing of the digital signal D1 to be demodulated by the averaging start signal P1 and the level discrimination signal P2 which are obtained from the power signal S3. Consequently, a corrected signal D6 as the digital signal having a certain timing and an accurate certain time width T is generated independently of step out of the demodulated digital signal D1 even in the case of step out of the demodulated digital signal. Thus, the transmitted signal is accurately demodulated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for demodulating a transmission signal in wired communication and a demodulation device for a transmission signal implementing this method. The present invention relates to a method and apparatus for demodulating a transmission signal transmitted via a communication medium such as a low-voltage power distribution line.

[Conventional technology]

The demodulation of the transmission signal in wired communication is as shown in Fig. 6(a), which is a frequency modulated analog signal, as shown in Fig. 5.
The input signal S1 shown in is input, and the first filter 4
The first amplification circuit 5 amplifies the amplified signal after cutting the 7th part, and from this amplified signal, the transmission signal S2 shown in FIG. This transmission signal S2 is extracted by the second filter 6.
After impedance matching is performed in the second amplifier circuit 7, the third filter 8 divides the signal component into a signal component and a signal component.
The digital signal D1 is converted into the digital signal 01 shown in FIG. 6(c), and the digital signal D1 is converted into the digital signal 01 shown in FIG. The digital signal D1 at the time of generation of each signal judgment reference pulse P3
The data signal D7 shown in the 61st ffl(f) is formed by determining the potential of the data signal D7.

The practical condition for demodulating the transmission signal in the above-mentioned wired communication is good transmission characteristics. However, if the communication medium is one with poor transmission characteristics such as a low-voltage distribution line, the transmission signal S2 is converted into the digital signal D1. When it is demodulated, signal distortion including bit splitting occurs due to pulse noise generated in the transmission, and the potential judgment using the signal judgment reference pulse P3 of the demodulated digital signal D1 is not performed normally. There is the inconvenience of running out.

That is, the digital signal D demodulated by the third filter 8
When a bit crack B occurs in I and the waveform becomes as shown in FIG. Abnormal data as shown in Figure (g) will result, making it impossible to perform normal communication.

For this reason, in the past, a fourth filter 9 consisting of a resistor and a capacitor was provided in order to remove the bit splitting B, which is signal distortion that occurred in the demodulated digital signal D1. This is to remove the bit breakage B that has occurred in the digital signal D1.

Separately, focusing on the fact that the frequency band in which signal distortion occurs changes depending on the time period of - day, the transmission signal S2 is transmitted using multiple frequency bands, and the received demodulated signal S2 is transmitted using a plurality of frequency bands. A normal digital signal D1 without any signal distortion is selected from among the plurality of digital signals D1, and only the transmission signal S2 in the frequency band of this digital signal D1 is used for communication.

[Problem to be solved by the invention]

In this way, the demodulation of the conventional transmission signal is performed by the fourth filter 9.
is provided to cut pulse noise of 5 ms or less in the digital signal Dl, but since the fourth filter 9 is an analog filter composed of a resistor and a capacitor, the filtering ability is limited. There is a limit, and although it is possible to completely cut out pulsed noise of several μs, it is not possible to completely cut out pulsed noise with a time width of several ms. Therefore, pulse noise of about 2ms to 4ms generated due to switching etc. passes through the fourth filter 9, and the digital signal D1 input to the signal judgment circuit 1° is changed as shown in Fig. 6 (()). There was a problem that the abnormal data signal remained.

Apart from this problem, the fourth filter 9, which is composed of a resistor and a capacitor, changes its filter characteristics depending on the characteristics of the parts used, such as the temperature characteristics, and the filter band may shift or the synchronization with the power signal may change. and the signal width of the demodulated data signal D7 changes, etc., resulting in a data signal D7.
There is a problem that reliability is low.

In addition, the transmission signal S2 is transmitted in multiple frequency bands, a demodulation circuit corresponding to each frequency band is provided, and a normal data signal D1 is transmitted.
If communication is performed using a demodulation circuit that can demodulate the signal, multiple demodulation circuits are required, resulting in a complex and large demodulation circuit configuration, complicated operation, and an enormous increase in communication equipment costs. There is.

Therefore, the present invention was devised to solve the above-mentioned problems in the conventional technology, and it is possible to completely and reliably remove pulse noise by digital processing, and to perform each process at a constant rate synchronized with the power signal. Achieving timing is a technical issue, and the purpose is to make it possible to achieve accurate and reliable demodulation and to simplify the circuit configuration.

[A means of saving to solve problems]

The means of the present invention to solve the above-mentioned technical problem (hereinafter, see FIGS. 1 to 4) is to convert the input transmission signal S2 into a digital signal D1, and to convert the input transmission signal S2 into a digital signal D1. A clock digital signal D3 and an inverted clock digital signal D4, which are two signals in which the clock pulse CL is inverted and a clock pulse CL is added, are created at intervals of a constant time width T, which is the code time width of the digital signal DI. , a counter output signal D indicating the magnitude relationship of the cumulative number of clock pulses between the clock digital signal D3 and the inverted clock digital signal D4.
5, to create a correction signal D6 which is a digital signal corrected by level determination of this counter output signal o5 at intervals of a constant time width T; to determine the level of this correction signal D6 at intervals of a constant time width T; The second step is to demodulate the data signal D7 by determining the data signal D7.

Clock digital signal D3 and anti-clock digital signal D
4, the clock digital signal D3 and the inverted clock digital signal D
The time to start calculating the magnitude of the cumulative number of clock pulses between clock pulses D1 and D4 is set to a time slightly delayed from the rise of the digital signal D1, and the time to determine the level of the counter output signal D5 is set to a time slightly delayed from the rise of the digital signal D1. It is preferable to set it at a time near the end of the code time of the digital signal D1, which is the same time as the start time of calculation of the cumulative number of clock pulses with respect to the inverted clock digital signal D4.

The device for carrying out the demodulation method described above includes a plurality of filters and a plurality of amplifier circuits that separate the transmission signal S2 from the input signal S1 and convert the transmission signal S2 into a digital signal port 1, and a plurality of amplifier circuits that separate the transmission signal S2 from the input signal S1. A correction circuit 1 that outputs a correction signal D6 obtained by correcting the signal 01, and also generates and outputs a reference pulse P3 for signal determination from a power supply signal S3 synchronized with the input signal Sl;
and a signal determination circuit 10 that determines the level of 6 using a reference pulse P3 for signal determination and creates a data signal D7; An averaging start signal P1 that instructs to start calculating the number of cumulative clock pulses between two signals, the digital signal D3 and the inverted clock digital signal D4, and the accumulation between the clock digital signal D3 and the inverted clock digital signal D4. A timing generation circuit unit 2 that generates and outputs a level judgment signal P2 that instructs level judgment of a counter output signal 05 indicating the magnitude relationship of the number of clock pulses and a reference pulse P3 for signal judgment; and an inverted digital circuit whose polarity is inverted. An inverted clock digital signal D4, which is the signal D2 with a clock pulse CL added to it, is input to the up-side terminal, and a clock digital signal D is obtained by adding the clock pulse CL to the input digital signal D1.
3 is input to the down side terminal, and the averaging start signal P1 is input to the clear terminal.
d and the counter output signal D5, which is the output signal of the up/down counter 3d, are input to the data terminal, and the level determination signal P2 is input to the clock terminal to generate the correction signal D.
and an averaging circuit section 3 consisting of a flip-flop circuit 3e which is a D-type flip-flop that outputs 6.

The timing generation circuit section 2, which is one component of the correction circuit 1, includes a bandpass filter 2a that removes harmonics and the like from the input power signal S3, and an all-pass filter that corrects timing deviations caused by the bandpass filter 2a. 2b, and a pulse generating circuit 2C that generates an averaging start signal P1, a level determination signal P2, and a reference pulse P3 for signal determination in accordance with the power signal S3 whose deviation has been corrected by the all-bus filter 2b.

[Effect]

Since the clock pulse CL added to the digital signal D1 and the inverted digital signal D2 is added to the low potential level locations of both signals D1 and D2, the clock pulse CL is added to the low potential level locations of both signals D1 and D2, so that the clock pulses CL are added to the low potential level locations of both signals D1 and D2. Clock pulse CL is also added to both signals DJ and D, which have become high potential level due to bit breakage B, and no clock pulse CL is added to the two positions of both signals DJ and D.

The clock digital signal D3 and the inverted clock digital signal D4 formed in this way alternately output clock pulses CL with a constant time width T, but if there is a bit crack B, this bit crack B Signals D3 and D4 output clock pulses CL only during the time period of
is reversed.

However, compared to the constant time width T in which both signals D3 and D4 output normal clock pulses CL, bit cracking B
The time width of is extremely small, and therefore the bit cracking B occurs compared to the number of normal lock pulses CL in a constant time width T.
Since the number of clock pulses C in the time width T is much smaller, the output level of the counter signal D5 becomes a digital signal that changes its level in an approximately constant time width T.

The signal level of the counter output signal D5, whose level is inverted in this almost constant time width T, is kept constant by selecting a time point that is not affected by bit cracking B every constant time width T and performing the signal level using the level judgment signal P2. It is possible to obtain the correction signal D6, which is a digital signal with a time width T and no bit cracks T.

The rising and falling points of the digital signal of this correction signal D6 are set according to the generation points of the level determination signal P2, so that they are delayed by more than half a cycle with respect to the old digital signal.

The averaging start signal P1, the level determination signal P2, and the signal determination reference pulse P3 are formed from the power supply signal S3 that is completely synchronized with the input signal S1, regardless of the demodulated digital signal D1. Perfect synchronization to S1 can be maintained. Further, the correction process of the correction circuit 1 for the digital signal 01 is performed using the averaging start signal P1 and the level judgment signal P2 obtained from the power supply signal S3, regardless of the timing of the demodulated digital signal D1. Even if there is a synchronization shift in the demodulated digital signal D1, the correction signal D6, which is a digital signal with a constant timing and an accurate fixed time width T, is formed regardless of this synchronization shift.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing one embodiment of the present invention.

FIG. 1 shows a basic circuit configuration block diagram of an embodiment of the device of the present invention, in which a first filter 4, a first amplifier circuit 5, a second filter 6, a second amplifier circuit 7, and a third filter are shown. 8
Since the combination of the fourth filter 9 and the fourth filter 9 is exactly the same as in the prior art, the digital signal 01 input to the correction circuit 1, which is the main component of the present invention, still contains signal distortion. . The correction circuit 1 is configured to include the function of the synchronization signal circuit 110 of the prior art, and the signal discrimination circuit 10 which inputs the correction signal D6 which is the output from the correction circuit 1 and forms the data signal D7 is different from the conventional technology. It's the same.

The basic operation of the present invention shown in FIG. 1 is as shown in FIGS. 2(a), (, b), (c
), as shown in (d), are completely the same as the conventional technology, but as shown in FIG. 2(e), the correction signal D6 obtained by correcting the digital signal D1 by the correction circuit 1 is The data signal 07, which is finally formed by the signal judgment circuit 10 based on this correction signal D6, is delayed by almost half a period, and is delayed by almost half a period compared to the conventional technology. You'll be late.

FIG. 3 shows a specific example of the configuration of the correction circuit 1, which is the main part of the present invention.

The correction circuit 1 includes a timing generation circuit B2 and an averaging circuit section 3.

The timing generation circuit section 2 includes a bandpass filter 2a that receives a power signal S3 completely synchronized with the input signal S1, an allpass filter 2b, and a pulse generation circuit 2c.
The band-pass filter 2a removes harmonics and the like contained in the power signal S3, and the all-pass filter 2b removes harmonics and the like contained in the power signal S3.
The deviation caused by this is corrected to ensure synchronization, and the pulse generation circuit 2c generates an averaging start signal P1, a level determination signal P2, and a signal determination reference pulse P3.

In power-synchronized transfer, the bits are switched at the peak of the sine wave of the commercial frequency power source, so the timing generation circuit section 2 generates an averaging start signal P1 synchronized with the commercial frequency power source, a level judgment signal P2, and a signal judgment signal. Therefore, the all-pass filter 2b allows stable generation timing of each pulse signal even with frequency fluctuations of the power supply, and also allows each pulse signal to be generated between the commercial frequency power supply and the carrier signal. The transmission signal S2 can be completely synchronized with the transmission signal S2.

The averaging circuit unit 3 includes an inverting circuit 3a that forms an inverted digital signal D2 from the digital signal D1, and inputs the inverted digital signal D2 and clock pulse CL from the inverting circuit 3a to form an inverted clock digital signal D4. A first OR circuit 3b, a second OR circuit 3c which inputs the digital signal D1 and the clock pulse C to form the clock digital signal D3, and a second OR circuit 3c which inputs the inverted clock digital signal D4 to the up terminal and forms the clock digital signal D3.
is input to the down terminal, and the averaging start signal P1 is input to the clear terminal to output the counter output signal D5.The counter output signal D5 is input to the data terminal and the level judgment signal P2 is output.
The device up/down counter 3d, which is composed of a flip-flop circuit 3e which inputs the clock pulse CL to the clock terminal and outputs the correction signal D6, calculates the number of clock pulses CL input to the UP terminal and the number of clock pulses CL input to the DOWN terminal. If the number of clock pulses CL input to the up terminal side is large, a high level signal is output, and conversely, if the number of clock pulses CL input to the down terminal side is large, a low level signal is output. , the count is cleared by inputting the averaging start signal P1 to the clear terminal.

In this way, the up/down counter 3d accumulates and subtracts the clock pulses CL distributed to the up side and the down side at intervals of a fixed time width T, at approximately the same period, so that it is difficult to avoid the effects of bit cracking B, for example. Even if a clock pulse CL is temporarily input to the other side terminal, the number of pulses temporarily input to the other side terminal is
Since this is much smaller than the cumulative number of pulses input to the one side terminal, the output signal level of the up/down counter 3d is maintained constant without changing. For example, the fourth
In the case shown in the figure, the clock pulse CL is input to the down terminal side between time t3 and t4 due to the Bi-Soto crack B, but the time from time t3 to t4 is the same as the time from time t2 to t3. Since the time is shorter, the number of pulses input to the down terminal from time t3 to t4 is
The number of pulses input to the up terminal between 2 and t3 is smaller than the number of pulses input to the up terminal side, so the counter output signal D5 is
To maintain the output level constant without being affected by bit cracking.

In the embodiment shown in FIG. 4, the averaging start signal P
1 is the rising time t of the digital signal D1.
The reason for setting the time t2 to be slightly later than 1 is because the time t1 coincides with the peak of the power supply voltage, so attenuation distortion is likely to occur in the transmission signal S2 due to the influence of load impedance, etc. This is to prevent attenuation distortion from affecting the waveform shape of the counter output signal D5. Similarly, the reason why the output point of the level judgment signal P2 is set slightly earlier than the end point t5 of the digital signal D1 is to prevent it from being affected by the attenuation distortion of the transmission signal S2, and to make the level judgment By setting the up/down counter 3d as close to the completion of the counting operation as possible, the cumulative number of pulses on one side terminal becomes a sufficiently large value, and even if a pulse is input to the other side terminal due to the influence of bit crack B. This is because the level of the counter output signal 05 is never inverted even when the counter output signal 05 is inverted.

〔Effect of the invention〕

Since the present invention has the above-described configuration, it has the following effects.

By distributing clock pulses according to the digital signal and averaging the distributed clock pulses, signal distortion such as bit splitting can be completely removed, thereby ensuring accurate demodulation of the transmitted signal.

The averaging start signal, level judgment signal, and signal judgment reference pulse are not obtained from the digital signal during demodulation, but are formed directly from the power supply signal, so there is a synchronization difference with the transmission signal at the time of each signal processing. It is possible to obtain a faithful data signal synchronized with the power supply without causing any noise.

Since the averaging operation is achieved by an up/down counter, it is not affected by changes in characteristics of resistors, capacitors, etc. due to temperature changes, and high reliability can be achieved.

Since the clock pulses are simply distributed according to the digital signal and the distributed clock pulses are averaged by an up/down counter, the circuit configuration is simple, and the circuit configuration of the demodulator can therefore be simplified.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing the circuit configuration of an embodiment of the device of the present invention. FIG. 2 is a waveform diagram showing the basic signal processing procedure of the method of the present invention. FIG. 3 is a block diagram showing the circuit configuration of the correction circuit which is the main part of the device of the present invention. FIG. 4 is a waveform diagram illustrating the operation of the correction circuit shown in FIG. 3. FIG. 5 is a block diagram showing a typical circuit configuration of a conventional demodulator. FIG. 6 is a waveform diagram illustrating the demodulation operation by the conventional demodulator shown in FIG. Explanation of symbols 1: Correction circuit, 2: Timing generation circuit section, 2a: Band pass filter, 2b: All pass filter, 2c: Pulse generation circuit, 3: Averaging circuit section, 3a + inverting circuit, 3b: First [IR circuit] , 3c; second [IR circuit,
3d; up/down counter; 3e; flip-flop circuit; 4; first filter; 5; first amplifier circuit; 6; second
Filter, 7; Second amplifier circuit, 8; Third filter, 9;
4th filter, 10; Signal judgment circuit, 11; Synchronous signal circuit, Sl: Input signal, S2: Transmission signal, S3: Power supply signal, Pl: Averaging start signal, P2: Level judgment signal, P3: Signal judgment standard Pulse, Dl: Digital signal, D2: Inverted digital signal, D3: Clock digital signal, D4: Inverted clock digital signal, D5: Counter output signal, D6: Correction signal, Dl: Data signal, CL
; Clock pulse, T: Fixed time width, B: Bit cracking. Burari l's 1-11 111 JL times 2-m-tie 3〉7
No. g Sum O Shishi (Door 202b-゛-1-rV H-shape +1/7 2C---)
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Claims (5)

[Claims] (1) Convert the input transmission signal (S2) into a digital signal (D1)
) and create two signals, a clock digital signal (D3) and an inverted clock digital signal (D4), whose polarities are mutually inverted and a clock pulse is added from the digital signal (D1). , the magnitude relationship of the cumulative number of clock pulses between the clock digital signal (D3) and the inverted clock digital signal (D4) is determined at intervals of a constant time width (T) which is the code time width of the digital signal (D1). Obtain a counter output signal (D5) shown in FIG. (D6) A method for demodulating a transmission signal, in which the level of the signal (D6) is determined at intervals of the constant time width (T) and demodulated into a data signal. (2) The start point of calculating the cumulative number of clock pulses between the clock digital signal (D3) and the inverted clock digital signal (D4) is set to a point slightly delayed from the rising point of the digital signal (D1). The method of demodulating a transmission signal according to claim 1. (3) The level determination point of the counter output signal (D5) indicating the magnitude relationship of the cumulative number of clock pulses between the clock digital signal (D3) and the inverted clock digital signal (D4) is determined from the clock digital signal (D3). The transmission signal according to claim 1 or 2, wherein the transmission signal is set at a point near the end of the code time of the digital signal (D1), which is the same as the start point of the calculation of the cumulative number of clock pulses between the inverted clock digital signal (D4) and the inverted clock digital signal (D4). demodulation method. (4) A plurality of filters and a plurality of amplifier circuits that separate the transmission signal (S2) from the input signal (S1) and convert the transmission signal (S2) into a digital signal (D1), and the input digital signal (D1). ), a correction circuit (1) that outputs a correction signal (D6) corrected for the input signal (S1), and generates and outputs a reference pulse (P3) for signal determination from a power supply signal (S3) synchronized with the input signal (S1); Input correction signal (
A signal determination circuit (D6) that determines the level of the signal determination signal (D6) using the signal determination reference pulse (P3) and creates a data signal (D7).
10), and converts the correction circuit (1) into two clock digital signals (D3) with inverted polarity and an inverted clock digital signal (D4) from a power supply signal (S3) synchronized with the input signal (S1). The averaging start signal (P1) that commands the start of calculation of the cumulative number of clock pulses between Counter output signal (D5)
A timing generation circuit section (2) that generates and outputs a level judgment signal (P2) that commands level judgment and a reference pulse (P3) for signal judgment; Inverted clock digital signal (D
4) is input to the up-side terminal, a clock digital signal (D3) obtained by adding a clock pulse (CL) to the input digital signal (D1) is input to the down-side terminal, and the averaging start signal is input to the clear terminal. (P1) is inputted, and the counter output signal (D5) which is the output signal of the up/down counter (3d) is inputted to the data terminal, and the level judgment signal (
The averaging circuit section (3e) is composed of a flip-flop circuit (3e) which is a D-type flip-flop that inputs the signal P2) to the clock terminal and outputs the correction signal (D6).
) and a transmission signal demodulator consisting of (5) The timing generation circuit section (2) includes a bandpass filter (2a) that removes harmonics etc. from the input power signal (S3), and an all-pass filter that corrects timing deviation caused by the bandpass filter (2a). Filter (2
b) and a pulse generator that generates an averaging start signal (P1), a level judgment signal (P2), and a reference pulse for signal judgment (P3) according to the power signal (S3) whose deviation has been corrected by the all-pass filter (2b). Circuit (2c
) A demodulating device for a transmission signal according to claim 4.