JPS62151047A - Pll synchronization supervising circuit - Google Patents

Abstract

PURPOSE:To prevent an undesired signal for a prescribed time or over from being outputted to a FSK demodulation circuit output by detecting a frequency of an output signal of a digital PLL FSK demodulation circuit and discriminating the out of synchronism from the result to detect a line fault of PCM transmission system at a high speed. CONSTITUTION:A synchronization supervisory circuit comprising MMV monostable multivibrators 4, 5 and a logic circuit 6 is provided. The multivibrator MMV4 generates a pulse of a width T1 at the rising of an output signal (a) of a digital PLL circuit 1 and the multivibrator MMV5 generates a pulse of a width T2 at the rising of the output pulse. When no rising of the signal (a) exists at an input B while the pulse exists, the logic circuit 6 discriminates it as out of synchronizm, a fault detection signal in an output signal (c) and the result is fed to a comparator 3. When the fault detection signal is given to the comparator 3, the output is locked to prevent an undesired signal from being kept in a demodulation output OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase-locked loop) synchronization monitoring circuit, and particularly to a PLL synchronization monitoring circuit that detects and monitors phase synchronization of a demodulating PLL circuit in an FSK communication system.

Conventional technology Conventionally, FDM (Frequency Division)
ion Multiplex) transmission line failures include instantaneous interruptions (level interruptions) and noise generation. Momentary interruptions (level interruptions) can be detected by adding a level drop detection circuit, and noise detection can be detected by adding a circuit that detects only the noise component, both of which can be detected at high speed. It is possible.

However, in the PCM transmission line, there is a conversion process between analog and digital signals, so if a data error or loss of synchronization occurs in the digital signal part, when converting to an analog signal, the FDM transmission system This causes signal disturbances that would otherwise occur, making it impossible for conventional line fault detection circuits to detect them at high speed. In particular, FSK demodulation circuits using digital PL are susceptible to signal disturbances and have the disadvantage of losing phase synchronization and outputting unnecessary signals.

The present invention eliminates the drawbacks of the conventional system, and its purpose is to detect line failures in the PCM transmission system at high speed, and remove unnecessary signals at the output of the FSK demodulation circuit for a certain period of time or longer. An object of the present invention is to provide a PLLno monitoring circuit that does not output the PLLno.

Structure of the Invention According to the present invention, there is provided a synchronization monitoring circuit for a digital PLL (phase-locked loop) circuit for modulating an FSK modulated wave input, which detects the frequency of an output signal of the PLL circuit and determines whether this frequency is a predetermined frequency. The PLL synchronization monitoring circuit is characterized in that it is determined that the PLL circuit is out of synchronization when the frequency is outside the frequency range.

Embodiment A device according to an embodiment of the present invention will be explained with reference to the block diagram shown in FIG.

Digital PLL circuit 1. Low pass filter 2. Comparator 3. The output terminals OUT are sequentially connected in cascade to form an FSK demodulation circuit. The output of the digital PLL circuit 1 is connected to the input of a monostable multivibrator (hereinafter referred to as MMV) 4 and the input B of a logic circuit 6, respectively.
V4. MMV5 are cascaded. The output of MMV5 is connected to input A of the logic circuit, and the output of logic circuit 6 is connected to input B of comparator 3.

In FIG. 1, the output a of the digital PLL circuit is phase-synchronized with the input signal. When the input frequency changes, the duty ratio of the output a changes, and the output a stabilizes in phase synchronization with the input signal.

The low-pass filter 2 receives the output signal a of the digital PLL circuit 1.
harmonics are removed and changes in duty ratio are converted into changes in the DC signal. The output converted into a DC signal by the low-pass filter 2 is connected to an input A of a comparator 3, which has a certain voltage as a reference, and is converted into a logic level signal. Therefore, it is possible to discriminate whether the input signal frequency is higher or lower than a certain reference frequency (determined by the internal reference voltage of the comparator).

Here, if disturbance occurs in the input signal for some reason, the digital PLL circuit 1 loses phase synchronization,
After the duty ratio changes and the input signal is restored to normal, the gate output OUT is
Unnecessary signals are output for quite a long time.

Therefore, in order to prevent this, MMV4.5 and logic circuit 6
A synchronization monitoring circuit is provided.

In FIG. 1, an MMV4 that generates a pulse with a width of time T1 at the rise of the output signal a of the digital PLL circuit 1 and an MMV5 that generates a pulse with a width of time T2 at the rise of the output pulse of this MMV4 are connected in cascade, MMV
5 is connected to the input A of the logic circuit 6. If the output signal a of the digital PLL circuit 1 does not rise at the input B while there is a pulse with a width of time T2 on the input A, the logic circuit 6 determines that the synchronization is out of order, and the logic circuit 6
An abnormality detection signal is outputted to the output signal C of the circuit, and this is added to the input B of the comparator 3.

Here, the synchronization loss will be explained. In Figure 3, the range of change in the input signal is f HHAX, f LHA
As X, if there is a signal frequency between them, it is normal, f HH
When the signal frequency is higher than AX or lower than f L WAX, it is considered abnormal and out of synchronization. f H
The value of HAX is set in MMV4, and the value of fL HAX is set in MMV5. That is, a window is provided for the signal frequency, and when a frequency component other than that is detected, the synchronization is determined to be out of synchronization.

In the comparator 3, when an abnormality detection signal is applied to the input 8, the output is locked to prevent unnecessary signals from being cascaded to the demodulated output 0tJT.

MMV4. MMV5 is the maximum frequency of the input signal.

The pulse width T1. All you have to do is set T2. Regarding the abnormality detection time of the logic circuit 6, for example, by providing a counter circuit, it is possible to output the abnormality detection after the abnormality has continued N (integer) times, or to output the abnormality detection output after the abnormality has continued for N (integer) times, or to output the abnormality detection output after the abnormality has been restored to normal for M (integer) times. It is also possible to cancel the abnormality detection output after confirming that.

Effects of the Invention As described above, the present invention provides a window for detecting the output frequency of a PLL circuit and detects an output outside the range by detecting a time T1 after a time T1 from the rising edge of a phase synchronization signal.
Digital PLLI
The normal frequency range of the FSK demodulation circuit output can be constantly monitored, making it possible to prevent unnecessary signals from being output for a certain period of time or longer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing waveform diagram showing the operation of the blocks in FIG. 1, and FIG. 3 is a diagram showing the out-of-synchronization detection range of the blocks in FIG. 1. Explanation of symbols of main parts 1...PLL 4, 5...MMV 6...Logic circuit

Claims (2)

[Claims] (1) Digital P for demodulating FSK modulated wave input
A synchronization monitoring circuit for an LL (phase locked loop) circuit, which detects the frequency of the output signal of the PLL circuit and determines that the PLL circuit is out of synchronization when this frequency is outside a predetermined frequency range. A PLL synchronization monitoring circuit characterized by: (2) means for generating a signal for a predetermined period of time after a predetermined period of time from the change point of the output signal of the PLL circuit, and means for comparing the signal generated during this predetermined time with the next successive change point of the output signal. 2. A PLL synchronization monitoring circuit according to claim 1, wherein the PLL synchronization monitoring circuit comprises: a PLL synchronization monitoring circuit, and is configured to determine whether the PLL circuit is out of synchronization based on the comparison result.