JPH04235438A - Line switching information generating circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale and to quickly transmit line switching information in a line switching informaiton generating circuit used, for example, in switching a ratio line transmitting a digital signal. CONSTITUTION:A digital multiplexed ratio system is provided with a transmitter 1 at the transmission side, and a receiver that incorporates a detection/ conversion part 2 taking out an orthogonal base band signal and converting it into the digital signal and a carrier wave reproduction part 3 which generates and transmits a control signal controlling the generated frequency of an applicable voltage control generator by means of the output of the detection/ conversion part and transmits a synchronizing step-out signal when the synchronization is stepped-out at the reception side. In the digital multiplexed ratio system, a wind comparator 5 transmitting an alarm signal when it is detected that the preset level of the applicable control signal is outside the preset level, and an OR means 6 transmitting a signal obtained by taking the OR of the applicable synchronizing step-out signal and the alarm signal as line switching information, are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching information generating circuit used, for example, in switching multiple radio lines for transmitting digital signals.

[0002] Normally, in order to prevent deterioration of line quality or line disconnection caused by fading that occurs in a wireless line or failure of equipment that makes up the line, for example, a backup line using a different radio frequency is set up in addition to the working line. Be prepared.

[0003] When a fault occurs in the working line, the receiving side detects the occurrence of the fault, sends line switching information to the transmitting side, and switches to the protection line. At this time, it is necessary to reduce the scale of the circuit for generating line switching information and to quickly send out the line switching information.

0004

2. Description of the Related Art FIG. 4 is an example of a schematic block diagram of a digital multiplex radio system, and FIG. 5 is an example of a block diagram of a conventional demodulator. The operation of the figure will be explained below.

First, in FIG. 4, on the transmitting side, input data in the CMI format is converted into unipolar format data that can be easily digitally processed by a CMI/unipolar converter 71, and then sent to a transmitting code converter 72. It will be done.

This converter divides one series of unipolar code into multiple series, then converts the speed to create a gap.
Frame synchronization signals, digital control line signals (monitoring/control signals, etc.), parity bits, etc. used only in the wireless section are inserted, scrambled and sent to the modulator 73.
Send to.

[0007] Therefore, the modulator 73 digitally modulates the carrier wave using the applied digital signal to generate a digitally modulated wave (for example, a 16 QAM wave).
It is converted to a predetermined frequency and power and sent to the receiving side.

On the receiving side, the received signal is frequency-converted into a received signal in an intermediate frequency band, and then demodulated by a demodulator 74 to extract a digital signal and sent to a receiving code converter 75. The receiving code converter performs the reverse processing to that on the transmitting side and extracts the digital control signal, parity bit, etc. inserted on the transmitting side.
Play MI format data.

[0009] Here, the line quality is determined using the parity bit extracted by the reception code converter, but when it is detected that the line quality has fallen below a specified value, the line quality is The switching information (parallel transmission command) is sent to the transmitting side via a digital control line separate from the data transmission line.The transmitting side drives a transmitting switch T-SW (not shown) to send the above input data to the faulty working line. Since the data is also sent to the protection line in parallel with the data, the data appears in the reception code converter section (not shown) of the protection line on the receiving side.

[0010] Therefore, on the receiving side, after adjusting the phase of the latter so that the phases of the data passing through the faulty working line and the protection line match, the faulty working line is switched to the protection line, but since the phases match, , switching without momentary interruption is possible.

Next, in FIG. 5, the input intermediate frequency band reception signal (for example, 16 QAM wave) is distributed by a hybrid 21 and applied to detectors 22a and 22b. Here, the output from the voltage controlled oscillator 4 is distributed by the 90 degree hybrid 26 and added as a regenerated carrier wave with a phase difference of 90 degrees, so the received signal is detected and converted into an Ich baseband signal. A Qch baseband signal is extracted.

[0012]The two baseband signals are then filtered through the corresponding low-pass filters 23a and 23b to remove noise, and then passed through the transversal equalizer 2.
The signals are applied to analog/digital converters (hereinafter abbreviated as A/D converters) 25a, 25b after being subjected to waveform equalization.

On the other hand, bit timing recovery (B
TR) The circuit 27 regenerates the clock using the intermediate frequency band reception signal distributed by the hybrid 21, and the A/D
It is sent to the converter and each necessary part.

[0014] Therefore, A/D converters 25a and 25b
converts the analog signal into a digital signal using the applied reproduction clock and sends it to the outside as Ich data and Qch data, and also sends, for example, the first bit and error bit of the digital signal to the carrier wave recovery circuit 3.

The carrier wave regeneration circuit 3 is configured in a well-known Costas type, and uses the applied Ich and Qch first bits and error bits to generate a control signal and send it to the voltage controlled oscillator 4. When the output of the oscillator becomes out of synchronization with the carrier wave on the transmitting side, an out-of-synchronization signal is sent out.

[0016]

[Problem to be solved by the invention] As mentioned above, since the quality of the wireless line is monitored using the parity bit, a part for inserting the parity bit is required on the transmitting side, and On the side, a part to detect the parity bit is required.

[0017]Therefore, there is a problem in that the circuit scale of the transmit code converter and the receive code converter in which this part is implemented becomes large. Further, when the line quality is very poor, it takes only a short time to make a quality judgment, but when the line quality is rather poor, it takes time to make a judgment, so there is a problem that it takes a long time to send the line switching information.

The object of the present invention is to reduce the circuit scale and quickly send out line switching information.

[0019]

SUMMARY OF THE INVENTION FIG. 1 shows a block diagram of the principle of the present invention. In the figure, 1 is a transmitter that digitally modulates a carrier wave using an input digital signal and sends it out.
2 is a detection/conversion unit that uses the output of the voltage controlled oscillator to detect the input received signal and extract the orthogonal baseband signal, and then converts it into a digital signal; 3 is the output of the detection/conversion unit; A control signal is generated to control the oscillation frequency of the voltage controlled oscillator so that the output of the voltage controlled oscillator is synchronized with the carrier wave. be.

Further, 5 is a window comparator that sends out an alarm signal when it detects that the level of the control signal is out of a preset range, and 6 is a logical sum of the out-of-synchronization signal and the alarm signal. This is an OR means that sends out a signal as line switching information.

[0021]

[Operation] The present invention applies a control signal sent from a carrier wave regeneration circuit to a window comparator. Here, the control signal is in a substantially constant state when the line quality has not deteriorated, but if it deteriorates, it deviates from the constant state and becomes a random state.

[0022] Therefore, the window comparator outputs, for example, '0' when the line quality has not deteriorated, and '1' when it is outside the window, but by changing the window width, the line outputs '1'. Quality values can be changed.

Therefore, by using a control signal instead of the conventional parity bit as the line switching information, it becomes possible to quickly send out the line switching information and reduce the circuit scale. Note that when the output of the voltage controlled oscillator becomes asynchronous with the carrier wave on the transmitting side, the control signal takes a random value, so the out-of-synchronization signal sent from the carrier wave regeneration circuit is used as the line switching information in this case.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is an example of a demodulator block diagram to which the present invention is applied, and FIG. 3 is an explanatory diagram of the operation of FIG.

Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. Also, the same reference numerals indicate the same objects throughout the figures. Here, hybrid 21,
26, detector 22a, 22b, low pass filter 2
3a, 23b, transversal equalizer 24a
, 24b, A/D converters 25a, 25b, and bit timing recovery circuit 27 are components of the detection/conversion section 2, and the OR gate 61 is a component of the logical sum means.

The operation of FIG. 2 will be explained below with reference to FIG. 3. Since the operations other than those shown by dotted lines in FIG. 2 have already been explained, they will be briefly explained, and the parts of the present invention will be explained in detail. In Figure 2, the input intermediate frequency band reception signal is
1 to the detectors 22a and 22b.

Here, since the output from the voltage controlled oscillator 4 is added as a regenerated carrier wave via the 90-degree hybrid 26, the received signal is detected and an Ich baseband signal and a Qch baseband signal are extracted. It will be done.

These two baseband signals are then passed through corresponding low-pass filters 23a and 23b.
Transversal equalizer 24a, 24
After waveform equalization is applied to A/D converters 25a and 25b.

On the other hand, the bit timing recovery circuit 27 uses the intermediate frequency band reception signal distributed by the hybrid 21 to recover a clock and sends it to the A/D converter and other necessary parts.

[0030] Therefore, A/D converters 25a, 25b
converts the analog signal into a digital signal using the applied reproduction clock and sends it to the outside as Ich data and Qch data, and also sends, for example, the first bit and error bit of the digital signal to the carrier wave recovery circuit 3.

The carrier wave regeneration circuit 3 is configured in a well-known Costas type, and uses the first bit of the applied Ich and Qch and the error bit to perform control so that the regenerated carrier wave and the carrier wave on the transmitting side are in a synchronized state. A signal is generated and sent to the voltage controlled oscillator 4 and the window comparator 5, but when an out-of-synchronization condition occurs, an out-of-synchronization signal is sent out to the outside.

Here, the window comparator is shown in FIG.
As shown in (2), the threshold value has two values, V1 and V2, and if the input voltage V2 is V2<V<V1, the output is, for example, '0'. However, if V2>V or V>V1, '1' is output (see Fig. 3-2).

Now, when waveform distortion occurs due to fading or the like occurring in the radio line, the transversal equalizers 24a and 24b find it difficult to equalize, the carrier wave regeneration circuit 3 no longer performs the carrier wave regeneration operation, and the control signal is Since the values are random as shown at points a, b, and c in FIG.

On the other hand, since the output of the window comparator 5 also randomly outputs 1 and 0, the output of this comparator and the out-of-synchronization signal are ORed by an OR gate 61 and used as line switching information.

[0035] As a result, parity bits are not used, so parts such as parity bit insertion and extraction become unnecessary, and line switching information can be sent out quickly.

[0036]

As described above in detail, the present invention has the advantage of reducing the circuit scale and speeding up line switching preparation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is an example of a demodulator block diagram to which the present invention is applied.

FIG. 3 is an explanatory diagram of the operation in FIG. 2;

FIG. 4 is an example of a schematic block diagram of a digital multiplex radio system.

FIG. 5 is an example of a conventional demodulator block diagram.

[Explanation of symbols]

1 Transmitting device 2 Detection/conversion section 3 Carrier wave regeneration section 4 Reference oscillator 5 Window comparator 6 Logical sum means

Claims (1)

[Claims] Claim 1: A transmitting device (on the transmitting side) that digitally modulates a carrier wave using an input digital signal and transmits the modulated carrier wave.
1) is installed on the receiving side using the output of the voltage controlled oscillator (4) to detect the input received signal, extract the orthogonal baseband signal, and then convert it into a digital signal.
A conversion unit (2) and the output of the detection/conversion unit are used to generate a control signal for controlling the oscillation frequency of the voltage controlled oscillator so that the output of the voltage controlled oscillator is synchronized with the carrier wave, In a digital multiplex radio system having a receiving device including a carrier wave regenerating section (3) that sends out an out-of-synchronization signal when out of synchronization, an alarm signal is generated when it is detected that the level of the control signal is out of a preset range. a window comparator (5) that sends out the out-of-synchronization signal and an alarm signal, and a logical sum means (6) that sends out a signal obtained by taking the logical sum of the out-of-synchronization signal and the alarm signal as line switching information. circuit.