JPH1168866A - Digital demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time till a normal locking state is reached at momentary interruption of a modulation signal at raising of a power supply or the like. SOLUTION: A voltage controlled oscillator VCO receives a VCO control signal Dc via a logic circuit 84 and generates a sampling clock Cs and outputs an asynchronous alarm signal A1 in the asynchronous state. A differential coefficient discrimination circuit 82 discriminates a differential coefficient of a waveform at a current sampling based on output data Di, Dq and detects a deviation from an optimum sampling point and outputs a VCO control signal Dc. A data area discrimination circuit 83 discriminates a data area based on output data and discriminates a faulty state, then outputs a fault discrimination signal A2. A logic circuit 84 masks the VCO control signal Dc when the asynchronous alarm signal Al indicates an a synchronous state and the fault discrimination signal A2 denotes a fault.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulator, and more particularly, to a digital demodulator for demodulating a four-phase phase shift keying signal into a baseband signal, and then converting the baseband signal into a digital signal and outputting the converted signal.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional digital demodulator of this type.

[0003] The four-phase shift keying signal S1 is supplied to a distribution circuit 1
And input to the multiplication circuits 2a and 2b respectively, and the reproduced carrier signal S having a phase difference of 90 degrees from each other
3 and S3b, respectively, and demodulated into baseband signals S2a and S2b that are orthogonal to each other.

The baseband signals S2a and S2b are band-limited by low-pass filters 3a and 3b, respectively, amplified by amplifiers 4a and 4b, and then sampled by A / D converters 5a and 5b by sampling clock Cs. And digitized. Then, the flip-flop 6 that operates according to the data extraction clock Cd
The signal components and transition signal components are separated by a and 6b, and output data Di and Dq are extracted.

The reproduced carrier signal S 3 is a signal synchronized with the carrier frequency of the four-phase phase shift keying signal S 1, and is generated by the reproduced carrier generation circuit 7. Regeneration carrier wave generation circuit 7
Is a VCO (Voltage Controlled Oscillator) 71 that oscillates at the carrier frequency of the four-phase shift keying signal S1, and output data Di,
This is a well-known circuit having a frequency control circuit 72 that controls the VCO 71 by performing data area determination based on Dq.

The sampling clock Cs is a clock signal having twice the frequency of the baseband signal, and is generated by the clock synchronization circuit 9. The data extraction clock Cd is a signal generated by dividing the sampling clock Cs by １ ／.

The clock synchronization circuit 9 includes a VCO 91 for generating a sampling clock Cs and output data Di and D
a differential coefficient discriminating circuit 92 for detecting a deviation of the sampling clock Cs from the optimum sampling point based on q and outputting a VCO control signal. A synchronous circuit having such a differential coefficient discriminating circuit is disclosed in Japanese Unexamined Patent Publication No. 61-71.
No. 736.

As described in the above publication, the differential coefficient discriminating circuit 92 calculates the data at the sampling point one time slot before and the data at the current sampling point, and the data at the current sampling point and one time. By comparing the data at the sampling point after the slot with the data at the sampling point, the differential coefficient of the waveform at the current sampling point is determined, and the deviation from the optimum sampling point is detected.

FIG. 5 is a diagram for explaining the operation of the differential coefficient discriminating circuit. For simplicity of explanation, a demodulated baseband signal in the case of a two-phase shift keying signal, a sampling point and digital data X1 , X2. 10A shows a case where the clock phase is normal, FIG. 10B shows a case where the clock phase is advanced, and FIG. 10C shows a case where the clock phase is delayed. There are four types of baseband signal waveforms indicated by a solid line, a broken line, a one-dot chain line, and a two-dot chain line.
One time slot before (T-1), present (T0), and one time slot after (T + 1) are set.

The baseband signal is compared with reference levels L1, L2, and L3 at sampling points, and becomes 2-bit data X1, X2. The data X1 is set to “1” and “0” with the reference level L2 as a boundary. Also,
The data X2 is data indicating positions set to “1” and “0” with the reference levels L1, L2, and L3 as boundaries.

When the clock phase is normal (FIG. 2A), the data X2 indicating the position becomes "1" and "0" with equal probability at all sampling points for the four types of waveforms. However, when the clock phase advances (FIG. 10B), in the baseband signal whose differential coefficient is positive at the sampling point T0, the data X2 is always “1” at the sampling point T0, and the data X1 is at the sampling point T0. It is always "0" at -1. Also,
For a baseband signal having a negative derivative at the sampling point T0, the data X2 is always “0” at the sampling point T0, and the data X1 is at the sampling point T−
1 always becomes “1”.

Therefore, when the clock phase advances, the exclusive OR of the value of data X2 at sampling point T0 and the value of data X1 at sampling point T-1 becomes "1" for all four types of waveforms. Becomes

Similarly, when the clock phase is delayed (FIG. 3C), the data X2 at the sampling point T0 is
Of the data X1 at the sampling point T-1 is "0" for all four types of waveforms.
Becomes In this way, by performing the VCO control with the signal indicating the advance or delay of the clock phase, a sampling clock with the optimal timing can be generated.

[0014]

As described above, in the conventional example, the deviation from the optimum sampling point is detected by the differential coefficient discriminating circuit, and the synchronous control of the sampling clock is performed. However, since the output data input to the differential coefficient discriminating circuit is data extracted by a data extraction clock obtained by dividing the sampling clock by 、, the synchronization pull-in is performed when the power is turned on or when the input modulation signal is momentarily interrupted. In the process, as shown in FIG. 6, a phase difference of 180 degrees easily occurs with respect to the sampling clock.

FIG. 6 (a) shows a state where the phase relationship between the sampling clock and the data extraction clock is normal, and FIG. 6 (b) shows a 180 ° phase difference between the sampling clock and the data extraction clock. Indicates an abnormal condition that has occurred. Here, the black point shown in the baseband signal waveform input to the A / D conversion circuit represents a point to be extracted as a signal. In the normal state, the rising edge of the data extraction clock coincides with the phase of the black point, but in the abnormal state, the rising edge of the data extraction clock does not coincide with the phase of the black point due to a 180 ° phase difference.

As described above, when a phase difference of 180 degrees occurs with respect to the sampling clock in the synchronization pull-in process, an error occurs in the output data input to the differential coefficient discriminating circuit, and until the normal pull-in state is reached. It takes a long time.

An object of the present invention is to provide a digital demodulator capable of shortening the time required for a normal pull-in state when the power is turned on or when a modulation signal is momentarily interrupted.

[0018]

A digital demodulator according to the present invention demodulates a four-phase phase shift keying signal into a baseband signal, and then converts the demodulated signal into digital data using a sampling clock having a frequency twice that of the baseband signal. A digital demodulator for extracting output data by a data extraction clock generated by dividing the sampling clock by 1/2, for detecting that the phase relationship between the sampling clock and the data extraction clock is approaching an abnormal state. When,
Means for masking a VCO control signal supplied to the VCO when the phase of the data extraction clock approaches an abnormal state in the synchronization pull-in process, so that the phase of the data extraction clock is shifted by 180 degrees from the sampling clock. To prevent

Specifically, a VCO (Voltage Controlled Oscillator) that receives the VCO control signal, generates the sampling clock, and outputs an asynchronous alarm signal in an asynchronous state, and a current sampling point based on the output data. And a differential coefficient determining circuit for detecting the deviation from the optimal sampling point and outputting the VCO control signal, and performing a data area determination based on the output data to determine that the state is abnormal. A data area determination circuit that outputs an abnormality determination signal, and receives the asynchronous alarm signal, the abnormality determination signal, and the VCO control signal, respectively, when the asynchronous alarm signal indicates asynchronous and the abnormality determination signal indicates abnormality. The VC
A logic circuit for masking the O control signal.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which the same components as those of the conventional example shown in FIG. The configuration other than the clock synchronization circuit 8 is the same as that of the conventional example.

In FIG. 1, the four-phase phase shift keying signal S1 distributed by the distribution circuit 1 is divided into multiplication circuits 2a and 2b.
, And are respectively multiplied by the reproduced carrier signals S3 and S3b having a phase difference of 90 degrees from each other, so that the baseband signals S2a and S2b are orthogonal to each other.
Is demodulated.

The reproduced carrier signal S 3 is a reproduced carrier signal synchronized with the carrier frequency of the four-phase phase shift keying signal S 1, and is generated by the reproduced carrier generation circuit 7. The reproduction carrier generation circuit 7 performs a data area determination based on a VCO (voltage controlled oscillation circuit) that oscillates at the carrier frequency of the four-phase shift keying signal S1 and the output data Di and Dq, and
And a frequency control circuit for controlling the CO.

The baseband signals S2a and S2b are band-limited by the low-pass filtering circuits 3a and 3b, respectively, amplified by the amplifier circuits 4a and 4b, and then sampled by the AD converter circuits 5a and 5b by the sampling clock Cs. And digitized. Then, the flip-flop 6 that operates according to the data extraction clock Cd
The signal components and transition signal components are separated by a and 6b, and output data Di and Dq are extracted.

The sampling clock Cs is a clock signal having twice the frequency of the baseband signal, and is generated by the clock synchronization circuit 8. The data extraction clock Cd is a signal generated by dividing the sampling clock Cs by １ ／. The configuration described above is the same as the conventional example.

By the way, in the conventional example, it takes time to reach a normal pull-in state when the power is turned on or when the modulation signal is momentarily interrupted. This is because the phase of the data extraction clock is shifted by 180 degrees from the sampling clock in the synchronization pull-in process. The present invention focuses on this point. That is, the present invention detects that the phase relationship between the sampling clock Cs and the data extraction clock Cd approaches an abnormal state, and the phase of the data extraction clock becomes abnormal in the synchronization pull-in process. By masking the VCO control signal when approaching the state,
The phase of the data extraction clock is prevented from being shifted by 180 degrees with respect to the sampling clock, and the time required for a normal pull-in state is reduced.

Next, the clock synchronization circuit 8 will be described.

The clock synchronization circuit 8 has a VCO control signal D
c, generates a sampling clock Cs, and outputs an asynchronous alarm signal A1 when in an asynchronous state. The VCO (voltage controlled oscillator) 81 outputs the output data Di,
A differential coefficient discriminating circuit 82 for detecting a deviation of the sampling clock Cs from the optimum sampling point based on Dq and outputting a VCO control signal Dc; a sampling clock Cs and a data extracting clock by performing area determination based on the output data Di and Dq Masks the VCO control signal Dc supplied to the VCO 81 in response to the data area determination circuit 83 for detecting an abnormality in the phase relationship with Cd and the asynchronous alarm signal A1 from the VCO 81 and the abnormality determination signal A2 from the data area determination circuit 83. And a logic circuit 84 that performs the operation.

The VCO 81 has a function of detecting an asynchronous state and outputting an asynchronous alarm signal A1. For example, by monitoring the fluctuation of the VCO control signal Dc, it is detected that the VCO is in an asynchronous state and is in a synchronization pull-in process.

The differential coefficient discriminating circuit 82, as in the conventional example,
By comparing the output data at the sampling point one time slot before and the output data at the current sampling point, and the output data at the current sampling point with the output data at the sampling point one time slot after, respectively, Determine the derivative of the waveform at the current sampling point, detect the deviation from the optimal sampling point, and
An O control signal Dc is output.

The data area determination circuit 83 is a circuit for detecting that the phase relationship between the sampling clock Cs and the data extraction clock Cd is abnormal. An example of the algorithm will be described.

As shown in FIG. 6B, in an abnormal state where a phase difference of 180 degrees has occurred, the output data is concentrated in the shaded area. FIG. 3 is a diagram showing an output data area in the case of a four-phase shift signal, and shows upper three bits X1, X2, and X3 of the output data. Further, the data convergence point in a normal state is indicated by a black circle, and the area in an abnormal state is indicated by a hatched line. In the abnormal state area, the upper 3 bits X of the output data
1, X2, X3 is "1,0,0" or "0,1,1"
Becomes Therefore, the upper 3 bits X1, X
By detecting that 2,2 becomes “1,0,0” or “0,1,1”, it can be determined that the phase relationship between the sampling clock Cs and the data extraction clock Cd is abnormal.

FIG. 2 shows an example of a basic circuit of the data area determination circuit 83. The upper three bits X1, X2 of the output data are shown.
2 and X3. here,
X1, X2, and X3 are "1,0,0" or "0,1,
When it becomes "1", it is determined that the state is abnormal, and the abnormality determination signal A2 is set to "0".
Is output to the logic circuit 84 as “1”.

The logic circuit 84 includes an asynchronous alarm signal A1 from the VCO 81, an abnormality determination signal A2 from the data area determination circuit 83, and a VC from the differential coefficient determination circuit 82.
O control signals Dc, respectively, and an asynchronous alarm signal A
When both 1 and the abnormality determination signal A2 indicate an abnormal state, the supply of the VCO control signal Dc is masked.

With such a configuration, it is possible to prevent the phase of the data extraction clock from being shifted from the sampling clock by 180 degrees in the synchronization pull-in process, so that the time required for a normal pull-in state is reduced. it can.

[0036]

As described above, according to the present invention, 4
After demodulating the phase shift keying signal to a baseband signal,
In a digital demodulator, a digital clock is converted into digital data by a sampling clock having a frequency twice as high as that of a baseband signal, and output data is extracted by a data extraction clock generated by dividing the sampling clock by 1/2.
Means for detecting that the phase relationship between the sampling clock and the data extraction clock has approached an abnormal state, and masking a VCO control signal to be supplied to the VCO when the phase of the data extraction clock has approached an abnormal state during the synchronization pull-in process. Means to prevent the phase of the data extraction clock from being shifted from the sampling clock by 180 degrees, so that a normal pull-in state is obtained at power-on or instantaneous interruption of the modulation signal. The time until the time can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a data area determination circuit 83 shown in FIG.

FIG. 3 is a diagram showing an area of output data in the case of a four-phase shift signal;

FIG. 4 is a block diagram showing a conventional digital demodulator.

FIG. 5 is a diagram for explaining the operation of the differential coefficient discriminating circuit.

FIG. 6 is a diagram showing a phase relationship between a sampling clock and a data extraction clock.

[Explanation of symbols]

 8 Clock Synchronization Circuit 81 VCO (Voltage Controlled Oscillation Circuit) 82 Derivative Coefficient Discrimination Circuit 83 Data Area Determination Circuit 84 Logic Circuit A1 Asynchronous Alarm Signal A2 Abnormality Determination Signal Cd Data Extraction Clock Cs Sampling Clock Dc VCO Control Signal Di, Dq Output Data S1 Four-phase shift keying signal S2a, S2b Baseband signal

Claims (6)

[Claims] 1. After demodulating a four-phase phase shift keying signal into a baseband signal, the demodulated signal is converted into digital data by a sampling clock having a frequency twice as high as that of the baseband signal, and the sampling clock is further divided by 1/2. In a digital demodulator for extracting output data by a generated data extraction clock, a VCO (voltage control oscillation circuit) that generates the sampling clock controlled by a VCO control signal, and generates the VCO control signal based on the output data Means for detecting that the phase of the data extraction clock is approaching an abnormal state in which the phase of the data extraction clock is shifted by 180 degrees with respect to the sampling clock, and the phase relationship between the sampling clock and the data extraction clock is abnormal during the synchronization pull-in process. When approaching the state, the VCO
Means for masking a control signal. 2. The data area determination circuit according to claim 1, further comprising: a data area determination circuit configured to perform an area determination of the data based on the output data and output an abnormality determination signal when it is determined that the state is abnormal. The digital demodulator according to claim 1, further comprising: 3. The data area determination circuit according to claim 1, wherein upper three bits of the output data are “1, 0, 0” or “0, 1,
The digital demodulator according to claim 2, wherein the digital demodulator is a logic circuit that determines an abnormal state when "1" is set. 4. The VCO has a function of outputting an asynchronous alarm signal when the VCO is in a synchronization pull-in process, and the mask means receives the asynchronous alarm signal, the abnormality determination signal, and the VCO control signal, respectively. 4. The digital demodulator according to claim 3, wherein the digital demodulator is a logic circuit that masks the VCO control signal when the asynchronous alarm signal indicates asynchronous and the abnormality determination signal indicates abnormality. 5. The means for generating the VCO control signal comprises:
2. A differential coefficient determining circuit for determining a differential coefficient of a waveform at a current sampling point based on the output data, detecting a deviation from an optimal sampling point, and outputting the VCO control signal. Digital demodulator. 6. After demodulating a four-phase phase shift keying signal into a baseband signal, the signal is converted into digital data by a sampling clock having a frequency twice as high as that of the baseband signal, and the sampling clock is further divided by 1/2. In a digital demodulator for extracting output data by a generated data extraction clock, a VCO (Voltage Controlled Oscillator) that receives a VCO control signal, generates the sampling clock, and outputs an asynchronous alarm signal when in an asynchronous state
A differential coefficient determining circuit that determines a differential coefficient of a waveform at a current sampling point based on the output data, detects a deviation from an optimum sampling point, and outputs the VCO control signal, and a data area based on the output data. A data area determination circuit that outputs an abnormality determination signal when it is determined that the state is abnormal, and receives the asynchronous alarm signal, the abnormality determination signal, and the VCO control signal, and determines whether the asynchronous alarm signal is asynchronous. And a logic circuit for masking the VCO control signal when the abnormality determination signal indicates an abnormality.