JPS6314544A - Data extracting circuit - Google Patents

Abstract

PURPOSE:To prevent an erroneous discrimination caused by a noise, by forming a Schmitt circuit having a hysteresis corresponding to a deviation of an input of a selector. CONSTITUTION:When it is detected by a comparator 30 that a count value of an up-down counter 20 exceeds a value from a terminal A corresponding to the upper limit voltage value VP which has been designated by a selector 40, an output of a comparing terminal C of the comparator 30 becomes '1', and an output of the selector 40 is switched to the loser limit voltage VN. Also, until the next down-pulse arrives, the up-down counter 20 maintains a preset value. When the down of the up-down counter 20 advances, and coincides with the lower limit voltage VN which has been set by the selector 40, an output of a D flip-flop 50 is used an a discriminating data and led out to a data output terminal OUT.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data extraction circuit, and in particular to a data extraction circuit that prevents incorrect extraction of data from being affected by noise. Regarding.

(Prior Art) Generally, in order to extract transmitted data without errors, a method such as transmitting at a predetermined level is used. In some cases, it also reduces malfunctions in data placement in majority circuits and the like.

FIG. 3 is a circuit diagram showing a conventional data extraction circuit,
Data from the digital transmission line is applied to the input terminal IN,
Input buffer circuit 1. Whoopass filter 2. The extracted data is output to the output terminal OUT via the output buffer circuit 3. The input/output buffer circuits 1.3 each include a Schmitt circuit or the like, detect the upper limit level and lower limit level of the input data, perform data identification, and output the identification results to the output terminal OUT. A data extraction circuit having such a configuration includes resistors 4. Due to fluctuations in the element value of the resistor 5 or fluctuations in the input thresholds of the human output buffers 1 and 3, erroneous omissions may occur in the identification data.

(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and is capable of preventing data identification errors for transmitted data, as well as identifying correct data even for data containing noise. The purpose is to provide a data extraction circuit that can extract data.

[Structure of the invention]

(Means for Solving the Problems) In the data extraction circuit according to the present invention, an up-down counter whose up-counting and down-counting are controlled according to the logic level of input data is provided, and an integral value by the up-down counter and a comparator are used. A compare j is provided to perform comparison with a set value. A preset value is applied to the comparator according to the high/low level selected and specified by the selector. The selection and designation of this preset value is controlled according to the comparison result of the comparator. At this time, the comparison result of the comparator is detected by a D flip-flop or the like, and this detection result is used as extracted data.

(Function) The input data is integrated by the up/down counter, and the integrated output is input to the comparator.

The reference value of the KONOTOKI comparator selects and specifies the input of the selector (upper limit value A, lower limit value B) according to the comparison result of the above-mentioned comparator.

The operation of this configuration forms a Schmitt circuit having hysteresis according to the deviation (A-B) of the input (person, B) of the selector, and the Schmitt operation allows data extraction operation with little influence from noise.

(Embodiments) Hereinafter, embodiments of the data extraction circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a data extraction circuit according to the present invention. Transmission data is transmitted using various modulation methods such as FSK, or baseband, and is demodulated as necessary. The data is input to the input terminal IN.

The operation of the data extraction circuit according to the present invention shown in FIG. 1 with respect to data input to the input terminal IN will be described with reference to the waveform diagram of each part shown in FIG.

In FIG. 1, the data to be identified (FIG. 2 (α)) obtained at the input terminal IN is first input to the D flip-flop 10.
In addition to the original data (D), there is noise (N) in the transmitted data shown in Figure 2 (α) above.
It is included. Therefore, it is necessary to prevent the influence of the noise (N) from being performed incorrectly.

The transmission data applied to the D flip-flop 10 is latched at the rising edge of the clock (4) in FIG.
, 0 (Fig. 2 (C), (d)).

At this time, the output 0°0 of the above-mentioned flip-flop 10 is applied to the OR gate 11.12, and the above clock (second
Gate (k)).

The outputs of the OR gates 11 and 12 are applied to the down clock terminal DC and up clock terminal UC of the up/down counter 20, respectively. The load terminal LOAD and the carry-out terminal of this up-down counter 20 are connected to perform up-counting to prevent a carry from exceeding the above-mentioned value.
The configuration is such that R is connected to the clear terminal CL so that there is no underflow. Further, the up/down counter 20 is provided with a preset input terminal 1000~D. By configuring the up/down counter 20 in this way, when the count value reaches "0" after counting down, the count value becomes rOJ because the clear terminal is connected to the BORO 1 terminal.
maintain. On the other hand, the count value is reset to the pre-reset value (r15J in the example shown in Figure 2).
), the carry terminal is connected to the load terminal, so the preset value is reloaded from the preset input terminal and the preset value "15" is maintained.

The up-down counter 20 has a second up-clock terminal UC and a down-clock terminal DC, respectively.
Figure (4), <! A clock indicated by > is applied in response to the above data to the BORO terminal of the up/down counter.

Borrow and carry as shown in Figure 2 (?) and (4) occur at each carry terminal.

Therefore, the count value output from the up/down counter 20 changes as shown in FIG. 2(t) in response to the transmitted data (FIG. 2(α)).

The output of the up/down counter 20 exhibiting such an output change is applied to one input terminal of the comparator 30, the output of the selector 40 is applied to the other input terminal of the comparator 30, and the output of the comparison terminal C of the comparator 30 is applied to the other input terminal of the comparator 30. The state of the D flip-flop 50 is controlled according to the output.

Here, the selector 40 has an upper limit voltage vP and a lower limit voltage VN set, and these voltages! ij! Vp +
Which of VN is input to the comparator 30 is controlled by the output of the D flip-flop 50 which receives the comparison result of the comparator 30 as input. At this time, the D flip-flop 50 recognizes the output of the comparator 30, and the output of the D flip-flop 50 is used as a control signal for the selector 40 and also as recognition data.

That is, the count value of the up/down counter 20 is equal to the upper limit voltage value v specified by the selector 40.
When the comparator 30 detects that the value from the terminal corresponding to P is changed, the output of the comparison terminal C of the comparator 30 becomes "1". At this time, the output of the D flip-flop 50 becomes "1". The output of the selector 40, which is dangerous due to this change, is switched to the lower limit voltage VN. If the clock continues to be applied in this state, the carry terminal of the up-down counter 20 is connected to the load terminal, so as long as a carry occurs, the up-down counter 20 will reach its maximum value until the next down pulse arrives. Maintain the value (preset value). After that, the incoming data falls, and accordingly, the down counter of the up/down counter 2G progresses, and when this count value matches the lower limit voltage VN set in the selector 40, the comparison output terminal C of the comparator 30 outputs changes from "1" to "0". That is, in response to the data between time to-ytet, the comparison output terminal C of the comparator 30 is output from time t1 to 1. It becomes "1" during the period, and changes in response to the data. (FIG. 2(c)) The change in response to the data of the comparator 30 is delayed by half a clock at the output terminal of the D flip-flop 50, and exhibits a change in response to the data from time t10 onward. This D
The output of the flip-flop 50 is used as identification data and is led to the data output terminal OUT (FIG. 2 (1))
.

In such a data extraction circuit, if noise N is mixed in after the arrival of data D as shown in Fig. 2, this noise N will be up-down as shown in Fig. 2 (4). This only has the effect of incrementing the counter 20 by 1, and the data length is only stretched by one clock, so there is little effect on data identification. Therefore, it has a function to block noise after data arrives, and equivalent surface noise removal can be performed to prevent data identification errors due to noise.

Furthermore, even when data is mixed in incoming data, it exhibits a noise integration effect and reduces data identification errors.

〔Effect of the invention〕

As described above, according to the data extraction circuit according to the present invention, it is possible to prevent incorrect identification of incoming data due to noise and to identify correct transmitted data.

Therefore, the data extraction circuit according to the present invention is suitable for data extraction such as FSK data demodulation processing. Furthermore, if the frequency of the clock used for data sampling is set appropriately for the data transmission rate, data identification malfunctions due to noise can be avoided. It can be further reduced.

By appropriately setting the preset values selected by the selector, the isometric hysteresis characteristic can be selected, and the control sensitivity to noise can be appropriately set.

[Brief explanation of the drawing]

FIG. 3 is a circuit diagram showing a conventional data extraction circuit. IN...Data input terminal, OUT...Data output terminal. 10...first latch means. 20...up/down counter. 30...Comparator, 40...Selector. 50...Second latch means. Figure 3

Claims (1)

[Claims] A data input terminal to which data to be extracted is applied; a first latch means for latching the signal of the data input terminal at a predetermined clock and outputting latched data; An up/down counter whose up-counting and down-counting is controlled by an output and counts a predetermined clock; a comparator to which the output of this up-down counter is inputted to one input terminal and a reference value is inputted to the other input terminal; and this comparator. a selector that performs a switching operation to switch the reference value applied to the other input terminal of the input terminal between a first level and a second level, and a comparison result between the comparator and the comparator, which latches this as input data; A data extraction circuit comprising at least second latch means for outputting extracted data to an extracted data output terminal and to the selector to control the selector.