JPH04363029A - Heterojunction field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a heterojunction field-effect transistor wherein various characteristics such as a high-frequency characteristic and the like are improved as compared with those in conventional cases and an element characteristic is stabilized. CONSTITUTION:A semiconductor layer 3, for channel use, which is composed of a compound semiconductor is formed on a semiconductor layer 2 for buffer use on a substrate 1. A semiconductor layer 5, for electron supply layer, which is composed of a compound semiconductor is formed on it. A Schottky junction gate electrode 8, a source electrode 10 and a drain electrode 11 are formed on it. In addition, a semiconductor layer 21 for electron traveling use is formed between the semiconductor layer 2 for buffer use and the semiconductor layer 3 for channel use. The semiconductor layer 21 is composed of a compound whose electron affinity is small as compared with that of the semiconductor layer 3 and large as compared with that of the semiconductor layers 2, 5 and whose electric-field intensity taking the maximum value of an electron velocity is situated in a position different form that of the semiconductor layer 3; it is arranged in such a way that an energy level at the bottom of an electron conduction band is set to nearly the same as a Fermi level.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction field effect transistor.

0002

2. Description of the Related Art Hitherto, various high-speed transistors have been developed, and this heterojunction field effect transistor is one of them. This conventional heterojunction field effect transistor has a configuration as shown in FIG. 9, for example.

In the figure, this transistor uses a semi-insulating semiconductor substrate 1 made of a compound semiconductor such as InP, and on top of this is an n-type semiconductor substrate made of a compound semiconductor such as InAlAs. A buffer semiconductor layer 2 is formed in which neither impurities nor p-type impurities are intentionally introduced, or even if they are introduced, they are introduced only at a sufficiently low concentration. The buffer semiconductor layer 2 is made of a compound semiconductor such as InGaAs, which has a larger electron affinity than the buffer semiconductor layer 2, and is intentionally free of either n-type impurities or p-type impurities. A channel forming semiconductor layer 3 is formed in which no impurities are introduced, or even if they are introduced, the impurities are introduced only at a sufficiently low concentration.

Further, on the channel forming semiconductor layer 3, a semiconductor material having a smaller electron affinity than that of the channel forming semiconductor layer 3, such as I
Composed of compound semiconductors such as nAlAs,
Furthermore, an electron supply semiconductor layer 5 into which n-type impurities are introduced at a high concentration is formed. In this case, the spacer semiconductor layer 4 is made of a compound semiconductor made of, for example, InAlAs, which has a smaller electron affinity than the channel-forming semiconductor layer 3, and is intentionally doped with either an n-type impurity or a p-type impurity. Either they have not been introduced, or even if they have been introduced, they have only been introduced at sufficiently low concentrations.

[0005] Further, on the electron supply semiconductor layer 5, an electrode semiconductor layer 6 is formed, which is made of a compound semiconductor such as InGaAs, and into which n-type impurities are introduced at a high concentration. . In this case, a window 7 is formed in the electrode-attached semiconductor layer 6 so that the electron supply semiconductor layer 5 is exposed to the outside. Further, on the electron supply semiconductor layer 5, in the region facing the window 7 of the electrode-attached semiconductor layer 6,
A gate electrode 8 is arranged to form a Schottky junction 9. Further, on the semiconductor layer 6 for electrode attachment, a source electrode 10 and a drain electrode 11 are ohmically connected to the semiconductor layer 6 for electrode attachment at both left and right positions across the window 7, and therefore at both left and right positions across the gate electrode 8. are placed in contact with each other.

According to the conventional heterojunction field effect transistor having such a structure, electrons are supplied to the channel forming semiconductor layer 3 from the electron supplying semiconductor layer 5 via the spacer semiconductor layer 4. , an electron gas layer 13 is formed on the spacer semiconductor layer 4 side of the channel forming semiconductor layer 3. And gate electrode 8
With reference to the source electrode 10, the depletion layer spreads from the Schottky junction 9 toward the semi-insulating semiconductor substrate 1 side until it reaches the heterojunction between the spacer semiconductor layer 4 and the channel forming semiconductor layer 3 or its vicinity. When a control voltage is applied in addition to a bias voltage, the electron concentration in the channel-forming semiconductor layer 3 due to electrons in the electron gas layer 13 is controlled in accordance with the value of the control voltage.

Therefore, if a required power source with the drain electrode 11 side being positive is connected in advance between the source electrode 10 and the drain electrode 11 through the load, a current corresponding to the control voltage can be applied to the load. can be supplied,
It functions as a field effect transistor.

[0008]

[Problems to be Solved by the Invention] However, in the case of a conventional heterojunction field effect transistor as shown in FIG. Since only one electron gas layer 13 is formed, the average electron concentration in the channel-forming semiconductor layer 3 cannot be made sufficiently high, and the current value that can be supplied to the load cannot be increased. Ta.

Furthermore, in the case of a conventional heterojunction field effect transistor as shown in FIG. The electric field strength varies from the edge of the region below the source electrode 10 to the drain electrode 1.
Although the height increases toward the edge of the region below 1, the height of InG constituting the channel forming semiconductor layer 3 increases.
In the case of a compound semiconductor such as an aAs-based compound semiconductor, the velocity of electrons traveling there exhibits an electric field strength dependence that reaches a maximum at a low electric field strength position, as shown in the characteristics of InGaAs in Figure 3. A relatively high electron velocity can be obtained in the region under the source electrode 10 in the region under the gate electrode 8 of the layer 3, but in the region under the drain electrode 11 in the region under the gate electrode 8 of the channel forming semiconductor layer 3 In the region on the region side, only a relatively low electron velocity is obtained, and the average velocity of electrons traveling through the channel forming semiconductor layer 3 is relatively low. For this reason,
This has the disadvantage that good high frequency characteristics as a field effect transistor cannot be obtained.

Further, in the case of the conventional heterojunction field effect transistor shown in FIG. 9, a slight gap 12 is usually provided between the gate electrode 8 and the semiconductor layer 6 for electrode attachment. This is because the portion of the gate electrode 8 that directly touches the electrode-attached semiconductor layer 6 into which n-type impurities are introduced at a high concentration does not exhibit Schottky characteristics, but exhibits ohmic characteristics. Therefore, gate leakage current flows directly from the gate electrode 8 to the semiconductor layer 6 for forming an electrode, and the semiconductor layer 3 for channel formation
This is to prevent the two-dimensional electron gas 13 inside from becoming uncontrollable. However, the surface potential of this gap 12 is likely to change due to exposure to the atmosphere, chemicals, plasma, etc. during manufacturing of the heterojunction field effect transistor. Also,
Because of this gap 12, the depletion layer below the gate electrode 8 spreads to below the gap 12, reducing the concentration of the two-dimensional electron gas 13 in the channel forming semiconductor layer 3 in the region below the gap 12. Put it away. This increases the source resistance and drain resistance of the heterojunction field effect transistor, and significantly deteriorates the device characteristics. The degree of this reduction varies greatly depending on the manufacturing process of the heterojunction field effect transistor, or even after manufacturing, it has the disadvantage that it becomes a factor that significantly deteriorates the stability of device characteristics.

Further, the conventional heterojunction field effect transistor shown in FIG. 9 needs to have a threshold voltage Vth determined by the circuit type in which the heterojunction field effect transistor is used. At this time, when a threshold voltage is applied to the gate electrode 8 with respect to the source electrode 10, the electric field strength Es at the Schottky junction 9 becomes Es=2(Vbi-Vth)/d. Here, d is the thickness of the electron supplying semiconductor layer 5, and Vbi is the internal voltage existing in the electron supplying semiconductor layer 5, the spacer semiconductor layer 4, and the channel forming semiconductor layer 3. In order to ensure the withstand voltage of the gate electrode, it is necessary to lower Es to a certain value or less that can be determined by the semiconductor material, but as can be seen from the above equation, if Vth is fixed, Es is determined only by d, d cannot be made small. however,
The transfer conductance gm of the transistor is gm=ε
It is given by vs/d (vs is the electron velocity), and it becomes impossible to increase the transfer conductance. For this reason, it has a drawback that it is difficult to improve the characteristics of the transistor while ensuring the gate breakdown voltage.

[0012] Therefore, an object of the present invention is to provide a heterojunction field effect transistor which has improved high frequency characteristics compared to the conventional one, whose device characteristics are more stable than the conventional one, and whose characteristics are improved while ensuring gate breakdown voltage. There is a particular thing.

[0013]

[Means for Solving the Problems] In order to achieve such an object, a channel forming semiconductor layer made of a compound semiconductor is formed on a buffer semiconductor layer on a substrate, and a channel forming semiconductor layer made of a compound semiconductor is formed on a buffer semiconductor layer on a substrate. In a heterojunction field effect transistor comprising an electron supplying semiconductor layer made of a formed compound semiconductor, and a Schottky junction gate electrode, a source electrode, and a drain electrode formed on this electron supplying semiconductor layer, It is smaller than the semiconductor layer and has a larger electron affinity than the spacer semiconductor layer, electron supply semiconductor layer, and buffer semiconductor layer, and the channel formation semiconductor layer has an electric field strength that takes the maximum electron velocity. The semiconductor layer for electron transport, which is composed of compound semiconductors in different positions and arranged so that the energy level at the bottom of the electron conduction band of this layer is about the same as the Fermi level, is connected to the semiconductor layer for buffer and the channel. It is formed between semiconductor layers for formation.

Furthermore, a second spacer semiconductor layer is formed between the electron travel semiconductor layer and the channel forming semiconductor layer. Furthermore, in addition to the electron transit semiconductor layer between the buffer semiconductor layer and the channel forming semiconductor layer, a third spacer semiconductor layer and a second spacer semiconductor layer are provided between the buffer semiconductor layer and the electron transit semiconductor layer. A semiconductor layer for supplying electrons is formed.

[0015]

[Function] By forming the electron transport semiconductor layer on the channel forming semiconductor layer, an electron gas layer different from the conventional one is formed in the channel forming semiconductor layer, and the current that can be supplied to the load is significantly increased. At the same time, good high frequency characteristics can be obtained. Furthermore, by forming the second spacer semiconductor layer, electrons in the channel forming semiconductor layer can effectively avoid Coulomb scattering from high concentration impurities in the electron transport semiconductor layer, increasing the electron velocity. This improves high frequency characteristics. Further, similar effects can be obtained by forming the third spacer semiconductor layer and the second electron supply semiconductor layer.

[0016]

【Example】

"Embodiment 1" FIG. 1 shows a first embodiment (first invention) of a heterojunction field effect transistor according to the present invention.
The semi-insulating semiconductor substrate 1 is made of a compound semiconductor such as InAlAs, and neither n-type impurities nor p-type impurities are intentionally introduced. Even if the buffer semiconductor layer 2 is doped, the buffer semiconductor layer 2 is doped only at a sufficiently low concentration. The buffer semiconductor layer 2 is made of a compound semiconductor such as InGaAs, which has a larger electron affinity than the buffer semiconductor layer 2, and is intentionally free of either n-type impurities or p-type impurities. The channel forming semiconductor layer 3, which is not introduced or is introduced only at a sufficiently low concentration, is formed through the electron transport semiconductor layer 21, which is characterized by the present invention and will be described in detail later. has been done.

Further, on the channel forming semiconductor layer 3, a material having a smaller electron affinity than that of the channel forming semiconductor layer 3, such as I
Composed of compound semiconductors such as nAlAs,
Furthermore, an electron supply semiconductor layer 5 into which n-type impurities are introduced at a high concentration is formed. In this case, the spacer semiconductor layer 4 is made of a compound semiconductor made of, for example, InAlAs, which has a smaller electron affinity than the channel-forming semiconductor layer 3, and is intentionally doped with either an n-type impurity or a p-type impurity. Either they have not been introduced, or even if they have been introduced, they have only been introduced at sufficiently low concentrations.

Further, on the electron supply semiconductor layer 5, an electrode semiconductor layer 6 is formed, which is made of a compound semiconductor such as InGaAs, and into which n-type impurities are introduced at a high concentration. . In this case, a window 7 is formed in the electrode-attached semiconductor layer 6 so that the electron supply semiconductor layer 5 is exposed to the outside. Further, on the electron supply semiconductor layer 5, in the region facing the window 7 of the electrode-attached semiconductor layer 6,
A gate electrode 8 is arranged to form a Schottky junction 9. Further, on the semiconductor layer 6 for electrode attachment, a source electrode 10 and a drain electrode 11 are ohmically connected to the semiconductor layer 6 for electrode attachment at both left and right positions across the window 7, and therefore at both left and right positions across the gate electrode 8. are placed in contact with each other.

The electron transport semiconductor layer 21 characterized by the present invention is formed between the buffer semiconductor layer 2 and the channel forming semiconductor layer 3. This semiconductor layer 21 for electron travel is smaller than the semiconductor layer 3 for channel formation and has a larger electron affinity than the semiconductor layer 4 for spacer, the semiconductor layer 5 for electrode attachment, and the semiconductor layer 2 for buffer, and forms a channel. For example, I
It is made of a compound semiconductor such as nP, and is doped with n-type impurities at a high concentration. The above is the configuration of the first embodiment of the heterojunction field effect transistor according to the present invention.

According to the heterojunction field effect transistor according to the present invention, as shown by line a in FIG.
Since the two-dimensional electron gas 13 is formed on the side of the electron supplying semiconductor layer 5 of the channel forming semiconductor layer 3 and has the electron traveling semiconductor layer 21, the electron traveling semiconductor layer 21 of the channel forming semiconductor layer 3 is provided with the electron traveling semiconductor layer 21. There is also an electronic gas layer 13 on the side.
' are formed, and the electron gas layers 13 and 1
The electron concentration at 3' is controlled according to the control voltage applied to the gate electrode 8. In this case, as in the case of the conventional heterojunction field effect transistor shown in FIG. 9, a current corresponding to the control voltage applied to the gate electrode 8 can be supplied to the load.

As described above, in the case of the heterojunction field effect transistor according to the present invention shown in FIG. 1, as shown by line a in FIG. As a result, the electron supply semiconductor layer 5 of the channel formation semiconductor layer 3
In addition to forming the electron gas 13 on the side of the semiconductor layer 3 for forming a channel, the semiconductor layer 21 for electron travel is formed adjacently to the lower side of the semiconductor layer 3 for forming a channel.
Another electron gas 13' is formed on the electron traveling semiconductor layer 21 side. Therefore, the channel forming semiconductor layer 3 has a high average electron concentration that is twice or nearly twice that of the conventional heterojunction field effect transistor described above with reference to FIG. As a result, the semiconductor layer 21 for electron travel is
It also acts as an electron supply layer, and the current value that can be supplied to the load can be made much larger than in the case of the conventional heterojunction field effect transistor shown in FIG.

Furthermore, in the case of the heterojunction field effect transistor shown in FIG.
Similarly to the conventional heterojunction field effect transistor shown in FIG. 9, the speed of electrons traveling therein is dependent on the electric field strength of the compound semiconductors constituting the transistors. As shown in FIG. 3, the electric field dependence is such that the electron velocity changes with the compound semiconductor (In0.53Ga0.4
7As) and the compound semiconductor (InP in FIG. 1) constituting the electron transport semiconductor layer 21 exhibit maximum values at different electric field strength positions.

Therefore, the channel forming semiconductor layer 3
And in the semiconductor layer 21 for electron travel, the gate electrode 8
In the region where the electric field strength is low on the source electrode 10 side in the lower region, electrons travel at high speed in the channel forming semiconductor layer 3 and the gate electrode in the channel forming semiconductor layer 3 and the electron traveling semiconductor layer 21. In the region below 8 where the electric field strength is strong on the drain electrode 11 side, the kinetic energy of electrons is large, and the potential energy of the electron conduction band of the electron traveling semiconductor layer 21 is as shown by line b in FIG. The concentration is lowered by the high concentration of n-type impurities and is close to the Fermi level (see FIG. 2), so the probability of existence of electrons in the electron transit semiconductor layer 21 increases, and the electrons are removed from the channel forming semiconductor layer 3. Electron movement becomes easier. Therefore, the average electron velocity in the region below the gate electrode 8 can be made higher than in the case of the conventional heterojunction field effect transistor shown in FIG. Therefore, it is possible to obtain better high frequency characteristics as a field effect transistor than in the case of the conventional heterojunction field effect transistor shown in FIG.

Further, in the heterojunction field effect transistor according to the present invention, when a threshold voltage is applied to the gate electrode 8 with respect to the source electrode 10, the Schottky junction 9
The electric field strength Es at is Es=2(Vbi-Vt
h)/d−N1(d12+d0+d)/(2dε). Here, N1 is the n-type impurity concentration of the electron transit semiconductor layer 21, d1 is the thickness of the electron transit semiconductor layer 21, d is the thickness of the electron supply semiconductor layer 5, and d0 is the thickness of the channel forming semiconductor layer 3. The thickness and Vbi are internal voltages existing in the electron supply semiconductor layer 5, the spacer semiconductor layer 4, and the channel formation semiconductor layer 3. As can be seen from this equation, the electric field strength of the Schottky junction 9 is lower than that of the conventional heterojunction field effect transistor shown in FIG. This increases compared to transistors. Furthermore, compared to the conventional heterojunction field effect transistor shown in FIG. 9, d can be made smaller without lowering the gate breakdown voltage, and the transfer conductance can be increased. For this reason,
The heterojunction field effect transistor according to the present invention has a larger design margin than the conventional heterojunction field effect transistor shown in FIG. 9, and can improve device characteristics.

``Embodiment 2'' Next, a second embodiment of the heterojunction field effect transistor according to the present invention will be described with reference to FIG. Note that in FIG. 4, parts corresponding to those in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. The heterojunction field effect transistor according to the present invention shown in FIG. 4 has the same structure as the heterojunction field effect transistor of the first embodiment described using FIG. 1, except for the following points. That is, the Schottky forming semiconductor layer 24 is placed between the electron supply semiconductor layer 5 and the electrode attachment semiconductor layer 6.
, an ohmic resistance reducing semiconductor layer 25 is formed. In this case, the Schottky forming semiconductor layer 24 is formed on the electron supplying semiconductor layer 5 side.

The Schottky forming semiconductor layer 24 is made of, for example, an InAlAs-based compound semiconductor having a smaller electron affinity than the channel forming semiconductor layer 3, and is intentionally doped with either an n-type impurity or a p-type impurity. It has the same structure as the spacer semiconductor layer 4 in which it is not introduced, or even if it is introduced, it is only introduced at a sufficiently low concentration. In this case, the Schottky forming semiconductor layer 2
4 has a thickness less than or equal to the diffusion length of electrons therein. The ohmic resistance reducing semiconductor layer 25 is made of, for example, InAlAs, which is the same as the Schottky forming semiconductor layer 24 and has a smaller electron affinity than the channel forming semiconductor layer 3.
This structure is made of a compound semiconductor based on a compound semiconductor and has a high concentration of n-type impurities introduced therein. The ohmic resistance reducing semiconductor layer 25 also includes a window (hereinafter, a window between the window and the electrode-attached semiconductor layer 6) that communicates with the window 7 of the electrode-attached semiconductor layer 6 and exposes the Schottky-forming semiconductor layer 24 to the outside. window 7
A gate electrode 8 (referred to as a window 7) is formed through the Schottky forming semiconductor layer 24 to form a Schottky junction 9 instead of being attached to the electron supplying semiconductor layer 5 of FIG. It is attached to.

The above is the structure of the second embodiment of the heterojunction field effect transistor according to the present invention. According to the second embodiment of the heterojunction field effect transistor according to the present invention having such a configuration, the structure is similar to that of the heterojunction field effect transistor according to the present invention described above with reference to FIG. 1, except for the above-mentioned matters. Therefore, the same functions and effects as the heterojunction field effect transistor according to the present invention described above with reference to FIG. Schottky forming semiconductor layer 24 formed on Schottky forming semiconductor layer 5 and in which neither n-type impurity nor p-type impurity is intentionally introduced, or even if introduced, it is only introduced at a sufficiently low concentration. Therefore, the Schottky junction 9 is formed better than in the case of the heterojunction field effect transistor shown in FIG. Therefore, better characteristics can be obtained than in the case of the heterojunction field effect transistor shown in FIG.

Embodiment 3 Next, a third embodiment (second invention) of the heterojunction field effect transistor according to the present invention will be described with reference to FIG. Note that in FIG. 5, parts corresponding to those in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. The heterojunction field effect transistor according to the present invention shown in FIG. 5 has the same structure as the heterojunction field effect transistor of the first embodiment shown in FIG. 1, except for the following points. In this embodiment, the semiconductor layer 2 for electron travel is
1 and the channel forming semiconductor layer 3, a second spacer semiconductor layer 34 is formed. The second spacer semiconductor layer 34 is a compound semiconductor that is smaller than the channel forming semiconductor layer 3 and has a larger electron affinity than the spacer semiconductor layer 4, the electron supply semiconductor layer 5, and the buffer semiconductor layer 2. Moreover, neither n-type impurities nor p-type impurities are intentionally introduced, or even if they are introduced, they are introduced only at sufficiently low concentrations.

The above is the structure of the third embodiment of the heterojunction field effect transistor according to the present invention. According to a heterojunction field effect transistor with such a configuration,
Except for the above-mentioned matters, it has the same structure as the heterojunction field effect transistor according to the present invention described above in FIG. Since the semiconductor layer 34 is provided, the electrons in the channel forming semiconductor layer 3 can effectively avoid Coulomb scattering from the high concentration n-type impurity in the electron traveling semiconductor layer 21, and therefore the channel forming semiconductor layer 3 The electron velocity within the transistor increases, and the high frequency characteristics can be improved more than in the case of the heterojunction field effect transistor of the first embodiment shown in FIG.

``Embodiment 4'' Next, a fourth embodiment of the heterojunction field effect transistor according to the present invention will be described with reference to FIG. Note that in FIG. 6, parts corresponding to those in FIG. 4 are given the same reference numerals, and detailed description thereof will be omitted. The heterojunction field effect transistor shown in FIG. 6 has the same configuration as the second embodiment shown in FIG. 4 except for the following points. That is, as in the case of the heterojunction field effect transistor according to the present invention described above with reference to FIG.
A second spacer semiconductor layer 34 is formed. The second spacer semiconductor layer 34 is a compound semiconductor that is smaller than the channel forming semiconductor layer 3 and has a larger electron affinity than the spacer semiconductor layer 4, the electron supply semiconductor layer 5, and the buffer semiconductor layer 2. Moreover, neither n-type impurities nor p-type impurities are intentionally introduced, or even if they are introduced, they are introduced only at sufficiently low concentrations.

The above is the configuration of the fourth embodiment of the heterojunction field effect transistor according to the present invention. The heterojunction field effect transistor according to the present invention having such a configuration has the same configuration as the heterojunction field effect transistor according to the present invention described above with reference to FIG. 4, except for the matters described above. The same effect as in the example of
This effect is obtained, and since the spacer semiconductor layer 34 is provided, the channel forming semiconductor layer 3 can be used similarly to the heterojunction field effect transistor described in connection with FIG.
Coulomb scattering from the high concentration n-type impurity in the electron transport semiconductor layer 21 is effectively avoided, and therefore,
The electron velocity within the channel-forming semiconductor layer 3 increases, and the high frequency characteristics can be improved more than in the case of the heterojunction field effect transistor of the second embodiment shown in FIG.

``Embodiment 5'' Next, a fifth embodiment (third invention) of the heterojunction field effect transistor according to the present invention will be described with reference to FIG. Note that in FIG. 7, parts corresponding to those in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. Further, the heterojunction field effect transistor according to the present invention shown in FIG. 7 has the same configuration as the heterojunction field effect transistor according to the invention shown in FIG. 1, except for the following points. In FIG. 7, the buffer semiconductor layer 2 and the channel forming semiconductor layer 3 are used instead of the electron transit semiconductor layer 21 having a high concentration of n-type impurity in the heterojunction field effect transistor of FIG. The following three layers are formed in between.

That is, one of these three layers is the electron transit semiconductor layer 21, which is smaller than the channel forming semiconductor layer 3 and is smaller than the spacer semiconductor layer 4 and the electron transit semiconductor layer 21. The channel forming semiconductor layer 3 has a larger electron affinity than the supply semiconductor layer 5.
The semiconductor layer 21 is made of a compound semiconductor, such as InP, in which the electric field strength at which the electron velocity reaches its maximum value is at a different position, and the electron traveling semiconductor layer 21 contains neither n-type impurities nor p-type impurities intentionally. has not been introduced into
Even if it is introduced, it is only introduced at a sufficiently low concentration. The remaining one of the three layers is a third spacer semiconductor layer 41, which is located below the electron transit semiconductor layer 21 and is smaller than the electron transit semiconductor layer 21. Compound semiconductors with electron affinity, such as InAlA
The semiconductor layer 41 is composed of s-based material, and furthermore, this semiconductor layer 41 has
Neither n-type impurities nor p-type impurities are intentionally introduced, or even if they are introduced, they are only introduced at sufficiently low concentrations. Moreover, the last one of the three layers is the second electron supply semiconductor layer 51. This semiconductor layer 51 is located under the third spacer semiconductor layer 4, and is made of a compound semiconductor having a smaller electron affinity than the electron transport semiconductor layer 21, such as InAlAs, and has a high concentration of n-type impurities. has been introduced.

The above is the configuration of the fifth embodiment of the heterojunction field effect transistor according to the present invention. According to the heterojunction field effect transistor having such a configuration, as shown in FIG.
Therefore, a two-dimensional electron gas 13' is formed in the electron transport semiconductor layer 21 for the same reason that the two-dimensional electron gas 13 is formed in the channel-forming semiconductor layer 3. Except for the above-mentioned matters, the structure is similar to that of the heterojunction field effect transistor of the embodiment shown in FIG. 1, so that the same functions and effects as the heterojunction field effect transistor of the embodiment shown in FIG. 1 can be obtained. Further, also in the heterojunction field effect transistor having the configuration shown in FIG. 7, the second electron supply semiconductor layer 5
1 has a high concentration of n-type impurities, the potential energy of the electron conduction band of the electron transport semiconductor layer 21 decreases, and the probability that electrons exist in the electron transport semiconductor layer 21 increases, as shown in FIG. Similar effects can be obtained for the same reason as the heterojunction field effect transistor of the first embodiment.

It should be noted that the present invention is not limited to the above-described embodiments, and the spacer semiconductor layer 4 may be omitted from the structure of the above-described embodiments. Also, in FIGS. 4 and 6, Semiconductor layer 25 for reducing ohmic resistance
It is also possible to adopt a structure in which the ohmic resistance reduction semiconductor layer or a Schottky formation semiconductor layer is introduced in the embodiment of FIG. 7. Further, in FIG. 1, a structure may be adopted in which the spacer semiconductor layer 4 is removed. In addition, various modifications and changes may be made without departing from the spirit of the invention.

[0036]

[Effects of the Invention] As described above, according to the heterojunction field effect transistor according to the present invention, by forming the electron transport semiconductor layer on the channel forming semiconductor layer, the channel forming semiconductor layer is different from the conventional one. An electron gas layer is formed, and the current that can be supplied to the load becomes significantly larger, and good high frequency characteristics can be obtained. Furthermore, by forming the second spacer semiconductor layer, electrons in the channel forming semiconductor layer can effectively avoid Coulomb scattering from high concentration impurities in the electron transport semiconductor layer, increasing the electron velocity. This improves high frequency characteristics. Further, by forming the third spacer semiconductor layer and the second electron supply semiconductor layer, the same effects as described above can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment (first invention) of a heterojunction field effect transistor according to the present invention.

FIG. 2 is a band structure diagram for explaining FIG. 1;

FIG. 3 is a diagram showing the relationship between the electron velocity (x10 cm/s) and the electric field strength (kV/cm) in the channel forming semiconductor layer and the electron transport semiconductor layer in FIG. 1;

FIG. 4 is a schematic cross-sectional view showing a second embodiment of a heterojunction field effect transistor according to the present invention.

FIG. 5 is a schematic cross-sectional view showing a third embodiment (second invention) of a heterojunction field effect transistor according to the present invention.

FIG. 6 is a schematic cross-sectional view showing a fourth embodiment of a heterojunction field effect transistor according to the present invention.

FIG. 7 is a schematic cross-sectional view showing a fifth embodiment (third invention) of a heterojunction field effect transistor according to the present invention.

8 is a band structure diagram for explaining FIG. 7; FIG.

FIG. 9 is a schematic cross-sectional view showing a conventional heterojunction field effect transistor.

[Explanation of symbols]

1 Semi-insulating semiconductor substrate 2 Semiconductor layer for buffer 3 Semiconductor layer for channel formation 4 Semiconductor layer for spacer 5 Semiconductor layer for electron supply 6 Semiconductor layer for electrode attachment 7 Window 8 Gate electrode 9 Schottky junction 10 Source electrode 11 Drain electrode 21 Semiconductor layer for electron transport 34 Second spacer semiconductor layer 41 Third spacer semiconductor layer 51 Second electron supply semiconductor layer

Claims (3)

[Claims] Claim 1: Formed on a semi-insulating semiconductor substrate, made of a compound semiconductor, and either n-type impurity or p-type impurity is not intentionally introduced, or even if it is introduced, the concentration is sufficiently low. A buffer semiconductor layer is formed on the buffer semiconductor layer and is made of a compound semiconductor having a larger electron affinity than the buffer semiconductor layer, and is doped with n-type impurities or p-type impurities. A channel-forming semiconductor layer in which no impurities are intentionally introduced or, even if impurities are introduced, only at a sufficiently low concentration, and a channel-forming semiconductor layer having a smaller electron affinity compared to the above-mentioned channel-forming semiconductor layer. With or without a spacer semiconductor layer made of a compound semiconductor and in which neither n-type impurities nor p-type impurities are intentionally introduced, or if introduced, only at a sufficiently low concentration. an electron-supplying semiconductor layer which is formed of a compound semiconductor having a smaller electron affinity than the channel-forming semiconductor layer and into which an n-type impurity is introduced at a high concentration, and the electron-supplying semiconductor layer. It is made of a compound semiconductor having a smaller electron affinity than the channel forming semiconductor layer formed above or on the electron supplying semiconductor layer, and in which either an n-type impurity or a p-type impurity is intentionally introduced. In the semiconductor layer for Schottky formation, which has not been introduced or has been introduced only at a sufficiently low concentration,
A heterojunction type having a gate electrode attached to form a Schottky junction, and a source electrode and a drain electrode electrically connected to the channel forming semiconductor layer at both positions sandwiching the gate electrode. In the field effect transistor, the spacer semiconductor layer and the electron supply semiconductor layer are formed between the buffer semiconductor layer and the channel formation semiconductor layer, and are smaller than the channel formation semiconductor layer. and is composed of a compound semiconductor that has a larger electron affinity than the buffer semiconductor layer and has a different electric field strength position at which the electron velocity reaches its maximum value than the channel forming semiconductor layer, and A heterojunction field effect transistor characterized by having an electron transit semiconductor layer arranged such that the energy level at the bottom of the electron conduction band is approximately the same as the Fermi level. 2. Formed on a semi-insulating semiconductor substrate, made of a compound semiconductor, and either n-type impurity or p-type impurity is not intentionally introduced, or even if it is introduced, the concentration is sufficiently low. A buffer semiconductor layer is formed on the buffer semiconductor layer and is made of a compound semiconductor having a larger electron affinity than the buffer semiconductor layer, and is doped with n-type impurities or p-type impurities. A channel-forming semiconductor layer in which no impurities are intentionally introduced or, even if impurities are introduced, only at a sufficiently low concentration, and a channel-forming semiconductor layer having a smaller electron affinity compared to the above-mentioned channel-forming semiconductor layer. With or without a spacer semiconductor layer made of a compound semiconductor and in which neither n-type impurities nor p-type impurities are intentionally introduced, or if introduced, only at a sufficiently low concentration. an electron-supplying semiconductor layer which is formed of a compound semiconductor having a smaller electron affinity than the channel-forming semiconductor layer and into which an n-type impurity is introduced at a high concentration, and the electron-supplying semiconductor layer. It is made of a compound semiconductor having a smaller electron affinity than the channel forming semiconductor layer formed above or on the electron supplying semiconductor layer, and in which either an n-type impurity or a p-type impurity is intentionally introduced. In the semiconductor layer for Schottky formation, which has not been introduced or has been introduced only at a sufficiently low concentration,
A heterojunction type having a gate electrode attached to form a Schottky junction, and a source electrode and a drain electrode electrically connected to the channel forming semiconductor layer at both positions sandwiching the gate electrode. In the field effect transistor, the spacer semiconductor layer is formed between the buffer semiconductor layer and the channel formation semiconductor layer, and is smaller than the channel formation semiconductor layer, and the spacer semiconductor layer and the electron supply semiconductor layer are formed between the buffer semiconductor layer and the channel formation semiconductor layer. The semiconductor layer is made of a compound semiconductor having a larger electron affinity than the buffer semiconductor layer, and neither n-type impurities nor p-type impurities are intentionally introduced, or even if they are introduced, only at a sufficiently low concentration. The second semiconductor layer for spacer, which is not introduced, is formed on the side of the semiconductor layer for channel formation, with or without intervening, and is smaller than the semiconductor layer for channel formation, and the semiconductor layer for spacer, The compound semiconductor layer is made of a compound semiconductor that has a larger electron affinity than the electron supply semiconductor layer and the buffer semiconductor layer, and has a different electric field intensity position at which the electron velocity reaches a maximum value than the channel formation semiconductor layer. 1. A heterojunction field effect transistor comprising: a semiconductor layer for electron transport into which n-type impurities are introduced at a high concentration; 3. Formed on a semi-insulating semiconductor substrate, made of a compound semiconductor, and containing neither n-type impurities nor p-type impurities intentionally introduced, or even if introduced, at a sufficiently low concentration. A buffer semiconductor layer is formed on the buffer semiconductor layer and is made of a compound semiconductor having a larger electron affinity than the buffer semiconductor layer, and is doped with n-type impurities or p-type impurities. A channel-forming semiconductor layer in which no impurities are intentionally introduced or, even if impurities are introduced, only at a sufficiently low concentration, and a channel-forming semiconductor layer having a smaller electron affinity compared to the above-mentioned channel-forming semiconductor layer. With or without a spacer semiconductor layer made of a compound semiconductor and in which neither n-type impurities nor p-type impurities are intentionally introduced, or if introduced, only at a sufficiently low concentration. an electron-supplying semiconductor layer which is formed of a compound semiconductor having a smaller electron affinity than the channel-forming semiconductor layer and into which an n-type impurity is introduced at a high concentration, and the electron-supplying semiconductor layer. It is made of a compound semiconductor having a smaller electron affinity than the channel forming semiconductor layer formed above or on the electron supplying semiconductor layer, and in which either an n-type impurity or a p-type impurity is intentionally introduced. In the semiconductor layer for Schottky formation, which has not been introduced or has been introduced only at a sufficiently low concentration,
A heterojunction type having a gate electrode attached to form a Schottky junction, and a source electrode and a drain electrode electrically connected to the channel forming semiconductor layer at both positions sandwiching the gate electrode. In the field effect transistor, the spacer semiconductor layer is formed between the buffer semiconductor layer and the channel formation semiconductor layer, and is smaller than the channel formation semiconductor layer, and the spacer semiconductor layer and the electron supply semiconductor layer are formed between the buffer semiconductor layer and the channel formation semiconductor layer. It is composed of a compound semiconductor that has a larger electron affinity than the semiconductor layer and the buffer semiconductor layer, and has a different position of electric field strength at which the electron velocity reaches its maximum value than the channel-forming semiconductor layer, and type impurity or p
The electron transport semiconductor layer has an electron transport semiconductor layer in which none of the type impurities are intentionally introduced or is introduced only at a sufficiently low concentration, and the electron transport semiconductor layer and the buffer semiconductor layer are combined. In addition to being formed between the semiconductor layer for electron transport, the semiconductor layer is made of a compound semiconductor having a smaller electron affinity than the semiconductor layer for electron transport, and neither n-type impurities nor p-type impurities are intentionally introduced. The compound semiconductor is formed with or without a third spacer semiconductor layer introduced only at a sufficiently low concentration even if and a second electron supply semiconductor layer into which n-type impurities are introduced at a high concentration.