CN116845109A - Electrostatic doped tunneling field effect transistor - Google Patents
Electrostatic doped tunneling field effect transistor Download PDFInfo
- Publication number
- CN116845109A CN116845109A CN202310799220.4A CN202310799220A CN116845109A CN 116845109 A CN116845109 A CN 116845109A CN 202310799220 A CN202310799220 A CN 202310799220A CN 116845109 A CN116845109 A CN 116845109A
- Authority
- CN
- China
- Prior art keywords
- region
- doped
- oxide layer
- gate oxide
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005641 tunneling Effects 0.000 title claims abstract description 37
- 230000005669 field effect Effects 0.000 title claims abstract description 31
- 230000005686 electrostatic field Effects 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 6
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000007769 metal material Substances 0.000 abstract description 3
- 238000005036 potential barrier Methods 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides an electrostatic field doped tunneling field effect transistor, which is characterized in that different metal materials are deposited on oxide layers on a source region and a drain region to form a bias electrode, a certain bias voltage is applied, a large number of electrons or holes are induced in the source region and the drain region by utilizing an electrode bias principle, N-type or P-type doping is formed, and the on-off of a device channel is controlled by utilizing a double-gate structure. In the on state, a very narrow N is formed between the source region and the channel region of the device + In the pocket region, the tunneling barrier width is reduced and the on-current is increased. A P-type gap is formed between the drain region and the channel region of the device in the off state, and the potential barrier width near the drain region can be adjusted by changing the length of the gap, so that the purpose of reducing bipolar current is achieved.
Description
Technical Field
The invention belongs to the technical field of nanoelectronics, and relates to an electrostatic field doped tunneling field effect transistor.
Background
As the size of MOSFETs continues to decrease, power consumption issues become an important factor in limiting the size of MOSFETs. Based on semiconductor physics knowledge, the minimum value of the subthreshold slope (Subthreshold Swing, SS) of the MOSFET is 60mV/dec. One of the most effective solutions to reduce power consumption of integrated circuits is to reduce the supply voltage. However, the minimum subthreshold slope determines that as the supply voltage drops, the difference between the on current and the off current also decreases. When the transistor is in the on state, the current value is not too small, so the on current cannot be reduced as much as possible, which means that as the power supply voltage decreases, the off current of the device is correspondingly increased, which greatly increases the static power consumption of the circuit. To address this problem, tunneling field effect transistors (Tunnel Field Effect Transistor, TFETs) are widely used.
The TFET breaks the constraint of the subthreshold slope of conventional MOSFETs, and the off current can still be kept at a low level when the supply voltage is reduced. It has some drawbacks, the most important of which is that the on-current is greatly reduced compared to MOSFETs, since carriers tunnel between energy bands by means of tunneling effects. In addition, taking an N-type TFET as an example, when a negative gate voltage is applied, the barrier width between the drain region and the channel region is small, and tunneling can also occur, so that bipolar current is formed. Therefore, how to increase the on-current of a TFET device while reducing its bipolar current is a problem to be solved.
Disclosure of Invention
The invention aims to solve the problem that the bipolar current of a tunneling field effect transistor device is reduced while the on-current of the tunneling field effect transistor device is improved in the prior art, and provides an electrostatic field doped tunneling field effect transistor.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
an electrostatic field doped tunneling field effect transistor comprises a P-type heavy doped source region, an N-type heavy doped pocket region, a P-type light doped channel region and an N-type heavy doped drain region which are transversely and sequentially arranged;
the top and the bottom of the P-type heavily doped source region are respectively a top first polarity gate oxide layer and a bottom first polarity gate oxide layer, a top first polarity gate electrode is arranged above the top first polarity gate oxide layer, a bottom first polarity gate electrode is arranged below the bottom first polarity gate oxide layer, and a source electrode contact region is arranged on the side face of the P-type heavily doped source region;
a top control gate oxide layer and a bottom control gate oxide layer are respectively arranged above and below the P-type lightly doped channel region, a top control gate electrode is arranged above the top control gate oxide layer, and a bottom control gate electrode is arranged below the bottom control gate oxide layer;
the top and the bottom of the N-type heavily doped drain region are respectively a top second polarity gate oxide layer and a bottom second polarity gate oxide layer, the top of the top second polarity gate oxide layer is a top second polarity gate electrode, the bottom of the bottom second polarity gate oxide layer is a bottom second polarity gate electrode, and a drain electrode contact region is arranged on the side face of the N-type heavily doped drain region.
The invention further improves that:
the top first polarity gate oxide layer and the bottom first polarity gate oxide layer have the same thickness and are made of the same material.
The top and bottom second polarity gate oxides have the same thickness and are made of the same material.
The top first polarity gate electrode and the bottom first polarity gate electrode have the same work function, and the top second polarity gate electrode and the bottom second polarity gate electrode have the same work function.
The doping concentration of the N-type heavily doped pocket region is 4 multiplied by 10 19 cm -3 The length is 1 nm-9 nm.
The doping concentration of the P-type lightly doped channel region is 1 multiplied by 10 17 cm -3 。
The upper part and the lower part of the N-type heavily doped pocket region are respectively a source region-channel region top side wall and a source region-channel region bottom side wall; and a drain region-channel region top side wall is arranged on one side, close to the N-type heavily doped drain region, of the upper side of the P-type lightly doped channel region, and a drain region-channel region bottom side wall is arranged on one side, close to the N-type heavily doped drain region, of the lower side of the P-type lightly doped channel region.
The length of the side wall at the top of the drain region-channel region is 5 nm-30 nm; the length of the bottom side wall of the drain region-channel region is 5 nm-30 nm.
The source electrode contact region and the drain electrode contact region are both composed of nickel silicide, and the Schottky barrier height is 0.45eV.
The field effect transistor is in a symmetrical structure along a central axis in the horizontal direction and in two parts above and below the central axis.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides an electrostatic field doped tunneling field effect transistor, which is characterized in that different metal materials are deposited on oxide layers on a source region and a drain region to form a bias electrode, a certain bias voltage is applied, a large number of electrons or holes are induced in the source region and the drain region by utilizing an electrode bias principle, N-type or P-type doping is formed, and the on-off of a device channel is controlled by utilizing a double-gate structure. In the on state, a very narrow N is formed between the source region and the channel region of the device + In the pocket region, the tunneling barrier width is reduced and the on-current is increased. A P-type gap is formed between the drain region and the channel region of the device in the off state, and the potential barrier width near the drain region can be adjusted by changing the length of the gap, so that the purpose of reducing bipolar current is achieved.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the final structure of an ESD doped tunneling field effect transistor according to the present invention;
fig. 2 is a schematic diagram of an initial structure of an esd-doped tunnel fet according to the present invention.
Wherein: the semiconductor device comprises a 1-P type lightly doped channel region, a 2-N type heavily doped pocket region, a 3 a-top control gate oxide layer, a 3 b-bottom control gate oxide layer, a 3 c-top first polarity gate oxide layer, a 3 d-bottom first polarity gate oxide layer, a 3 e-top second polarity gate oxide layer, a 3 f-bottom second polarity gate oxide layer, a 4 a-top control gate electrode, a 4 b-bottom control gate electrode, a 5 a-top first polarity gate electrode, a 5 b-bottom first polarity gate electrode, a 6 a-top second polarity gate electrode, a 6 b-bottom second polarity gate electrode, a 7-P type heavily doped source region, an 8-N type heavily doped drain region, a 9 a-source electrode contact region, a 9 b-drain electrode contact region, a 10 a-source region-channel region top side wall, a 10 b-source region-channel region bottom side wall, a 11 a-drain region top side wall, a 11 b-drain region bottom side wall, a 12-P type lightly doped channel region and a 13-N type heavily doped source region.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the embodiments of the present invention, it should be noted that, if the terms "upper," "lower," "horizontal," "inner," and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and does not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Furthermore, the term "horizontal" if present does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. As "horizontal" merely means that its direction is more horizontal than "vertical", and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The invention provides an electrostatic doping tunneling field effect transistor based on a polar bias principle, which is characterized in that different metal materials are deposited on oxide layers on a source region and a drain region to form a bias electrode, a certain bias voltage is applied, a large number of electrons or holes are induced on the source region and the drain region by utilizing the electrode bias principle, N-type or P-type doping is formed, and the on-off of a device channel is controlled by utilizing a double-gate structure. Taking an N-type TFET device as an example, a very narrow N is formed between a device source region and a channel region in an on state + In the pocket region, the tunneling barrier width is reduced and the on-current is increased. A P-type gap is formed between the drain region and the channel region of the device in the off state, and the potential barrier width near the drain region can be adjusted by changing the length of the gap, so that the purpose of reducing bipolar current is achieved.
The invention is described in further detail below with reference to the attached drawing figures:
referring to FIG. 1, an electrostatic doped tunnel in the present inventionThe field effect transistor comprises a P-type heavy doping source region 7, an N-type heavy doping pocket region 2, a P-type light doping channel region 1 and an N-type heavy doping drain region 8 which are transversely and sequentially arranged; the top and the bottom of the P-type heavily doped source region 7 are respectively a top first polar gate oxide layer 3c and a bottom first polar gate oxide layer 3d, the thicknesses of the top first polar gate oxide layer 3c and the bottom first polar gate oxide layer 3d are the same, and the P-type heavily doped source region 7 is made of the same material, the top of the top first polar gate oxide layer 3c is a top first polar gate electrode 5a, the bottom of the bottom first polar gate oxide layer 3d is a bottom first polar gate electrode 5b, the top first polar gate electrode 5a and the bottom first polar gate electrode 5b have the same work function, a source electrode contact region 9a is arranged on the side surface of the P-type heavily doped source region 7, the source electrode contact region 9a is composed of nickel silicide, and the schottky barrier height is 0.45eV; the top control gate oxide layer 3a and the bottom control gate oxide layer 3b are respectively arranged above and below the P-type lightly doped channel region 1, and the doping concentration of the P-type lightly doped channel region 1 is 1 multiplied by 10 17 cm -3 A drain region-channel region top side wall 11a is arranged on one side, close to the N-type heavily doped drain region 8, above the P-type lightly doped channel region 1, the length of the drain region-channel region top side wall 11a is 5-30 nm, a drain region-channel region bottom side wall 11b is arranged on one side, close to the N-type heavily doped drain region 8, below the P-type lightly doped channel region 1, and the length of the drain region-channel region bottom side wall 11b is 5-30 nm; a top control gate electrode 4a is arranged above the top control gate oxide layer 3a, and a bottom control gate electrode 4b is arranged below the bottom control gate oxide layer 3 b; the top and bottom of the N-type heavily doped drain region 8 are respectively a top second-polarity gate oxide layer 3e and a bottom second-polarity gate oxide layer 3f, the thicknesses of the top second-polarity gate oxide layer 3e and the bottom second-polarity gate oxide layer 3f are the same, and the N-type heavily doped drain region is made of the same material, the top second-polarity gate electrode 6a is arranged above the top second-polarity gate oxide layer 3e, the bottom second-polarity gate electrode 6b is arranged below the bottom second-polarity gate oxide layer 3f, and the top second-polarity gate electrode 6a and the bottom second-polarity gate electrode 6b haveWith the same work function, the side of the N-type heavily doped drain region 8 is provided with a drain electrode contact region 9b, the drain electrode contact region 9b being composed of nickel silicide, the schottky barrier height of which is 0.45eV. The doping concentration of the N-type heavily doped pocket region 2 is 4 multiplied by 10 19 cm -3 The length is 1 nm-9 nm, and the upper part and the lower part of the N-type heavily doped pocket region 2 are respectively a source region-channel region top side wall 10a and a source region-channel region bottom side wall 10b.
Referring to fig. 2, an initial structure of an electrostatic doped tunneling field effect transistor according to the present invention is shown, wherein the initial structure includes a lateral N-type heavily doped source region 13 and a P-type lightly doped channel and drain region 12. According to the polarity bias principle, when a certain negative bias is applied to the top first polarity gate electrode 5a and the bottom first polarity gate electrode 5b, a large number of holes are induced in a part of the source region below the top first polarity gate electrode and the bottom first polarity gate electrode, so that a P-type heavily doped source region 7 is formed. When a certain positive bias is applied between the top second polarity gate electrode 6a and the bottom second polarity gate electrode 6b, a large amount of electrons are induced in the partial drain region below the top second polarity gate electrode, and an N-type heavily doped drain region 8 is formed. The P-type heavy doping source region and the N-type heavy doping drain region are both formed by electrostatic doping, the traditional chemical doping steps such as ion implantation are not needed, and standard PN junctions can be realized within the range of a few nanometers.
The working principle of the electrostatic doped tunneling field effect transistor in the invention is as follows:
1. in the on state, the field effect transistor forms a PNPN structure, and the on current is increased.
For an N-type tunneling field effect transistor, when the work function of the first polarity gate electrode is smaller (< 4.33 eV) and a sufficiently large negative voltage (< -0.7V) is applied, a large amount of holes are induced in a part of the source region below the first polarity gate electrode according to the polarity bias principle, so that a P-type heavily doped region is formed. Therefore, the N-type heavily doped source region of the initial structure is replaced by the P-type heavily doped source region and the N-type heavily doped pocket region. Meanwhile, the work function of the second polar gate electrode is also smaller (< 4.5 eV), and when a sufficiently large positive voltage (> 0.7V) is applied, a large amount of electrons are induced in a part of the drain region below the second polar gate electrode according to the polar bias principle, so that an N-type heavily doped region is formed. Therefore, the P-type lightly doped region of the initial structure is replaced by a P-type lightly doped channel and an N-type heavily doped drain region, and the field effect transistor forms a PNPN structure, which is characterized in that: in the on state, an N-type heavily doped pocket part between the source region and the channel can introduce a local minimum point on the energy band, so that the tunneling barrier width is rapidly reduced, the tunneling probability of carriers is greatly increased, and therefore, the on current is also increased.
2. In the off state, the bipolar current decreases.
For N-type devices, when a sufficiently large negative voltage is applied to the control gate electrode<-0.7V) the energy band of the channel is raised and when the valence band of the channel is higher than the conduction band of the drain, the carrier may experience inter-band tunneling between the channel and the drain, and bipolar current increases. And the tunneling probability of carriers is inversely proportional to the tunneling barrier width near the drain region, and the larger the tunneling barrier width is, the smaller the tunneling probability is, and the smaller the bipolar current is. Because the bipolar current is increased to seriously reduce the performance of the TFET device, the gap length L between the drain region and the channel can be increased by reducing the length of the second polarity gate electrode on the premise that the total length of the device is kept unchanged gap Bipolar current is further reduced. Thus, the tunnel barrier width near the drain region of the device is controllable.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The electrostatic field doped tunneling field effect transistor is characterized by comprising a P-type heavy doped source region (7), an N-type heavy doped pocket region (2), a P-type light doped channel region (1) and an N-type heavy doped drain region (8) which are transversely and sequentially arranged;
the top and the bottom of the P-type heavily doped source region (7) are respectively a top first polar gate oxide layer (3 c) and a bottom first polar gate oxide layer (3 d), the top of the top first polar gate oxide layer (3 c) is a top first polar gate electrode (5 a), the bottom of the bottom first polar gate oxide layer (3 d) is a bottom first polar gate electrode (5 b), and a source electrode contact region (9 a) is arranged on the side surface of the P-type heavily doped source region (7);
the upper part and the lower part of the P-type lightly doped channel region (1) are respectively a top control gate oxide layer (3 a) and a bottom control gate oxide layer (3 b), a top control gate electrode (4 a) is arranged above the top control gate oxide layer (3 a), and a bottom control gate electrode (4 b) is arranged below the bottom control gate oxide layer (3 b);
the top and the bottom of the N-type heavily doped drain region (8) are respectively a top second polar gate oxide layer (3 e) and a bottom second polar gate oxide layer (3 f), the top of the top second polar gate oxide layer (3 e) is a top second polar gate electrode (6 a), the bottom of the bottom second polar gate oxide layer (3 f) is a bottom second polar gate electrode (6 b), and a drain electrode contact region (9 b) is arranged on the side face of the N-type heavily doped drain region (8).
2. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said top (3 c) and bottom (3 d) first polar gate oxide layers are of the same thickness and made of the same material.
3. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said top (3 e) and bottom (3 f) second polar gate oxide layers are of the same thickness and made of the same material.
4. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said top first polarity gate electrode (5 a) and bottom first polarity gate electrode (5 b) have the same work function, and said top second polarity gate electrode (6 a) and bottom second polarity gate electrode (6 b) have the same work function.
5. The electrostatic field doped tunneling field effect transistor according to claim 1, wherein said N-type heavy materialThe doping concentration of the doped pocket region (2) is 4 multiplied by 10 19 cm -3 The length is 1 nm-9 nm.
6. An electrostatic field doped tunneling field effect transistor according to claim 1, wherein said P-type lightly doped channel region (1) has a doping concentration of 1 x 10 17 cm -3 。
7. An electrostatic field doped tunneling field effect transistor according to claim 1, wherein the top and bottom of said N-type heavily doped pocket region (2) are a source-channel region top sidewall (10 a) and a source-channel region bottom sidewall (10 b), respectively; a drain region-channel region top side wall (11 a) is arranged on one side, close to the N-type heavily doped drain region (8), of the upper side of the P-type lightly doped channel region (1), and a drain region-channel region bottom side wall (11 b) is arranged on one side, close to the N-type heavily doped drain region (8), of the lower side of the P-type lightly doped channel region (1).
8. An electrostatic field doped tunneling field effect transistor according to claim 7, wherein said drain-channel region top sidewall (11 a) has a length of 5nm to 30nm; the length of the drain region-channel region bottom side wall (11 b) is 5 nm-30 nm.
9. An electrostatic field doped tunneling field effect transistor according to claim 1, characterized in that said source electrode contact region (9 a) and drain electrode contact region (9 b) are each comprised of nickel silicide with a schottky barrier height of 0.45eV.
10. An electrostatic field doped tunneling field effect transistor according to claim 1 wherein said field effect transistor has a central axis in a horizontal direction and has a symmetrical structure in two parts above and below said central axis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310799220.4A CN116845109A (en) | 2023-06-30 | 2023-06-30 | Electrostatic doped tunneling field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310799220.4A CN116845109A (en) | 2023-06-30 | 2023-06-30 | Electrostatic doped tunneling field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116845109A true CN116845109A (en) | 2023-10-03 |
Family
ID=88164716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310799220.4A Withdrawn CN116845109A (en) | 2023-06-30 | 2023-06-30 | Electrostatic doped tunneling field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116845109A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117810264A (en) * | 2024-01-17 | 2024-04-02 | 中国科学院半导体研究所 | Tunneling device and preparation method thereof |
-
2023
- 2023-06-30 CN CN202310799220.4A patent/CN116845109A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117810264A (en) * | 2024-01-17 | 2024-04-02 | 中国科学院半导体研究所 | Tunneling device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9269775B2 (en) | Tunneling devices and methods of manufacturing the same | |
| US6617643B1 (en) | Low power tunneling metal-oxide-semiconductor (MOS) device | |
| US8629428B2 (en) | Line-tunneling tunnel field-effect transistor (TFET) and manufacturing method | |
| CN101740621B (en) | Tunnel field-effect transistor with metal source | |
| US7839209B2 (en) | Tunnel field effect transistor | |
| US8653504B2 (en) | Complementary tunneling field effect transistor and method for forming the same | |
| US8288803B2 (en) | Tunnel field effect devices | |
| JP2003533887A (en) | Charge carrier extraction transistor | |
| CN116845109A (en) | Electrostatic doped tunneling field effect transistor | |
| KR20010032538A (en) | Field effect transistor | |
| US8853824B1 (en) | Enhanced tunnel field effect transistor | |
| JPH0624208B2 (en) | Semiconductor device | |
| KR101910579B1 (en) | Graphene switching device having tunable barrier | |
| EP0482726A2 (en) | Heterojunction field-effect transistor | |
| KR101576267B1 (en) | Esaki Tunneling Assisted Tunnel Field-Effect Transistor | |
| CN105702721A (en) | Novel asymmetric double-gate tunnelling field effect transistor | |
| Keighobadi et al. | Switching performance investigation of a gate-all-around core-source InGaAs/InP TFET | |
| JP7164204B2 (en) | tunnel field effect transistor and electronic device | |
| KR20190105768A (en) | Tunneling field effect transistor having a gate overlap the source and drain | |
| KR102273935B1 (en) | Tunnel field-effect transistor based on negative differential transconductance | |
| Wang et al. | Recessed-anode AlGaN/GaN diode with a high Baliga's FOM by combining a p-GaN cap layer and an anode-connected p-GaN buried layer | |
| CN109560128B (en) | Tunneling field effect transistor | |
| JP3840036B2 (en) | Compound semiconductor epitaxial wafer and HEMT | |
| US3500138A (en) | Bipolar mos field effect transistor | |
| CN109244121B (en) | Longitudinal tunneling field effect transistor with grid field plate structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20231003 |
|
| WW01 | Invention patent application withdrawn after publication |