JPH04356928A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an emitter region, an intrinsic base and an outer base in a self-aligned manner by a method wherein, after second epitaxial and polycrystalline growth operations have been executed simultaneously, a mask material having a sidewall film is left only in the emitter region, high- concentration ions are implanted only into the outer base and the mask material is removed. CONSTITUTION:An epitaxial layer 5 and a poly-Si layer 6 are formed by executing second epitaxial and polycrystalline growth operations. The poly-Si other than an element part is removed; after that, an SiO2 film 7 is formed on the whole surface. Then, a poly-Si layer is formed on the whole surface; an SiO2 film is formed on the surface of the poly-Si layer 8 in an emitter part; after that, a sidewall 9 is formed on the side face of the poly-Si film 8. Only a collector extraction part is covered with a resist; boron ions are implanted. After that, an SiO2 film is formed; after that, a polishing operation is executed by using the poly-Si layer 8 as a stopper. Then, the poly-Si layer 8 is removed selectively. Then, a poly-Si layer 11 is deposited on the epitaxial growth layer 5 and the poly-Si layer 6; after that, arsenic ions are implanted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing ultrahigh speed bipolar transistors. In order to further increase the operating speed of a bipolar transistor, it is required to further increase the impurity concentration of the base layer and to further reduce the thickness (depth) of the diffusion layer. For this reason, it has become difficult to meet this requirement using the normal ion implantation method, and instead a method of forming the base layer by low-temperature epitaxial growth has been attempted.

0002

[Prior Art] Conventionally, when forming an intrinsic base layer by a silicon (Si) epitaxial growth method in order to form a base extraction electrode, a polysilicon (Si) layer which will become an external base electrode is simultaneously grown on a field insulating film. Either the epi-poly co-growth method was used, or the extrinsic base layer was formed separately from the intrinsic base layer. The former is as shown in the structural diagram of the main part of a bipolar transistor in FIG. 3(a). A field oxide film 32 and a collector active region 34 are formed on the surface of a silicon substrate (or epitaxial layer) 31. Collector active region 34 is formed by epitaxial growth method.
An intrinsic base (internal base layer) 35 is formed on the top, and at the same time, a poly-Si layer 3 is formed on the field oxide film 32.
6 is formed. An emitter layer 37 is formed at the center of the surface of the intrinsic base 35 by diffusion of impurities from the highly doped poly-Si layer 38.

0003

[Problem to be solved by the invention] However, the intrinsic base layer 3
Since 5 is very thin, polyS is used as the external base electrode.
The i-layer 36 is also very thin. Therefore, the external base resistance increases, and the operating speed of the transistor does not increase. To this end, there is a method of forming a thick extrinsic base layer separately from the intrinsic base layer to reduce the extrinsic base resistance. This is as shown in FIG. 3(b). In this case, the poly-Si layer 39 is deposited in an overlapping manner on the poly-Si layer 36, so that the external base resistance can be reduced. However, the drawback was that the manufacturing process was complicated.

[0004] Accordingly, an object of the present invention is to provide a method for manufacturing an ultrahigh-speed bipolar transistor that has a low-resistance base portion (a term that includes an intrinsic base layer and an extrinsic base layer) and that does not require complicated manufacturing processes. .

[0005]

[Means for solving the problem] The above problem is to form a poly-Si layer (external base layer) that will become a collector active layer and a base extraction electrode by epi-poly simultaneous growth on a Si substrate on which a field oxide film has been formed. After that, there is a step of forming an intrinsic base layer and a poly-Si layer by a second epi-poly simultaneous growth overlapping this, and a step of forming a high concentration layer on the poly-Si layer and the external base layer by masking the emitter region. The ion implantation process and SOG (Spin O
After flattening the surface with a masking material such as N Glass, the emitter layer,
This problem is solved by a manufacturing method that includes a step of forming an intrinsic base layer and an external base layer in self-alignment.

FIG. 1 is a diagram explaining the principle of the present invention. In the figure, 1 is a substrate, and 2 is a field oxide film layer formed on the surface of the substrate 1. Reference numerals 3 and 4 denote an n-type collector active region layer and an external base layer, respectively, which are formed by simultaneous epi-poly growth. Reference numerals 5 and 6 denote a p-type intrinsic base layer and a poly-Si layer, which are formed on the collector active region layer 3 and the external base layer 4, respectively, by simultaneous epi-poly growth. 7 is silicon dioxide (SiO2
) film, 8 is a mask material such as poly-Si, 9 is SiO
This is the sidewall film of No. 2.

[0007]

[Effect] As shown in Figure 1, the second epi-
Poly simultaneous growth (intrinsic base layer 5 and poly-Si layer 6)
Later, if the mask material 8 (for example, poly-Si) having the sidewall film 9 is left only in the emitter region, high-concentration ion implantation can be performed only in the external base region. In this way, a low-resistance base lead-out electrode can be formed without complicating the manufacturing process.

[0008] Thereafter, by selectively removing the mask material 8, the emitter region, the intrinsic base, and the extrinsic base can be formed in a self-aligned manner.

[0009]

Embodiments Examples of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram explaining the manufacturing method in this example, and FIGS. 2(a), 2(b), and 2(c) are diagrams showing the main parts of the manufacturing process, respectively. The various process technologies used in the manufacturing process are well known in conventional bipolar transistor manufacturing, and will only be briefly explained.

After forming a heavily doped n-type buried layer 21 on the surface of the Si substrate 1, an n-type epitaxial layer 22 of 1 Ωcm and 1 μm thick is grown. Next, element isolation regions 2 are formed on the surface. after that,
A diffusion layer 23 serving as a collector lead-out portion is provided. Next, epitaxial growth is performed on the epitaxial layer 22 and on the element isolation region 2, respectively, to form an epitaxial growth layer 3 and a poly-Si layer 4. The conditions for this CVD growth are, for example, as follows. Disilane (Si2H6) was used as the reaction gas, the growth temperature was 750°C, and the gas pressure was 1 Torr. And the specific resistance of the epitaxial growth layer 3 is n
The mold is 1.0 Ωcm and the thickness is 200 nm. Next, a second epitaxial growth is performed on the epitaxial growth layer 3 and the poly-Si layer 4, thereby forming an epitaxial growth layer 5 that will become an intrinsic base layer and a poly-Si layer 6 that will become an extrinsic base layer. be done. The specific resistance of the epitaxial growth layer 5 is p-type 0.02Ωcm
, the thickness is 70 nm. Then, phosphorus ions are selectively implanted into the collector lead-out section. As a result, the epitaxial growth layer 5 and the poly-Si layer 6 in the collector lead-out portion are converted to n-type. Next, after removing the poly-Si other than the element portion by reactive ion etching (RIE), a 30 nm thick SiO2 film 7 is formed on the entire surface by CVD.
Next, a poly-Si layer with a thickness of 200 nm was formed on the entire surface.
The poly-Si layer other than the emitter portion is removed by RIE. C is applied to the surface of the remaining poly-Si layer 8 in the emitter section.
After forming a 100 nm thick SiO2 film by the VD method, sidewalls 9 are formed on the sides of the poly-Si layer 8 by the RIE method. The state at this stage is shown in FIG. 2(a).

[0011] Only the collector lead-out portion is covered with resist, and boron ion implantation is performed with an ion energy of 2.
At 0 KeV, the dose is 3 x 1015 cm
- Performed under the conditions of 2. After that, it was made to a thickness of 500 mm using the CVD method for planarization.
After forming the SiO2 film 10 with a thickness of 100 nm, the poly-Si layer 8 is
Use this as a stopper to perform polishing. For this flattening, it is also possible to apply SOG instead of using the SiO2 film. Next, poly-Si was coated with a caustic potash solution.
Layer 8 is selectively removed. SiO in the collector drawer
An opening is provided in the SiO2 film 10, and the SiO2 film 7 is etched and removed using a hydrofluoric acid solution. At this time, the SiO2 film 7 in the emitter section is also removed at the same time. The state at this stage is shown in FIG. 2(b).

After this, a 100 nm thick layer is formed on the epitaxial growth layer 5 in the emitter section, the epitaxial growth layer 5 in the collector lead-out section, and the poly-Si layer 6.
A poly-Si layer 11 is deposited, and arsenic ions are implanted into this. The implantation conditions were an energy of 30 KeV,
The dose was 1 x 1016 cm-2, and then
For example, annealing is performed at 1100°C for 10 seconds. As a result, an emitter layer 12 is formed inside the intrinsic base layer 5 in contact with the interface between the intrinsic base layer 5 and the poly-Si layer 11. After removing the poly-Si layer 11 other than the emitter part and the collector lead-out part, the base window 13 is opened. After this, metal electrodes 14 are formed on the emitter section, base section, and collector lead-out section.
The bipolar transistor structure is completed. The state at this stage is shown in FIG. 2(c).

[0013]

[Effects of the Invention] According to the present invention, a bipolar transistor having a thin base layer with a high impurity concentration and a structure in which a low resistance external base and an emitter are self-aligned has been realized, which contributes to speeding up the bipolar transistor. There's a lot to do.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1, 31 Si substrate 2, 32 Field oxide film 3, 34 Collector active region layer 4, External base layer 5, 35 Intrinsic base layer 6, 11, 38, 39 Poly-Si layer 7, 1
0 SiO2 film 8 Mask material 9 Sidewall film 12, 37 Emitter layer 13 Base window 14 Metal electrode

Claims (4)

[Claims] Claim 1. A method for manufacturing a semiconductor device having a base lead-out electrode portion on a field insulating film formed on a semiconductor substrate, in which a silicon single crystal layer serving as a collector active region and a base lead-out electrode portion are formed by epi-poly simultaneous growth. A process of forming a polysilicon layer that will become the intrinsic base layer, a process of forming a silicon epitaxial layer that will become the intrinsic base layer, a process of forming a mask material with sidewalls only in the emitter region, and a process of high-concentration ion implantation only in the base extraction electrode. 1. A method for manufacturing a semiconductor device, comprising the steps of: performing a step of flattening the mask material; and selectively removing the mask material after planarization. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the intrinsic base layer is formed by one of a low-temperature epitaxial growth method and a simultaneous epi-poly growth method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the mask material is polysilicon, and the sidewall is made of one of silicon oxide and silicon nitride. 4. The planarization is performed using a silicon dioxide chemical vapor deposition (CVD) method and an SOG (Spin On
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is carried out by one of the glass coating methods.