JPH04355382A - Apparatus and method for inspecting integrated circuit - Google Patents

Abstract

PURPOSE:To enhance inspecting accuracy by enhancing the fault detecting rate for an integrated circuit. CONSTITUTION:An electron beam 4 is emitted from an electron beam tester 3 on the output node part of the gate of an integrated circuit 2. Secondary electrons 5 which are discharged as a result are received with the detecting part of the electron beam tester 3. The potential is measured based on the detected amount. The logic values 1 and 0 are identified based on the potential, and the result is sent into a collator 7. The measurement is performed for each gate of the integrated circuit. In the collator 7, all measured results are collated with the test vector of a good product from a good-product-test-vector generator 8, and the good or bad state of the integrated circuit 2 is judged.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit testing device and method.

0002

2. Description of the Related Art In conventional integrated circuit testing, test vectors for testing are input to the integrated circuit, the integrated circuit is actually operated, and the quality of the integrated circuit is determined based on the output results. FIG. 2 is a block diagram showing a conventional inspection device. A test vector generator 9 generates an input test vector 10 and an output expected value vector 11. The input test vector 10 is a test pattern input to the integrated circuit 12 to be tested, and the output expected value vector 11 means correct output pattern data for this input test pattern. The integrated circuit 12 is provided in advance with a plurality of measurement points (output terminals and test terminals provided at intermediate points of the circuit), and the output signals obtained at these measurement points in response to the input of the input test vector 10 are are sequentially sent to the collation unit 13. The collation unit 13 collates this output signal with the output expected value vector 11 from the test vector generator 9 to determine pass/fail and generates a pass/fail determination signal.

0003

[Problems to be Solved by the Invention] As described above, in the conventional example, pass/fail judgment is made based on the output signal for the input test vector. In particular, the input test vector is limited because it is impossible to cover all usage patterns. The following failure patterns may not be detected.

FIG. 3 is a circuit diagram showing a part of the circuits constituting the integrated circuit. This is a configuration example in which an AND circuit (AND) 14 and an OR circuit (OR) 15 are connected in series. Now, all of the input signals 101, 102, and 103 have a logical value of 1.
Then, the expected value of the output signal 104 is a logical value of 1,
Therefore, if the output signal 104 has a logical value of 1, it is determined that the product is non-defective. However, AND14 fails and its output is a logic 0.
Even so, as long as the input signal 103 has a logical value of 1, the output signal 104 has a logical value of 1, so a failure of the AND 14 cannot be detected. In order to detect this fault, it is necessary to make the input pattern, that is, the input test vector, more diverse and longer, or to increase the number of test terminals, but there is a practical limit to this. Therefore, in the conventional example, there is a problem that the failure detection rate is low.

[0005]

[Means for Solving the Problems] An integrated circuit inspection apparatus of the present invention includes a first means for measuring an output node potential of a gate of an integrated circuit using an electron beam, and a first means for measuring the output node potential of a gate of an integrated circuit; and second means for determining the quality of the integrated circuit by comparing the output node potential of the non-defective integrated circuit. The first means is:
This can be performed by irradiating the output node portion with the electron beam and measuring reflected secondary electrons.

The integrated circuit testing method of the present invention measures the output node potential of the gate of the integrated circuit using an electron beam, and compares the measured output node potential with the output node potential of the non-defective integrated circuit prepared in advance. The quality of the integrated circuit is determined by checking the quality of the integrated circuit.

[0007]

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. The inspection is performed during the integrated circuit manufacturing process, and is performed on the chip-shaped integrated circuit 2 on the semiconductor substrate 1 at the time when the wiring process is completed. In this integrated circuit testing apparatus, first, an electron beam 4 is irradiated from the irradiation section 31 of the electron beam tester 3 toward the output node section of the gate of the integrated circuit 2 . The secondary electrons 5 emitted as a result are received by the detection section 32 of the electron beam tester 3, and the potential is measured from the detected amount. Logical values 1 and 0 are identified from this potential and the results are sent to the collation unit 7. This measurement is performed for each gate of the integrated circuit,
The collation unit 7 collates all measurement results with the non-defective test vector from the non-defective test vector generator 8 and outputs the result to the integrated circuit 2.
Determine the quality of the product. The non-defective test vector indicates the expected value of a non-defective integrated circuit.

The above-mentioned measurements are performed with the integrated circuit 2 in an operating state in which a fixed pattern is input. In addition, the electron beam tester 3 is similar to a commonly used one for failure analysis of integrated circuits (measuring the potential at each point inside the integrated circuit without contact with an electron beam); However, a function to automatically perform the above-mentioned measurements has been added. Furthermore, it is also possible to simultaneously measure a plurality of output node potentials using a plurality of electron beams to speed up the measurement.

[0009]

Effects of the Invention As explained above, the present invention determines whether the integrated circuit is good or bad by measuring the potential of the output node of each gate that makes up the integrated circuit, resulting in a high failure detection rate and high inspection accuracy. It has the effect of increasing

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of this embodiment.

FIG. 2 is a block diagram showing the configuration of a conventional example.

FIG. 3 is a circuit diagram showing part of a circuit that constitutes an integrated circuit.

[Explanation of symbols]

1 Semiconductor substrate 2 Integrated circuit 3　　　Electron beam tester 4 Electron beam 5 Secondary electrons 7. Collator 8. Good product test vector generator

Claims (3)

[Claims] 1. A first means for measuring an output node potential of a gate of an integrated circuit using an electron beam, and comparing the measured output node potential with a previously prepared output node potential of a non-defective integrated circuit. and second means for determining the quality of the integrated circuit. 2. The integrated circuit inspection apparatus according to claim 1, wherein the first means is performed by irradiating the electron beam onto an output node portion of the gate and measuring reflected secondary electrons. . 3. The output node potential of the gate of the integrated circuit is measured using an electron beam, and the measured output node potential is compared with the output node potential of the non-defective integrated circuit prepared in advance. 1. A method for testing an integrated circuit, the method comprising determining the quality of an integrated circuit.