JPH04355270A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To retain synchronizing detection information when the synchronizing state between a digital input and its reproducing clock is changed and to quickly change over the selection of a system clock and input signal when the digital input is unlocked. CONSTITUTION:An identification signal SLAD of a system control means 15 is taken in a synchronization detection means 13 as the condition of synchronization discrimination, and when the digital input is unlocked, the system control means 15 detects it with a synchronizing detection signal DILOK and prevent a synchronization discrimination result from being updated until the identification signal SLAD is changed over.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording and reproducing apparatus such as a digital audio tape recorder.

0002

2. Description of the Related Art In a recording/reproducing apparatus equipped with a digital interface, a PLL (Phase Locked Loop) circuit is used as a method for extracting a clock component of an input digital signal. For example, IEC (Inter
national electrotechnical
DAT (Digital Au
dio Tape Recorder), the clock signal superimposed on the digital signal is extracted using three types of synchronization signals, B-amble, W-amble, and M-amble included in the input digital signal, and Based on this, the PCM data of the main information, channel status bits, user's bits, etc. of the accompanying information are demodulated.

FIG. 5 is a block diagram showing the configuration of a conventional DAT system. Hereinafter, clock reproduction of a digital audio interface in a conventional DAT and control of input signal and system clock selection will be explained using FIG.

In FIG. 5, 10 is an A/D converter that converts an analog input signal into PCM data, 11 is demodulation means that demodulates a digital input signal, 12 is clock regeneration means that extracts a clock signal from the digital input signal, and 14 16, 17, and 18 are selectors; 19 is a memory for storing reproduced data; and 20 is a memory control for sequentially reading reproduced data from the memory 19. 43 is a synchronization signal detection means for detecting that the reproduced clock output from the clock regeneration means 12 is synchronized with the digital input signal; 45 is a synchronization signal detection means for selecting inputs and setting the system operation mode; This is a system control means that controls the selectors 16, 17, and 18 according to the output of the synchronization detection means 43.

[0005] The operation of the recording/reproducing apparatus having the above-mentioned components will be explained below. When the operating mode of the system is a reproduction mode, reproduction signals reproduced from a recording medium such as a magnetic tape are temporarily stored in a memory 19, and after being subjected to error correction processing, etc., are read out by a memory control means 20 in the order in which they were recorded. The memory control means 20 outputs the read data as reproduced data PBDT. At this time, the selector 17 selects and outputs the reproduced data PBDT according to the operation mode signal SLPR output from the system control means 45. Also selector 18
is the output ADCK of the clock generation means 14 according to the input selection signal SLAD outputted from the system control means 45.
Select and output this as the system clock.

When the operating mode of the system is the recording mode, at least one of the analog signal AIN and the digital signal DIN is supplied to the recording/reproducing apparatus as an input signal to be recorded. The analog input signal AIN is converted into PCM data ADDAT in the A/D converter 10 based on the master clock ADCK input from the clock generation means 14. On the other hand, digital input signal D
IN is input to the demodulating means 11, the clock reproducing means 12 and the synchronization detecting means 43. The clock reproducing means 12 extracts the clock signal DICK from the digital input signal DIN by comparing the phases of the input signal and the reproduced clock by the PLL circuit. Also, the clock signal DIC
A frequency-divided signal DI128 of K is generated, and this is sent to the demodulating means 1.
1 and the synchronization detection means 43. The demodulation means 11 converts the main information PCM data DIDA from the digital input signal DIN using the frequency-divided signal DI128 of the reproduced clock.
Demodulate T. Further, the synchronization detection means 43 regularly determines whether the frequency and phase of the frequency-divided signal DI128 of the reproduced clock are correct and synchronized with the digital input signal DIN.

FIG. 6 is a block diagram showing a more detailed configuration of the synchronization detection means 43. In FIG. 6, the synchronization signal detection unit 21 detects the synchronization signals B-amble, W-amble, and M-amble by latching the digital input signal DIN with the frequency-divided signal DI128 of the reproduced clock, and detects the results. Output as signal SYNC. The synchronization determination unit 53 manages the periodicity of the synchronization signal detection signal SYNC using the control signal DIFS generated from the frequency division signal DI128 in the control signal generation unit 22, and determines the frequency and phase of the frequency division signal DI128 of the reproduced clock. is synchronized with the digital input signal DIN. The result of the determination is input to the system control means 45 as a synchronization detection signal DILOK. System control means 45
is the manually set input selection signal SLAD, system operation mode signal SLPR, and synchronization detection signal DI.
Selectors 16, 17, and 18 are controlled according to LOK. In other words, when recording analog input signals, A/D
The output ADDAT of the converter 10 is selected by selectors 16 and 17.
the output ADC of the clock generation means 14.
K is selected using the selector 18. In addition, when recording a digital input signal, the output DIDAT of the demodulation means 11
are selected by the selectors 16 and 17, respectively, and the output DICK of the clock reproducing means 12 is selected by the selector 18.

FIG. 7 is a block diagram showing a more detailed configuration of the system control means 45. In FIG. 7, input selection information, system operation mode information, etc. are set in the setting section 24. The decoding unit 25 extracts input selection information and system operation mode information from the output of the setting unit 24. The processing section 26 uses the input selection information and operation mode information outputted from the decoding section 25 and the synchronization detection signal DILOK outputted from the synchronization detection means 43 to determine the input selection signal SLAD and operation mode according to the procedure of the flowchart shown in FIG. Generate signal SLPR. That is, step 70
It is determined whether the manually set operation mode is a recording mode or a mode other than the recording mode, such as a playback mode. As a result of the determination, if the mode is other than the recording mode, the input selection signal SLAD and the operation mode signal SLPR are each set to "0" in step 76. by this,
Memory control means 20 in selector 17 in FIG.
The reproduced data PBDT outputted from the clock generator 14 is selected as the PCM output by the selector 18.
The clock signal ADCK output from the system clock is selected as the system clock. On the other hand, if the result of the determination in step 70 is that the operation mode is the recording mode, the operation mode signal SLPR is set to "1" in step 71. Further, if the manually set input selection in step 72 is an analog input, the input selection signal SLAD is set to "0" in step 75. As a result, the PCM data ADDAT of the analog input signal output from the A/D converter 10 is selected by the selector 16 in FIG. 5, and is output as a PCM output via the selector 17. Further, the selector 18 selects the clock signal ADCK output from the clock generation means 14 and outputs it as a system clock. If the set input selection is digital input, in step 73 the synchronization detection signal DILO output from the synchronization detection means 43 of FIG.
K determines whether the digital input and its reproduced clock signal are in synchronization (hereinafter, this state will be referred to as "the digital input is locked"). As a result of the determination, if the digital input is locked, the input selection signal SLAD is set to "1". As a result, the selector 16 selects the output DIDAT of the demodulating means 11 and outputs it via the selector 17 as a PCM output. Further, in the selector 18, the clock reproducing means 12
The reproduced clock signal DICK is selected and output as the system clock. As a result of the determination in step 73, the digital input is not locked (hereinafter referred to as
This state is called the "unlocked state". ), even if the setting by manual input is a digital input recording mode, it is disabled and the input selection signal SLAD and operation mode signal SLPR are set to "0" to prohibit the recording operation.

As described above, the conventional DAT shown in FIG. 5 generates an input selection signal and an operation mode signal from manually set information, and switches these settings according to the result of digital input synchronization detection. Ta.

0010

[Problems to be Solved by the Invention] However, in the above-mentioned conventional configuration, while recording digital input, the system control means is in an unlocked state for a period shorter than the synchronization period during which a change in the synchronization detection signal can be detected. During this time, there is a problem in that the recording operation continues without being able to detect that the reproduced clock of the digital input has stopped or that the frequency or phase of the reproduced clock has changed. Also,
Even if the system control means is able to detect a change in the synchronization detection signal, there is a problem in that the system malfunctions because the abnormal clock signal becomes the system clock until the system clock selection is switched accordingly. Ta.

The present invention solves the above-mentioned conventional problems, and a first object thereof is to provide a recording/reproducing apparatus that can control a synchronization detection signal of a digital input in accordance with an operation mode signal by a system control means. . Furthermore, it is an object of the present invention to provide a recording/reproducing device in which the system control means can immediately switch the selection of the system clock when the digital input changes from the locked state to the unlocked state, in addition to the normal step of determining the synchronization detection signal. This is the second purpose.

0012

[Means for Solving the Problems] In order to achieve this object, the recording and reproducing apparatus of the present invention includes a clock reproducing means for receiving an input digital signal and extracting a clock component, and an output of the clock reproducing means that is digital. synchronization detection means for detecting synchronization with the input signal; demodulation means for demodulating the digital input signal using the output of the clock regeneration means to extract main information and additional information; A clock generation means for generating a predetermined clock signal, a system control means for selecting an input and setting an operation mode of the system and controlling the system accordingly, and an output of the demodulation means in accordance with an output of the system control means. It has a configuration including a selector for selecting, and a selector for selecting the output of the clock reproducing means or the output of the clock generating means depending on the output of the system control means.

[0013]

[Operation] With the above-described configuration, the present invention changes the output of the synchronization detection information in the synchronization detection means in accordance with the operation mode information output from the system control means, and the change in the synchronization detection information is confirmed by the system control means. The synchronization detection information can be held until the operation mode is changed. Further, when the synchronization detection information changes, the output of the system clock and the corresponding PCM data can be switched regardless of the input selection information set by the system control means. Furthermore, when selecting a digital input signal and its regenerated clock, by matching the frequency and phase of the clock of another system output from the clock generation means with the regenerated clock, the system Changes in the system clock can be kept to a minimum by substituting a clock from another system by the clock generation means until the control means detects it.

[0014]

Embodiments (Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a recording/reproducing apparatus according to a first embodiment of the present invention. In FIG. 1, 10 is an A that converts an analog input signal into PCM data.
/D converter, 11 is a demodulation means for demodulating the digital input signal, 12 is a clock regeneration means for extracting a clock signal from the digital input signal, and 13 is a clock regeneration means output from the clock regeneration means 12 in synchronization with the digital input signal. synchronization signal detection means for detecting that the
15 is a clock generation means for generating a clock signal at a predetermined frequency using a crystal oscillator; 15 is a clock generation means for selecting inputs and setting an operating mode of the system, and operating the system according to these settings and the output of the synchronization detection means 13; 16, 17 and 18 are selectors; 19 is a memory for storing reproduction data; and 20 is a memory control means for sequentially reading reproduction data from the memory 19. Note that the same components as in the conventional example shown in FIG. 5 are given the same reference numerals.

FIG. 2 also shows the synchronization detection means 1 in FIG.
FIG. 3 is a block diagram showing a more detailed configuration of FIG. In FIG. 2, 21 converts the digital input signal into a reproduced clock DI1.
28 is a synchronization signal detection unit that detects a synchronization signal by latching it; 22 is a control signal generation unit that generates a control signal DIFS using the reproduced clock DI128; and 23 is a synchronization detection signal SYNC output from the synchronization signal detection unit 21. and the control signal DIFS output from the control signal generation unit 22 and the identification signal SLAD output from the system control means.
This is a synchronization determination unit that determines whether the reproduced clock is synchronized with the digital input signal using the synchronization determination unit.

FIG. 3 shows the system control means 15 in FIG.
FIG. 2 is a block diagram showing a more detailed configuration. In FIG. 3, 24 is a setting unit that manually sets the system operation mode and input signal selection, 25 is a decoding unit that extracts the operation mode information and input selection information from the set information, and 26 is the decoding unit 25. A processing unit 27 generates an operation mode signal SLPR and an identification signal SLAD according to the synchronization detection signal DILOK output from the synchronization detection means 13 in FIG. The processing unit 2 detects that the reproduced clock is not synchronized with the digital input signal.
input selection signal SL from the identification signal SLAD generated in step 6.
This is an unlock detection unit that generates DI.

The operation of the recording/reproducing apparatus of this embodiment having the above-mentioned components will be explained below.

The operation of the system when the operating mode of the system is the reproduction mode is the same as that of the conventional recording/reproducing apparatus shown in FIG. 5, so a description thereof will be omitted.

When the operating mode of the system is the recording mode, one of the analog signal AIN and the digital signal DIN is supplied as the input signal to be recorded. The analog input signal AIN is a master clock AD input from the clock generation means 14 in the A/D converter 10.
It is converted into PCM data ADDAT based on CK. On the other hand, the digital input signal DIN is input to the demodulating means 11, the clock reproducing means 12 and the synchronization detecting means 43. The clock reproducing means 12 extracts the clock signal DICK from the digital input signal DIN by comparing the phases of the input signal and the reproduced clock by the PLL circuit. It also generates a frequency-divided signal DI128 of the clock signal DICK, and sends it to the demodulating means 11 and the synchronization detecting means 13.
supply to. The demodulating means 11 demodulates the main information PCM data DIDAT from the digital input signal DIN using the frequency-divided signal DI128 of the reproduced clock. In addition, in the synchronization detection means 13, the frequency division signal DI of the reproduced clock
The frequency and phase of 128 are constantly input to the digital input signal D.
Determine whether it is correct and synchronized with IN.

In FIG. 2, the synchronization signal detection section 21 receives the digital input signal D using the frequency-divided signal DI128 of the reproduced clock.
By latching IN, the synchronizing signals B-amble, W-amble, and M-amble are detected, respectively, and the results are output as the detection signal SYNC. Synchronization determination section 2
3, the control signal generation unit 22 generates the divided signal DI12.
The control signal DIFS generated from 8 is used to manage the periodicity of the synchronization signal detection signal SYNC, and it is determined whether the frequency and phase of the reproduced clock frequency division signal DI128 are synchronized with the digital input signal DIN. . At this time, the output of the synchronization detection signal DILOK is controlled according to the identification signal SLAD outputted from the system control means 15. That is, the clock signal ADC by the clock generation means 14
When the system is operating with K as the system clock, the identification signal SLAD becomes "0" and manages the periodicity of the synchronization signal detection signal SYNC in the same way as the synchronization determination section 53 in the conventional recording/reproducing apparatus shown in FIG. Then, it is determined whether the frequency and phase of the frequency-divided signal DI128 of the reproduced clock are correct and synchronized with the digital input signal DIN. As a result of the determination, if the reproduced clock is synchronized with the digital input signal, the synchronization detection signal DILOK is set to “1”.
”, and when they are not synchronized, it is set to “0”. However, when the system is operating using the recovered clock signal DICK by the clock recovery means 12 as the system clock, the identification signal SLAD becomes “1” and the recovered clock is set to digital input. When synchronization with the signal is lost, the synchronization detection signal DILOK is set to "0" at any time, but even if synchronization is performed again, the synchronization detection signal DILOK is set to "0".
The system control means 15 detects that the value has become 0'',
The synchronization detection signal DILOK is not set to "1" until the identification signal SLAD is set to "0".

The synchronization detection signal DILOK is input to the system control means 15. The system control means 15 generates an identification signal SLA from manually set input selection information, system operation mode information, and synchronization detection signal DILOK.
D, generates an operation mode signal SLPR and an input selection signal SLDI, and controls the selectors 16, 17, and 18. That is, when recording an analog input signal, the output ADD of the A/D converter 10 is
AT is selected by selectors 16 and 17, respectively, and output ADCK of clock generation means 14 is selected by selector 18. Further, when recording a digital input signal, the output DIDAT of the demodulation means 11 is selected by selectors 16 and 17, and the output DICK of the clock reproduction means 12 is selected by the selector 18.

In FIG. 3, input selection information, system operation mode information, etc. are set in the setting section 24. The decoding unit 25 extracts input selection information and system operation mode information from the output of the setting unit 24. The processing unit 26 is
Using the input selection information and operation mode information output from the decoding section 25 and the synchronization detection signal DILOK output from the synchronization detection means 13, the identification signal SLAD and the operation mode signal SLPR are generated according to the procedure of the flowchart shown in FIG. . A description of the flowchart shown in FIG. 8 will be omitted since it is the same as that of the processing section 26 in the conventional recording/reproducing apparatus shown in FIG.

Identification signal SLAD generated by processing section 26
is output to the synchronization detection means 13 in FIG. 1 and also input to the unlock detection section 27. Unlock detection section 27
is the synchronization detection signal DI output from the synchronization detection means 13
When the digital input is unlocked by constantly managing LOK, the input signal SLDI is immediately set to "0" regardless of the logic of the identification signal SLAD. by this,
Until the processing unit 26 detects the unlocked state using the synchronization detection signal DILOK and changes the identification signal SLAD to "0", the system clock is changed from the recovered clock DICK by the clock recovery means 12 to the clock generation means ADC.
Can be switched to K. Then, the synchronization detection signal DILOK can become "1" again only when the identification signal SLAD becomes "0" by the processing unit 26.

As described above, according to the recording/reproducing apparatus of the embodiment of the present invention, even if the reproduced clock suddenly becomes abnormal while the reproduced clock of the digital input is being used as the system clock, the system clock is immediately restored. can be changed to a stable clock system using a crystal oscillator, etc.
By switching the PCM output at the same time, it is possible to prevent noise from occurring.

(Embodiment 2) Furthermore, as a method of minimizing changes in frequency and phase when switching the system clock, the configuration shown in FIG. 4 can be cited. FIG. 4 is a block diagram showing the configuration of a recording/reproducing apparatus according to a second embodiment of the present invention. In FIG. 4, 10 is an A/D converter that converts an analog input signal into PCM data;
13 is a clock reproducing means for extracting a clock signal from the digital input signal; 13 is a synchronization signal detecting means for detecting that the reproduced clock outputted from the clock reproducing means 12 is synchronized with the digital input signal; 14 is a crystal oscillator; 16, 17, 18 are selectors; 19 is a memory for storing reproduced data; 20 is a memory control means for sequentially reading reproduced data from the memory 19; 31 is a digital Demodulates the input signal and extracts information about the recovered clock and PCM
Demodulation means 35 is a system control means that selects inputs and sets the operating mode of the system and controls the system according to these settings and the outputs of the synchronization detection means 13 and the demodulation means 31. Note that the same components as in the conventional example shown in FIG. 5 are given the same reference numerals.

The difference from the first embodiment of the present invention shown in FIG.
The second point is that the IFS is extracted, and the second point is that the system control means 35 controls the clock generation means 14 according to the information DIFS regarding the recovered clock. That is, the recovered clock DIC by the clock recovery means 12 is used as the system clock.
When selecting K, the system control means 35 obtains information regarding its frequency and phase from DIFS and generates a control signal SPFS. The clock generation means 14 always adjusts the frequency and phase of the generated clock ADCK to be the same as the reproduced clock DICK using the control signal SPFS. As a result, even if the digital input is unlocked and the system clock is switched from DICK to ADCK, there is no fluctuation in frequency and phase, and abnormalities in the recording signal can be avoided.

[0028]

As is clear from the above embodiments, according to the present invention, the synchronization detection means changes the output of the synchronization detection signal according to the operating mode of the system, so that the system control means can control the output of the synchronization detection signal. It is possible to hold the synchronization detection signal until a change is detected, and immediately transition to the next state when the operation mode is switched after detection. Also, regarding the selection signal that selects the input signal and system clock,
By controlling the selection of the input signal and system clock to be switched immediately when the digital input becomes unlocked when using the recovered clock of the digital input, abnormalities such as the system clock stopping can be avoided. Furthermore, while the regenerated clock of the digital input is used as the system clock, the regenerated clock is generated by unlocking the digital input, etc. by always generating a clock signal having the same frequency and phase as the regenerated clock in the clock generation means. It is possible to provide a recording and reproducing apparatus that can stably operate the system even if the system becomes abnormal until the system control means detects this and switches the settings.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a recording/reproducing device in a first embodiment of the present invention.

FIG. 2: Synchronization detection means 1 in the first embodiment of the present invention.
Block diagram showing a more detailed configuration of 3.

FIG. 3 is a block diagram showing a more detailed configuration of the system control means 15 in the first embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a recording/reproducing device in a second embodiment of the present invention.

[Fig. 5] Block diagram showing the configuration of a conventional recording/reproducing device

FIG. 6 is a block diagram showing a more detailed configuration of the synchronization detection means 43 in the conventional example.

FIG. 7 is a block diagram showing a more detailed configuration of the system control means 45 in the conventional example.

FIG. 8 is a flowchart showing the processing in the processing unit 26 in the conventional example shown in FIG. 7;

[Explanation of symbols]

11, 31 Demodulation means 12 Clock regeneration means 13 Synchronization detection means 14 Clock generation means 15, 35 System control means 16, 17, 18 Selector 21 Synchronization signal detection section 22 Control signal generation section 23 Synchronization judgment section 24 Setting section 25 Decoding section 26 Processing section 27 Unlock detection part

Claims (4)

[Claims] 1. Clock regeneration means for receiving an input digital signal and extracting a clock component; synchronization detection means for detecting that the output of the clock regeneration means is synchronized with the digital signal; demodulating means for demodulating the digital signal and extracting main information using the output of the reproducing means; clock generating means for generating a predetermined clock signal regardless of whether or not the digital signal is input; and input selection and system operation. system control means for setting modes and controlling the system accordingly; a selector for selecting the output of the demodulation means according to the output of the system control means; and the clock regeneration according to the output of the system control means. a selector for selecting an output of the means or an output of the clock generating means, the synchronization detecting means changing output of synchronization detection information according to operation mode information output from the system control means. playback device. 2. The system control means includes a selector for selecting the output of the demodulation means and an output of the clock regeneration means or the clock generation according to the output of the synchronization detection means irrespective of set input selection information. 2. The recording and reproducing apparatus according to claim 1, further comprising a selector for selecting an output of the means. 3. The demodulation means demodulates main information from the input digital signal and extracts information regarding the recovered clock, and the system control means controls the clock generation means according to the information regarding the recovered clock. 2. The recording/reproducing apparatus according to claim 1, wherein the recording/reproducing apparatus outputs a predetermined clock signal. 4. The clock generating means outputs a predetermined clock signal according to the information regarding the recovered clock outputted from the demodulating means, and also outputs the generated clock in phase with the recovered clock. 3
The recording and reproducing device described.