JPH04352432A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture the title device easily at low cost. CONSTITUTION:At the bottom of a semiconductor element chip are stacked a first metallic layer 2 of vanadium and a second metallic layer 3 of nickel, and further on the surface of the second metallic layer 3 is stacked a tin-gold- copper alloy layer 4, and by pressing this alloy layer 4 to a table 5, which is heated to a temperature higher than the melting point of the alloy layer 4, so as to fuse it, and then, cooling it so as to solidify it, the semiconductor element chip 1 is fixed to the table 5 by brazing material 6 consisting of tin- gold-copper alloy. Hereby, the quantity of used gold can be reduced without affecting the semiconductor element chip 1, and it can easily be manufactured at low cost.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element chip is fixed to a mounting base such as a lead frame, and a method for manufacturing the same.

0003

2. Description of the Related Art Conventionally, as a technique for fixing a semiconductor element chip to a mounting table such as a lead frame, for example, Japanese Patent Publication No. 59-2174 discloses a bonding structure using a gold-germanium alloy. This method involves forming multiple metal layers on the bottom surface of a semiconductor element chip, and then laminating a gold/germanium alloy layer on the surface of the outermost metal layer.
This is a technology that uses a germanium alloy layer as a brazing material when fixing a semiconductor element chip to the surface of a mounting table. However, in the above technology, the amount of germanium in the gold/germanium alloy layer that serves as the brazing material is as small as 12% by weight, and most of the remaining portion is gold, resulting in a large amount of gold being used.
This joining structure is very expensive.

On the other hand, as a bonding structure that does not use gold, a plurality of metal layers are formed on the bottom surface of a semiconductor element chip, and a tin-copper alloy is used as a brazing material on the bottom surface of these metal layers to fix it on a mounting table. Although there is technology, there are problems with low reliability, such as difficult processing control and easy contact and peeling. In other words, if the mounting temperature is kept constant, the molten state may change due to variations in the film quality or alloy ratio of the brazing material, which may weaken the adhesion strength and cause peeling. Adjusting and changing the mount temperature would cause a change in the reaction state of the brazing filler metal in areas other than the joint, which could cause peeling, change the resistance of the metal, and change the device characteristics.

[0005] Therefore, it can be easily manufactured under stable conditions at a temperature that does not affect the semiconductor element chip or the mounting table, etc., it is difficult to cause poor contact or peeling, and the manufacturing cost is low. is required to do so.

[0006]

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned situations in which manufacturing costs are high due to the use of large quantities of expensive materials, and processing control is difficult. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can be easily manufactured without affecting semiconductor element chips and the like, and which can be manufactured at low cost.

[Configuration of the invention]

[0008]

[Means for Solving the Problems] A semiconductor device and a method for manufacturing the same of the present invention provide a semiconductor device chip having one or more of titanium, chromium, zirconium, niobium, and vanadium deposited on the bottom surface thereof. A brazing filler metal made of a tin-gold-copper alloy is used to connect the first metal layer made of an alloy of It is characterized by being fixed to a mounting base, and the semiconductor element chip is made of a first material made of one of titanium, chromium, zirconium, niobium, vanadium or an alloy mainly composed of titanium, which is adhered to the bottom surface of the semiconductor element chip. a second metal layer made of either nickel or cobalt or an alloy containing these as a main component; and a third metal layer made of a gold-antimony alloy interposed between the first and second metal layers. It is characterized in that it is fixed to the mounting base with a brazing material made of tin, gold, and copper alloy through the metal layer of
It is characterized by being composed of an alloy consisting of 5 to 40% by weight of gold, 4 to 6% by weight of copper, and the balance being tin, and also has nickel and nickel on the bottom side of the semiconductor element chip. After a second metal layer made of cobalt or an alloy mainly composed of cobalt is formed, a tin-gold-copper alloy layer is formed on the surface of the second metal layer, and then heated. The semiconductor chip is fixed to the mounting base by pressing and melting an alloy layer on the surface,
Furthermore, a second layer made of nickel, cobalt, or an alloy mainly composed of nickel or cobalt is placed on the bottom side of the semiconductor element chip.
After layering the second metal layer, the surface of this second metal layer is coated with tin.
A method in which a tin/copper alloy layer containing copper is layered, a gold layer is layered on the surface of the tin/copper alloy layer with a metal layer having a lower melting point than the tin/copper alloy layer interposed therebetween, and then heated. This device is characterized in that a gold layer is pressed onto the surface of the table and the tin/copper alloy layer is melted to fix the semiconductor element chip to the mounting table.

[0009]

[Operation] In the semiconductor device and the manufacturing method thereof configured as described above, a first metal layer and a second metal layer are layered on the bottom surface of a semiconductor element chip, and a tin-gold-copper alloy layer is further layered. By pressing this alloy layer against a heated mounting table, melting and solidifying it, the semiconductor element chip is fixed to the mounting table using a brazing material made of a tin-gold-copper alloy. Alternatively, an alloy layer containing tin and copper, a metal layer with a lower melting point, and a gold layer are further layered on the metal layer formed on the bottom surface of the semiconductor element chip, and this gold layer is pressed against a heated mounting table. By melting the metal layer with a low melting point to make it a good heat conductor, and then melting and solidifying the alloy layer containing tin and copper, the semiconductor element chip is fixed to the mounting base using a brazing material made of tin, gold, and copper alloy. be done. This reduces the amount of gold used in the brazing filler metal,
Moreover, highly reliable fixing can be achieved without affecting the semiconductor element chip and without requiring difficult processing control.

0010

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, a first embodiment will be explained with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view before bonding, and FIG. 2 is a cross-sectional view after bonding. In the figure, 1 is a semiconductor element chip in which a predetermined semiconductor element, for example, an npn type transistor, is formed on a silicon substrate, and a first metal layer 2 made of vanadium (V) is formed on the lower surface of the semiconductor element chip 1. 0.0
It is laminated to a thickness of 6 to 0.08 μm. A second metal layer 3 made of nickel (Ni) is layered on the lower surface of the first metal layer 2 to a thickness of 0.2 to 0.3 μm. Further, on the lower surface of the second metal layer 3, there is a Sn/Au/Cu alloy layer 4 containing 35 to 40% by weight of gold (Au), 4 to 6% by weight of copper (Cu), and the remainder being tin (Sn). are layered to a thickness of 1.5 to 3.0 μm. Note that 5 is a stand for arranging a Cu lead frame and the like. The semiconductor element chip 1 is Sn
- The Au/Cu alloy layer 4 is fixed to the installation stand 5 using the brazing material 6. 6a is Sn/Au/Cu alloy brazing material 6
This is a reaction layer between the base plate 5 and the mounting table 5.

Further, the above structure is manufactured as follows. First, a first metal layer 2 of 0.06 to 0.08 μm is coated on the lower surface of the wafer before it is divided into semiconductor element chips 1.
m, and then a second metal layer 2 is deposited on the surface of the first metal layer 2.
A metal layer 3 is deposited to a thickness of 0.2 to 0.3 μm, and a Sn/Au/Cu alloy layer 4 is further deposited to a thickness of 1.5 to 3.0 μm on the surface of the second metal layer 3. to adhere to. Each of the above depositions is performed by sputtering or vacuum evaporation. Subsequently, the first metal layer 2, the second metal layer 3 and Sn/Au/Cu
A wafer having an alloy layer 4 deposited on its bottom surface is divided into semiconductor element chips 1. Then, by pressing the Sn/Au/Cu alloy layer 4 of the divided semiconductor element chip 1 onto a predetermined position of the mounting table 5 which has been heated to 370° C. or higher in advance, the Sn/Au/Cu alloy layer 4 is pressed. Melt 4. Then, the melted Sn-Au-Cu alloy layer 4 is solidified by starting cooling within a time that does not affect the characteristics of the semiconductor element chip 1 while keeping the position of the semiconductor element chip 1 unchanged. As a result, the semiconductor element chip 1 is made of Sn, Au, C.
It is fixed onto the installation table 5 with a brazing filler metal 6 made of U alloy. The first metal layer 2 of V serves as an adhesive layer between the semiconductor element chip 1 and the second metal layer 3 of Ni, and the second metal layer 3 of Ni serves as a bonding layer between the semiconductor element chip 1 and the second metal layer 3 of Ni. It acts as a protective layer.

According to the first embodiment formed in this way, the Sn-Au-Cu alloy layer 4 has a melting point in the range of 300 to 350°C, and the mounting table 5 is heated to 370°C or higher in advance. By keeping the Sn/Au/Cu alloy layer 4 in a stable molten state, it can be easily reacted with the Cu mounting base 5 to form the Sn/Au/Cu alloy as the brazing material 6. It is possible to achieve highly reliable adhesion that does not cause peeling, without affecting the characteristics of the semiconductor element chip 1, and without requiring difficult processing control. Further, since the brazing material 6 is not mainly made of gold but is made of a Sn-Au-Cu alloy, the amount of gold used is small and the product is inexpensive, resulting in low manufacturing costs.

Next, a second embodiment will be explained with reference to FIGS. 3 to 5. FIG. 3 is a cross-sectional view before bonding, FIG. 4 is a cross-sectional view after bonding, and FIG. 5 is a distribution diagram. In the figure, a first metal layer 2 made of V and having a thickness of 0.06 to 0.08 μm is layered on the lower surface of a semiconductor element chip 1 on which a predetermined semiconductor element is formed, as in the first embodiment. There is. On the lower surface of the first metal layer 2 is a third metal layer 7 containing 50% by weight each of Au and antimony (Sb) and having a thickness of 0.12 to 0.18 μm.
are stratified. The lower surface of the third metal layer 7 has N
A second metal layer 8 having a thickness of 0.45 to 0.55 μm is layered. Further, on the lower surface of the second metal layer 3, there is a Sn/Au/Cu alloy layer 4 containing 35 to 40% by weight of Au, 4 to 6% by weight of Cu, and the balance of Sn.
It is layered to a thickness of 0 μm. Similarly to the first embodiment, the semiconductor element chip 1 is fixed to the mounting table 5 using the Sn.Au.Cu alloy layer 4 as the brazing material 6. Furthermore, 7a
is silicon (Si) on the bottom surface of the semiconductor element chip 1 and A
Si formed by reacting with the third metal layer 7 of u・Sb
・It is an alloy of Au and Sb.

Further, the above structure is manufactured in the following manner in the same manner as in the first embodiment. First, the first metal layer 2 is deposited to a thickness of 0.06 to 0.08 μm on the lower surface of the wafer before it is divided into semiconductor element chips 1, and then the surface of the first metal layer 2 is coated. The third metal layer 7 is 0.12 to 0.18
A second metal layer 7 is deposited on the surface of the third metal layer 7 to a thickness of μm.
a metal layer 8 of 0.45 to 0.55 μm thick,
Furthermore, a Sn-Au-Cu alloy layer 4 is deposited on the surface of the second metal layer 8 to a thickness of 1.5 to 3.0 μm. Each of the above depositions is performed by sputtering or vacuum evaporation. Subsequently, first, third, second metal layers 2, 7, 8 and Sn.A
A wafer having a u/Cu alloy layer 4 deposited on the bottom surface is divided into semiconductor element chips 1. Then, by pressing the Sn/Au/Cu alloy layer 4 of the divided semiconductor element chip 1 onto a predetermined position of the mounting table 5 which has been heated to 370° C. or higher in advance, the Sn/Au/Cu alloy layer 4 is pressed. Melt 4. Then, the melted Sn-Au-Cu alloy layer 4 is solidified by starting cooling within a time that does not affect the characteristics of the semiconductor element chip 1 while keeping the position of the semiconductor element chip 1 unchanged. As a result, the semiconductor element chip 1 becomes Sn.
It is fixed onto the installation table 5 by a brazing material 6 made of Au/Cu alloy.

Furthermore, in the process of melting, cooling and solidifying the Sn/Au/Cu alloy layer 4, the third metal layer 7 begins to melt at 360°C, and a part of the extremely thin first metal layer 2 is melted. Reacts with Si on the more exposed bottom surface of the semiconductor element chip 1 to form Si.
- An alloy 7a of Au and Sb is formed. That is, A
The eutectic temperature of u・Sb alloy is 360℃ and Au・Si
By utilizing the eutectic temperature of the alloy, 370°C, Si.
A ternary alloy of Au and Sb is formed. As shown in the distribution diagram of FIG. 3, the collector-emitter saturation voltage (VCEsat) of the npn type transistor formed in the semiconductor element chip 1 is such that the collector current (IC) and base current (IB) are respectively IC = 100mA, I
When B = 10mA, the conventional one has about 140mV
However, in the invention of this example, the length was about 120 m.
It was as low as V.

According to the second embodiment formed in this manner, the same functions and effects as those of the first embodiment described above can be obtained, and when the semiconductor element chip 1 is firmly bonded to the mounting base 5, Si/Au is formed on the bottom surface of the semiconductor element chip 1 by heating.
- An alloy of Sb is formed, which reduces contact resistance, provides good ohmic properties, and improves electrical properties.

Next, a third embodiment will be explained with reference to FIGS. 6 and 7. FIG. 6 is a sectional view before joining, and FIG. 7 is a sectional view after joining. In the figure, the lower surface of a semiconductor element chip 1 on which a predetermined semiconductor element is formed has a VV with a thickness of 0.07 μm.
A first metal layer 9 consisting of is laminated. On the lower surface of the first metal layer 9, a third metal layer 10 containing 50% by weight each of Au and Sb and having a thickness of 0.18 μm is laminated. A second metal layer 11 made of Ni and having a thickness of 0.5 μm is layered on the lower surface of the third metal layer 10. Further, on the lower surface of the second metal layer 11, a Sn/Cu alloy layer 12 containing 6% by weight of Cu and the remainder Sn is laminated to a thickness of 1.3 μm. Furthermore, an Sn layer 13 with a thickness of 0.2 μm is layered on the lower surface of the Sn/Cu alloy layer 12, and an Au layer 14 with a thickness of 0.3 μm is further layered on the lower surface of the Sn layer 13. Then, the Sn/Cu alloy layer 12 and the Sn layer 13 are melted, the Au layer 14 is diffused, and a brazing material 15 is formed, thereby fixing the semiconductor element chip 1 to the mounting table 5.

Further, the above structure is manufactured in the following manner in the same manner as in each of the above embodiments. First, semiconductor element chip 1
A first metal layer 9 is placed on the bottom surface of the wafer before it is divided into
to a thickness of 0.07 μm, followed by a first metal layer 9
A third metal layer 10 is deposited on the surface of the third metal layer 10 to a thickness of 0.18 μm, a second metal layer 11 is deposited on the surface of the third metal layer 10 to a thickness of 0.5 μm, and A Sn/Cu alloy layer 12 is deposited on the surface of the second metal layer 11 to a thickness of 1.3 μm. Furthermore, a Sn layer 13 is deposited on the surface of the Sn/Cu alloy layer 12 to a thickness of 0.2 μm, and an Au layer 14 is deposited on the surface of the Sn layer 13 to a thickness of 0.3 μm. Each of the above depositions is performed by sputtering or vacuum evaporation. Subsequently, the wafer, on which the first, third, and second metal layers 9, 10, and 11, the Sn/Cu alloy layer 12, the Sn layer 13, and the Au layer 14 are deposited on the bottom surface, is divided into semiconductor element chips 1. . Then, the installation table 5 was heated to 400±10°C in advance.
The Au of the divided semiconductor element chip 1 is placed at a predetermined position of
The Sn layer 13 is first melted, for example by heating for 0.4 seconds while pressing the layer 14, and then the Sn
- Melt the Cu alloy layer 12. Then, the Sn layer 13 is melted without changing the position of the semiconductor element chip 1.
Then, the Sn/Cu alloy layer 12 is cooled and solidified. As a result, the semiconductor element chip 1 is fixed onto the mounting table 5 by the brazing material 15 made of a Sn.Au.Cu alloy in which Au is diffused into the Sn.Cu alloy. Note that 9a is an alloy of Si, Au, and Sb formed by the reaction between Si on the bottom surface of the semiconductor element chip 1 and the third metal layer 9 of Au and Sb;
is a reaction layer between the Sn/Au/Cu alloy brazing filler metal 15 and the mounting table 5.

[0020] The Sn layer 13 and the Sn/Cu alloy layer 12
In the process of melting, diffusing and cooling the Au layer, the Sn/Cu alloy layer 1 is in an initial state with poor thermal conductivity.
The Sn layer 13, which has a lower melting point than that of 2, is melted first, and in a state where the heat conduction is improved by melting, the Sn/Cu alloy layer 12 is melted.
is subsequently melted. This provides a stable process from melting to solidification. Therefore, the semiconductor element chip 1
In the present embodiment, the occurrence of defects such as sticking to the mounting table 5, which conventionally had a failure rate of 0.5% or more, no longer occurs. Further, as in the second embodiment, an alloy of Si, Au, and Sb is formed on the semiconductor element chip 1 by the third metal layer 10, and between the collector and emitter of the npn type transistor formed on the semiconductor element chip 1. Saturation voltage (VCEsa
t) was lower in this example than in the conventional one.

As described above, the third embodiment also provides the same functions and effects as the second embodiment described above.

In each of the above embodiments, V is used as the first metal layers 2, 9, and V is used as the second metal layers 3, 8, 11.
Although the case where Ni was used as the
Similar effects can be obtained when Ti, Cr, Zr, Nb, or an alloy thereof is used as the first metal layer, and when Co or an alloy thereof is used as the second metal layer. In the lower surface of the second metal layer 11, Sn.
Although the Cu alloy layer 12 is provided, it may also be a Sn/Cu/Au alloy layer, or an upper layer of Sn/C may be used instead of the Sn layer 13.
The present invention can be practiced with appropriate modifications within the scope of the gist, such as a metal layer having a lower melting point than the alloy layer containing u.

[0023]

[Effects of the Invention] As is clear from the above description, the present invention is a method of melting and solidifying a tin-gold-copper alloy layer formed on the bottom side of a semiconductor element chip by pressing it against a heated mounting table. The semiconductor element chip is fixed to the mounting base using a brazing filler metal made of tin, gold, and copper alloy, or an alloy layer containing tin and copper layered on the bottom side of the semiconductor element chip and a metal layer with a lower melting point than this are layered on the bottom side of the semiconductor element chip. The metal layer with a low melting point is melted, and the alloy layer containing tin and copper is melted and solidified by pressing the gold layer onto a heated mounting table, thereby forming a semiconductor chip using a brazing material made of tin, gold, and copper alloy. By having a configuration in which the device is fixed to the mounting table, it is possible to easily manufacture the device at a low manufacturing cost without affecting the semiconductor element chip or the like.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view before bonding according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view after bonding according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view before bonding according to a second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view after bonding according to a second embodiment of the present invention.

FIG. 5 is a distribution diagram of collector-emitter saturation voltage of an npn transistor.

FIG. 6 is a schematic cross-sectional view before bonding according to a third embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view after bonding according to a third embodiment of the present invention.

[Explanation of symbols]

1...Semiconductor element chip 2...First metal layer 3...Second metal layer 4...Tin/gold/copper alloy layer 5…Arrangement stand 6...Brazing material

Claims (5)

[Claims] Claim 1: A semiconductor element chip has a first metal layer made of one of titanium, chromium, zirconium, niobium, and vanadium or an alloy mainly composed of titanium, chromium, zirconium, niobium, and vanadium, and nickel and cobalt. 1. A semiconductor device, characterized in that it is fixed to a mounting table with a brazing filler metal made of a tin-gold-copper alloy via a second metal layer made of one of these or an alloy containing the same as a main component. 2. A semiconductor element chip has a first metal layer made of one of titanium, chromium, zirconium, niobium, and vanadium or an alloy mainly composed of titanium, chromium, zirconium, niobium, and vanadium, and nickel and cobalt. A second metal layer made of one of these or an alloy containing the same as a main component;
It is fixed to the installation base with a brazing material made of tin, gold, and copper alloy through a third metal layer made of gold and antimony alloy interposed between the first and second metal layers. A semiconductor device characterized by: [Claim 3] The brazing filler metal is 35 to 40% by weight of gold, and 4
3. The semiconductor device according to claim 1, wherein the semiconductor device is made of an alloy containing up to 6% by weight of copper and the remainder tin. 4. After layering a second metal layer made of nickel, cobalt, or an alloy mainly composed of nickel or cobalt on the bottom side of the semiconductor element chip, tin or gold is deposited on the surface of the second metal layer. - A method for manufacturing a semiconductor device, characterized in that a copper alloy layer is laminated, and then the alloy layer is pressed onto the surface of a heated mounting table and melted, thereby fixing the semiconductor chip to the mounting table. 5. After layering a second metal layer made of either nickel or cobalt or an alloy mainly composed of nickel or cobalt on the bottom side of the semiconductor element chip, tin or copper is deposited on the surface of this second metal layer. A metal layer having a melting point lower than that of the tin-copper alloy layer is interposed on the surface of the tin-copper alloy layer, and a gold layer is deposited on the surface of the tin-copper alloy layer, and then heated. A method of manufacturing a semiconductor device, characterized in that the semiconductor element chip is fixed to the mounting table by pressing the gold layer onto the surface and melting the tin-copper alloy layer.