JPH04352416A - Reference mark for detecting position for electron beam and manufacture of field-effect transistor using said mark - Google Patents

Abstract

PURPOSE:To provide a position detecting reference mark for electron beams capable of facilitating a lift-off after the exposure to electron beams. CONSTITUTION:A position detecting reference mark 4 for electron beams is formed at a position to be exposed to electron beams on a semiconductor substrate. When the position detecting reference mark 4 for electron beams is used for preparing an FET, a process, in which a source electrode 1, a drain electrode 2 and the position detecting reference mark 4 for electron beams are formed simultaneously onto the semiconductor substrate, a process, in which an electron beam resist is formed from the whole surface, and a process, in which a section corresponding to the gate electrode 3 is exposed to electron beams on the basis of the position detecting reference mark 4 for electron beams, are included, and the position detecting reference mark 4 for electron beams is formed in the pad section 6 of the gate electrode 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam position detection reference mark used in electron beam exposure and a method of manufacturing a field effect transistor using the same.

0002

[Prior Art] Conventionally, field effect transistors (hereinafter referred to as F
It's called ET. ) When electron beam exposure is used to create the gate electrode, the electron beam position detection reference mark 12 is formed using the process of forming the source electrode 10 and drain electrode 11 of the FET, as shown in FIG. Ta.

Further, electron beam exposure of the electron beam resist for forming the gate electrode 13 by lift-off is performed from two directions A and B including the electron beam position detection reference mark 12.

[0004] Usually, the electron beam position detection reference mark 12 is placed very close to the FET so as to minimize the chip area. In the example of FIG. 3, it is installed on the left side of the drain electrode 11 in the drawing.

[0005]

[Problem to be solved by the invention] In the above-mentioned prior art,
Since the electron beam position detection reference mark 12 is located outside the FET, even if the electron beam position detection reference mark 12 is installed very close to the FET to minimize the chip area, the chip area of the FET will increase. is unavoidable.

Furthermore, since the electron beam resist on the electron beam position detection reference mark 12 is also exposed to the electron beam, when a gate electrode metal is vapor-deposited and lift-off is performed after the electron beam exposure, the electron beam position is The gate electrode metal remains on the detection reference mark 12 as well. Therefore, in some cases, the gate electrode metal on the electron beam position detection reference mark 12 may come into contact with the drain electrode 11, which may adversely affect the high frequency characteristics of the completed FET.

Furthermore, an electron beam position detection reference mark 12
It is necessary to lift off the portion of the gate electrode metal at the same time as the gate electrode portion, and the lift-off process for the electron beam position detection reference mark 12 portion is more difficult and less reproducible than the lift-off for the gate electrode portion.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electron beam position detection reference mark that can facilitate lift-off after electron beam exposure.

Another object of the present invention is to reduce the chip area of an FET in which a gate electrode is formed by electron beam exposure using an electron beam position detection reference mark, and to avoid adversely affecting the high frequency characteristics of the FET. do.

0010

[Means for Solving the Problems] The present invention provides an electron beam position detection reference mark formed on a semiconductor substrate and used during electron beam exposure, the mark being located at a position on the semiconductor substrate to be exposed to the electron beam. This is an electron beam position detection reference mark characterized by being formed.

The present invention also provides a step of simultaneously forming a source electrode, a drain electrode, and an electron beam position detection reference mark on a semiconductor substrate, a step of forming an electron beam resist on the entire surface, and a step of forming an electron beam resist on the entire surface of the semiconductor substrate. and exposing a portion corresponding to the gate electrode to an electron beam based on the position detection reference mark, the electron beam position detection reference mark being formed within a pad portion of the gate electrode. This is a method of manufacturing a field effect transistor using a position detection reference mark.

0012

[Operation] According to the present invention, since the electron beam position detection reference mark is formed at the position exposed to the electron beam, in the lift-off process performed after the electron beam exposure, the metal film is formed as the electron beam position detection reference mark. It will completely cover the mark.

[0013]

[Embodiment] FIG. 1 shows an FET showing a first embodiment of the present invention.
FIG.

In the figure, 1 is a source electrode, 2 is a drain electrode, 3 is a gate electrode, and 4 is an electron beam position detection reference mark. These are formed on a semiconductor substrate. Further, the gate electrode is composed of a gate electrode portion 5 and a pad portion 6.

A method of manufacturing this FET will be explained below.

First, a positive photoresist (LMR) is formed to a thickness of 2 μm over the entire surface of a semiconductor substrate, and the source electrode 1, drain electrode 2, and electron beam position detection reference mark 4 are exposed to deep ultraviolet rays. After development, a metal film made of AuGe is formed on the entire surface of the semiconductor substrate, and lift-off is performed with acetone to form a source electrode 1, a drain electrode 2, and an electron beam position detection reference mark 4. The electron beam position detection reference mark 4 is installed within a pad portion 6 of the gate electrode 3 that will be formed later.

Next, an electron beam resist (
PMMA) is formed to a thickness of about 8000 Å, and a portion corresponding to the gate electrode 3 is exposed to electron beam. This electron beam exposure is performed after the position of the electron beam position detection reference mark 4 is detected. That is, before exposing the gate electrode portion 5 and the pad portion 6 to electron beam (scanning with the electron beam), the electron beam position detection reference mark 4 is scanned with the electron beam in the A direction (main scanning) and the B direction (
The position of the electron beam position detection reference mark 4 is detected by exposing the electron beam to electron beam during the sub-scanning and detecting the electron beam reflected from the electron beam position detection reference mark 4. Thereafter, based on this detection result, that is, a portion corresponding to the gate electrode 3 is exposed to electron beam at a predetermined position from the electron beam position detection reference mark 4.

Next, the electron beam resist is coated with a developer (MIBK
(stirred for 120 seconds at 25°C).

Note that the exposure conditions include the scanning distance of the electron beam (
The distance in the A direction) is approximately 30 μm, the acceleration voltage is 25 kV, the beam current is 500 pA, the line dose of the gate electrode portion 5 is 4 nC/cm, and the surface dose of the pad portion 6 is 70 mC.
/cm2. In addition, position detection reference mark 4 for electron beam
was in the shape of a cross, with a width of 5 μm and a length of 40 μm.

In the case of the first embodiment, the scanning distance of the electron beam (
Since the distance in the A direction) was set to about 30 μm and the length of the electron beam position detection reference mark 4 was set to 40 μm, the pad portion 6 is not exposed to light during position detection.

As described above, since the electron beam exposure of the portion corresponding to the gate electrode 3 is performed after the position of the electron beam position detection reference mark 4 has been detected, the exposure of the pad portion 6 is performed using the electron beam position detection reference mark 4. This will include the area above mark 4. Therefore, after development, the electron beam resist on the pad portion 6 is completely melted, and the electron beam position detection reference mark 4 is exposed.

Next, Ti/Al (Ti
= 50 Å/Al = 5500 Å), lift-off with acetone is performed, and gate electrode portion 5 is formed.
and a gate electrode 3 constituted by the pad portion 6. This lift-off does not need to be performed on the electron beam position detection reference mark 4 portion, and since the electron beam position detection reference mark 4 is formed within the pad portion 6, lift-off for forming the gate electrode 3 can be easily performed. It can be carried out.

FIG. 2 shows an FE showing a second embodiment of the present invention.
It is a top view of T.

In the first embodiment, the electron beam position detection reference mark was simply placed on the pad of the gate electrode of the prior art FET shown in FIG. 3, and the size of each electrode was not changed. 1 is the lateral width of the drain electrode 2 (
The second embodiment shown in FIG. 2 focuses on the fact that the ohmic characteristics are sufficient even if the gate electrode direction is made to match the direction of the gate electrode.

In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted. In addition, the manufacturing process etc.
This is the same as the embodiment.

As is clear from FIG. 2, the difference from FIG. 1 is that the width of the source electrode 1 is made to match the width of the drain electrode 2 in the lateral direction.

For example, if the chip size in FIG. 1 is 340 μm long×440 μm wide, the chip size in FIG. 2 is approximately 340 μm long×340 μm wide. Due to this reduction in chip size, the number of chips that can be made from the same wafer (for example, a 3-inch wafer) is approximately 1.3.
It will be doubled.

Although each of the above embodiments has been explained using an FET as an example, it is also applicable to other semiconductor devices. That is, the present invention can be applied to a semiconductor device in which it is necessary to form an electron beam position detection reference mark before electron beam exposure.

[0029]

As is clear from the above description, by using the electron beam position detection reference mark of the present invention during electron beam exposure, lift-off after electron beam exposure is facilitated.

Furthermore, by using the electron beam position detection reference mark of the present invention in fabricating an FET, lift-off of the gate electrode becomes easy and the chip area can also be reduced.

[Brief explanation of drawings]

FIG. 1 is a top view of a FET according to a first embodiment of the present invention.

FIG. 2 is a top view of a FET according to a second embodiment of the present invention.

FIG. 3 is a top view of a conventional FET.

[Explanation of symbols]

1 Source electrode 2 Drain electrode 3 Gate electrode 4 Position detection reference mark for electron beam 5
Gate electrode part 6 Pad part

Claims (2)

[Claims] 1. An electron beam position detection reference mark formed on a semiconductor substrate and used during electron beam exposure, characterized in that it is formed at a position on the semiconductor substrate to be exposed to the electron beam. Position detection reference mark for electron beam. 2. A step of simultaneously forming a source electrode, a drain electrode, and an electron beam position detection reference mark on a semiconductor substrate, a step of forming an electron beam resist from the entire surface, and the step of forming the electron beam position detection reference mark. and exposing a portion corresponding to the gate electrode to an electron beam based on the method, wherein the electron beam position detection reference mark is formed within a pad portion of the gate electrode. A method for manufacturing field effect transistors using marks.