JPH04352244A - Control circuit for electronic device - Google Patents

Abstract

PURPOSE:To improve the efficiency of debugging operation by generating a trap flag at the time of program debugging similarly to an interrupt flag after all steps of an instruction processing program in a microprogram memory end. CONSTITUTION:An address arithmetic output is inputted to flag generation 6a and it is checked whether or not the output is a use inhibition address; when so, a trap signal is generated and inputted to an F/F 6b. A clock generated in each step of the memory 7 is inputted to the 0 terminal of a multiplexer 6c and an input terminal of an AND circuit 6d. Gate control data which is written in the 1st field of the memory 7 is inputted to the other input terminal and the output of a circuit 6d is inputted to the 1st terminal of an MUX. Data written in the 2nd field of the memory 7 is inputted to the select terminal of the MUX. The output of the MUX is supplied to the F/F 6b, whose output is used as a flag.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for an electronic device such as a semiconductor testing device, and more particularly to an improvement in a trap flag setting method.

0002

2. Description of the Related Art [1] First, the flow of execution of a system program set on the main memory 1 will be explained with reference to FIGS. 3 to 5. (1) The explanation starts from the point where the memory address calculation unit 5 outputs 100 as the address value.

(2) The content "SUB" of main memory address 100 is output as read data of main memory 1 and taken into instruction register 2. (3) The output of the instruction register 2 fetched in (2) is input to the instruction decoder 3. The address of the microprogram memory 7 is output as the output of the instruction decoder 3.

(4) Instruction degouter 3
The output of is connected to the 0 side input terminal of the multiplexer 4, and the 0 side of this multiplexer 4 is normally selected. Therefore, multiplexer 4 outputs address 0 of the macro program memory, which in this example implements "SUB". (5) At address 0 of the microprogram memory, “
A control code for controlling each piece of hardware is written in order to implement the "SUB" instruction. A part of this control code is passed to the memory address calculation unit 5.

(6) The memory address calculation unit 5 performs (5
) The size information 2 of the instruction of "SUB" itself among the instructions of "SUB" which is the contents of the instruction register 2 fetched in (2) is added to the main memory address value 100 currently pointed to by the control code passed in (2). , and outputs the value 102.

(7) As a result of (6), the output of the memory address calculation unit 5 is 102, and the read data of the main memory 1 is the content of the 102nd value. This is an “ADD” instruction. (8) From then on, (2) to (7) are repeated to execute the instructions on the main memory 1. [2] Next, the flow of operations when the trap flag is raised from the trap flag generating section 6 will be explained.

(1) Normally, the 0 side is selected as the output of the multiplexer 4, so it is the address of the microprogram memory 7 obtained by decoding the instruction, but when the trap flag is raised from the trap flag generator 6, this The flag selects the 1 side of the multiplexer 4, and the output of the multiplexer 4 becomes 200.

(2) Therefore, the address of the microprogram memory 7 is 200, and the program related to the trap processing written in the microprogram memory 7 is executed from address 200. The flow of execution by this program will be explained below. (2-1) As a control code passed from the microprogram memory 7 to the memory address calculation unit 5, a code that causes the memory address calculation unit 5 to output 0 is passed, and the output of the memory address calculation unit 5 becomes 0. .

(2-2) A value 60 indicating the optical head address of program A is written at address 0 of the main memory 1, and this value 60 is taken into the memory read data register 10 as memory read data. . (2-3) The value 60 fetched in (2-2) is passed to the memory address calculation unit 5, and the output of the memory address calculation unit 5 becomes 60.

(2-4) The value of the main memory address becomes 60, and the program A written in the main memory 1, ie, the trap processing program, is executed from address 60 of the main memory 1. The program written on the main memory 1 is executed according to the flow described in [1].

(3) When program A on main memory 1 is executed, for example, the instruction "abc" written in program A is executed along the flow of [1]. Therefore, the instruction “a”
The processing program for the instruction "abc" on the microprogram memory 1 that implements "bc" is executed.As a result, the control code is passed from the microprogram memory 7 to the CRTi/F8, and the CRT
The i/F (CRT interface) 8 outputs characters to the CRT 9. The system user can see the characters (message) output on the CRT and know that a trap has occurred. [3] Up until now, we have explained using traps as an example, but now we will explain the difference between traps and interrupts.

[0012] Normally, traps are made to be accepted at any time for the purpose of prompt response. That is, each step of the microprogram on the microprogram memory 7 is accepted. The problem in this case is that another processing program is executed by a trap in the middle of a multi-step microprogram that describes the movement of one instruction, so after the execution of this other processing program is finished, the previous microprogram is executed again. Even if you try to restart the program, it cannot be restarted because no information remains.

On the other hand, in consideration of restarting an interrupted program, interrupts are accepted only at the end of each instruction, that is, at the end of a multi-step microprogram that describes the movement of each instruction. . For example, instruction A
If a microprogram is written in five steps (■ to ■), the multiplexer 4 accepts traps in all steps (■ to ■) and interrupts only in step (■). "Accept" means that the multiplexer 4 outputs the address of the microprogram memory 7 corresponding to the trap/interrupt/general instruction.

When the interrupt flag goes up, the flow of operation is the same except for the timing of acceptance, and the interrupt flag selects the 2 side of the multiplexer 4.
Thereafter, the interrupt processing program in the main memory 1 is executed through the same operations as in the trap. Normal time/
The timing when a trap flag is generated/an interrupt flag is generated will be briefly explained with reference to FIG.

Normally, as shown in FIG. 6A, after all three steps of "SUB" are completed, the next step (2) of "ADD" begins. When the trap flag goes up, in the middle of "SUB", Figure 6B
In the example, the ■ step of trap processing starts immediately after the ■ step. In the case of an interrupt, even if the interrupt flag goes up at the same time as the trap flag, step (2) of the interrupt processing starts after all steps (2) to (2) of "SUB" are completed, as shown in FIG. 6C.

As shown in FIG. 7, the conventional trap flag generating section 6 inputs read data from the main memory 1 to a trap flag generating circuit 6a, and outputs the output, that is, a trap signal, to a flip-flop circuit (hereinafter referred to as F/F). say) 6b
Supplied to the data input terminal of The trap flag generating circuit 6a is, for example, a parity check circuit, and immediately generates a trap signal upon detecting a parity error. F/
F6b is the clock terminal C when the trap signal c is input.
The polarity of the Q output is inverted from L (low level) to H (high level) in synchronization with clock b of K (b in Figure B; generated at each step of the microprogram in Figure 7Ba), and the trap flag is activated. d (FIG. 7Bd) is generated and supplied to the select signal generator 10.

[0017]

[Problem to be Solved by the Invention] When a trap flag is raised during debugging of a system program written to the main memory 1, multiple instructions that describe the processing of the instructions written to the main memory 1 are detected as described above. A trap processing program is executed in the middle of a step microprogram. However, after the trap processing program has finished executing, even if an attempt is made to restart the previously interrupted microprogram, it cannot be restarted because no information remains. After determining the cause of the trap and correcting the program or hardware, the instructions must be restarted from the beginning. When debugging a program, trap plugs are raised much more frequently than during normal operation (when the system is running), and there is little need to urgently run a trap processing program, so such interruptions are extremely inconvenient. . An object of the present invention is to improve the trap flag generating unit 6, etc. so that during debugging, the trap flag is raised after all steps of the microprogram that describes the processing of instructions are raised, just like interrupts, and after the trap processing program is executed. The aim is to facilitate the restart of the main program and improve the efficiency of program debugging.

[0018]

[Means for solving the problem] (1) Main memory,
A microprogram memory that stores processing programs for each instruction of the system program, trap processing program, and interrupt processing program written in the main memory, and a microprogram memory that stores processing programs for each instruction of the system program, trap processing program, and interrupt processing program written in the main memory; An instruction register that sequentially stores read data, an instruction decoder that decodes the output of the instruction register and outputs an address on the microprogram memory of a processing program for each instruction of the system program, and an address input from the instruction decoder. and the addresses on the microprogram memory of each instruction of the trap processing program and the interrupt processing program that are input separately, and calculate the multiplexer to supply the microprogram memory and the address of the main memory. a memory address calculation unit that supplies the main memory with the
a trap flag generating section; an interrupt flag generating section; generating corresponding select signals at predetermined timings when the trap flag is input, when the interrupt flag is input, and at other times, and supplying them to the multiplexer; In the control circuit for an electronic device, the control circuit includes a select signal generator that inputs the output of the memory address calculation unit to the trap flag generation unit to check whether the address is a prohibited address; a trap signal generation circuit that generates a trap signal when the address is a prohibited address; a clock that generates for each address of each row (each step) of the microprogram memory; and each step other than the final step of the instruction processing program and the final step. a logical 0 and a logical 1 respectively written to the common first field of
An AND gate is provided to obtain a logical sum with the read data.

Further, read data of mode data (logic 1 in debug mode, logic 0 in normal mode) written in a common second field of each step of a predetermined instruction processing program in the microprogram memory is read. When the output of the AND gate is applied to the select terminal, the output of the multiplexer that selects the clock in the normal mode, and the output of the trap signal generation circuit are input to the data terminal, the output of the AND gate is input to the clock terminal. A flip-flop circuit is provided that generates a trap flag by inverting the polarity of the output in synchronization with the output of the multiplexer, and supplies the trap flag to the select signal generator.

(2) A trap flag generating section consisting of a flip-flop circuit is provided as a part of the trap flag generating section in item (1) above, and a trap flag generating section is provided which writes to a common field of each row corresponding to each address of the microprogram memory. The read data of the input trap signal (writes a logic 0 to the row of used addresses and a logic 1 to the row of unused addresses) is supplied to the data input terminal of the flip-flop circuit, and the read data of the trap signal (writes a logic 0 to the row of used addresses and a logic 1 to the row of unused addresses) is supplied to the data input terminal of the flip-flop circuit, and the address of each row of the microprogram memory is A clock signal generated at each step (each step) may be input to the clock terminal of the flip-flop circuit, and the output of the flip-flop circuit may be supplied to the select signal generator as a trap flag.

[0021]

[Embodiment] As shown in FIG. 1, by preparing a clock that can be controlled by the control code output from the microprogram memory 7 as the clock e for setting the trap signal c, it is possible to use the trap like an interrupt. Become. (a) The case where the normal mode trap signal generation circuit 6a is a main memory address monitoring circuit will be described as an example. The main memory address monitoring circuit monitors the address data passed from the memory address calculation unit 5 to the main memory 1 in FIG. 3, compares it with a comparison address given in advance, and immediately raises a trap signal when a match is detected. This is usually done by setting a range in the main memory 1 that is allowed to be accessed to prevent the program from running out of control.

Next, the flow of operation will be explained. Assuming that 300 is given to the main memory address monitoring circuit 6a as a pre-given comparison address and the accessible range is up to address 299, the output of the memory address calculation unit 5 starts from 100 as explained in the conventional technique. 106, "ST3, label 1" (
This instruction writes the contents of register 3 to label address 1 on main memory 1. ), if label 1, which is the write target address, is address 300 due to a program error, the output of the memory address calculation unit 5 becomes 300, and the main memory address monitoring circuit 6a outputs the pre-given 300. By comparing the two and detecting that the access prohibited area is being accessed based on a match, outputting the trap signal c, and outputting the trap flag d from the F/F 6b at the timing of the clock b, the instruction of "ST" Execution is interrupted midway, and writing of data to address 300 of main memory 1 is not executed, so that the contents of address 300 of main memory are not destroyed. Therefore, if field 2 of the microprogram memory 7 in FIG. 1 is described as a normal mode with all 0s, the select signal input of the multiplexer 6c to which the output of field 2 is connected becomes 0, that is, each step of the microprogram. The clock b that appears every time is selected. As a result, the trap flag is raised during the execution of the "ST" instruction, and the execution of the "ST" instruction is interrupted. (b) Debugging mode Next, when you want to execute the remaining microprogram processing that was interrupted and actually write data to address 300 of main memory 1, and check what value you were trying to write during debugging, As a debug mode, 1 is written in field 2 of the microprogram memory 7, and the selection of the multiplexer 6c is set to the 1 side. Then, since the clock b is gated by the AND circuit 6d, the microprogram memory 7 that controls this gate
It can be controlled by field 1 of In other words, by writing 1 in field 1 of step ■ at the end of the microprogram where the trap flag can be raised, in this case the "ST" instruction is written, the trap flag will only be raised during step ■. . Therefore, all steps of the "ST" instruction can be executed. Embodiment Corresponding to Claim 2 As shown in FIG. 2, by connecting the output of the microprogram memory 7 to the input of the trap flag generating section 6, it is possible to raise the trap flag programmably by the microprogram. By doing this, for example, if 1 is written in only the empty area in field 1 (1 bit) connected to the F/F 6b of the trap flag generation unit 6 as a trap signal from the microprogram memory 7, the program The microprogram memory 7 has gone out of control and is never accessed during normal operation.
When the address is accessed, the trap flag d is raised and an abnormality can be detected at the first stage of runaway.

Next, the flow of operation will be explained. When the programs SUB, ST, and ADD are sequentially written in the main memory 1, the addresses of the microprogram 7 are 100, 101, 102, and the next for "SUB" in the case of FIG. 2, as explained in the conventional technology. Regarding “ST” 1
08, 109, 110, then 103 regarding “ADD”
, 104. At this time, since 0 is written in the trap signal field of these addresses, no trap is generated. On the other hand, due to a microprogram error or hardware failure, for example, 100
, 101, 102/107 are accessed. At this time, 1 is written in the trap signal field at address 107, so it becomes a trap and transitions to trap processing. You can see when an address has been accessed.

[0024]

According to the invention of claim 1, in the normal mode, a trap flag can be generated at the same timing as before, and in the debug mode, all steps of a predetermined instruction processing program in the microprogram memory can be generated. A trap flag can be generated only after completion, ie, a trap flag can function similarly to an interrupt flag. This prevents the execution of the instruction processing program from being interrupted at any intermediate step, making it easy to restart the program after trap processing, and greatly improving the efficiency of program debugging.

According to the second aspect of the invention, when an address that is not accessed during normal operation of the microprogram memory is accessed due to a program error or hardware failure, a trap flag is immediately generated; Abnormalities can be detected early. In this case as well, since each instruction processing program is not interrupted in the middle, it is easy to restart the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing main parts of an embodiment corresponding to claim 1.

FIG. 2 is a block diagram showing main parts of an embodiment corresponding to claim 2.

FIG. 3 is a block diagram showing main parts of a control circuit of the electronic device.

FIG. 4 is a diagram showing an example of a program stored in the main memory 1 of FIG. 3.

FIG. 5 is a diagram showing an example of a microprogram stored in the microprogram memory 7 of FIG. 3;

FIG. 6 is a time chart of the microprogram memory 7 in FIG. 5;

7A is a block diagram showing a conventional configuration of the trap flag generating section 6 of FIG. 3, and B is a time chart of A. FIG.

Claims (2)

[Claims] 1. A main memory, a microprogram memory in which processing programs for each instruction of a system program, a trap processing program, and an interrupt processing program written in the main memory are stored; an instruction register that sequentially stores read data of a plurality of instructions of a system program, and an instruction decoder that decodes the output of the instruction register and outputs an address on a microprogram memory of a processing program for each instruction of the system program. , a multiplexer that selects either the address input from the instruction decoder or the address on the microprogram memory of each instruction of the trap processing program and the interrupt processing program that is input separately, and supplies the selected address to the microprogram memory; ,
a memory address calculation unit that calculates the address of the main memory and supplies it to the main memory, a trap flag generation unit, an interrupt flag generation unit, when a trap flag is input, when an interrupt flag is input, and at other times. In a control circuit for an electronic device comprising a select signal generator that generates corresponding select signals at predetermined timings and supplies them to the multiplexer, the trap flag generating section inputs the output of the memory address calculating section. a trap signal generation circuit that checks whether the address is a prohibited address and generates a trap signal when the address is a prohibited address; and a clock that is generated for each address of each row (for each step) of the microprogram memory. , a logic 0 written in the common first field of each step other than the final step of the instruction processing program and the final step, respectively.
and a common second gate for each step of the predetermined instruction processing program of the microprogram memory.
The read data of the mode data (logic 1 in debug mode, logic 0 in normal mode) written in the field is given to the select terminal, and the output of the AND gate is output in debug mode, and the clock is output in normal mode. When the output of the trap signal generating circuit and the multiplexer for selecting is input to the data terminal, a trap flag is generated by inverting the polarity of the output in synchronization with the output of the multiplexer input to the clock terminal, A control circuit for an electronic device, comprising a flip-flop circuit that supplies the trap flag to the select signal generator. 2. A trap flag generating section comprising a flip-flop circuit in place of the trap flag generating section of claim 1, and a trap written in a common field of each row corresponding to each address of the microprogram memory. The read data of the signal (writes a logic 0 in the row of used addresses and a logic 1 in the row of unused addresses) is supplied to the data input terminal of the flip-flop circuit, A control circuit for an electronic device, characterized in that a clock signal generated at each step) is input to a clock terminal of the flip-flop circuit, and an output of the flip-flop circuit is supplied as a trap flag to the select signal generator. .