JPH04350967A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize ultra-microminiaturization of a memory cell by substantially preventing delay of signal. CONSTITUTION:A semiconductor storage device can be divided into a memory cell section and a peripheral circuit section. A field-effect transistor constituting the peripheral circuit section is largely influenced by delay of signal and therefore its gate electrode has a polycide structure. Meanwhile, the memory cell section is required to form an accumulation electrode 7 of a capacitance body above a gate electrode of the field effect transistor 101. Therefore, the gate electrode of the field effect transistor 101 is formed only by a polysilicon film 4 to realize ultra-microminiaturization of the accumulation electrode 7.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
In particular, the present invention relates to a semiconductor memory device equipped with a stacked capacitor using a polycide gate to reduce wiring resistance of gate electrodes and signal delay.

0002

2. Description of the Related Art FIGS. 11 and 12 show a conventional dynamic random access memory (Dynamic Random Access Memory) having stacked capacitor cells.
FIG. 2 is a vertical cross-sectional view showing the structure of cessMemory (hereinafter referred to as DRAM). Figure 11 shows the memory cell section.
Reference numerals 2 and 2 respectively indicate peripheral circuit sections.

In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate polysilicon film, 5 is an impurity diffusion layer, 6 is an interlayer insulating film, 7 is a capacitor storage electrode, and 8 is a capacitor storage electrode. A capacitive insulating film, 9 a capacitive counter electrode, 10 a refractory metal silicide film, 11 an interlayer insulating film, 12 a bit line, 13 an interlayer insulating film, and 14 an aluminum wiring.

In this conventional DRAM, the transistors in the memory cell section and the transistors in the peripheral circuit section are coated with a high melting point metal silicide film 10 in order to reduce the resistance of the gate electrode.
The gate electrode has a silicide structure in which a polysilicon film 4 and a polysilicon film 4 are laminated.

[0005]

[Problems to be Solved by the Invention] In this conventional semiconductor memory device, the lower limit of the film thickness of the gate polysilicon film 4 is determined on the condition that the withstand voltage and reliability of the gate oxide film are not deteriorated. The lower limit of the thickness of the melting point metal silicide film 10 is determined so that the resistance value of the polycide gate electrode falls within an allowable range in terms of circuit design.

For example, if the thickness of the gate polysilicon film 4 is 1,500 angstroms or more, and the refractory metal silicide film 10 is required to have a thickness of 1,000 angstroms or more, the total thickness of the polycide gate electrode is 2,500 angstroms or more.
angstrom or more. In this case, if the area occupied by the memory cell is to be 4 microns or less, the wiring interval between the gate electrodes in the memory cell is 0.5 μm.
There was a problem that microfabrication became difficult.

For example, in a memory cell having a stacked capacitor, the capacitance storage electrode 7 is processed by anisotropic dry etching, but the thicker the gate electrode, the more etching residue is formed along the sidewalls of the gate electrode. When the gap between the gate electrodes narrows as described above, etching residue due to poor microfabrication causes defective products.

[0008]

[Means for Solving the Problems] The gist of the present invention is to provide a memory cell comprising a field effect transistor on a semiconductor substrate and a capacitor having a storage electrode on the gate electrode of the field effect transistor; In a semiconductor memory device in which a peripheral circuit for accessing information of the memory cell is formed, the gate electrode of the field effect transistor of the memory cell is formed only of a polycrystalline silicon film, and the gate electrode of the field effect transistor constituting the peripheral circuit is The electrode has a polycide structure in which a polycrystalline silicon film and a high melting point metal silicide film are laminated.

[0009]

Effects of the Invention Even if the gate electrode of the field effect transistor constituting the peripheral circuit is thick, it will not lead to defects in microfabrication, so a polycide structure is used to increase the speed of signal transmission.

On the other hand, the gate of the field effect transistor of the memory cell is formed only from a polycrystalline silicon film.
Since the film thickness can be reduced, accurate microfabrication can be performed even if a storage electrode is provided above.

[0011]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are cross-sectional views of a semiconductor memory device according to a first embodiment of the present invention. Figure 1 shows the memory cell section.
FIG. 2 shows the peripheral circuit section.

In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate polysilicon film, 5 is an impurity diffusion layer, 6, 11, 13 are interlayer insulating films,
7 is a capacitor storage electrode, 8 is a capacitor insulating film, 9 is a capacitor counter electrode, 10 is a high melting point metal silicide film, 12 is a bit line, 1
4 indicates aluminum wiring.

In the peripheral circuit section, since signal delay due to resistance has a large effect on circuit operation, the field effect transistor 10
The gate electrode of 0 has a polycide structure consisting of a gate polysilicon film 4 and a high melting point metal silicide film 10 to reduce resistance, and the field effect transistor 101 in the memory cell part is processed to reduce the step difference in the gate electrode. For simplicity, the gate electrode is formed only from the gate polysilicon film 4. 3 to 6 are cross-sectional views showing the main steps for forming the semiconductor memory device according to the first embodiment.

First, as shown in FIG. 3, a predetermined region of a semiconductor substrate 1 made of silicon or the like is oxidized by a selective oxidation method to form a field oxide film 2, followed by a gate oxide film 4 and then a polycrystalline silicon film. A gate polysilicon film 4,
Refractory metal silicide 10 made of tungsten silicide, for example, is sequentially formed.

Of course, titanium (Ti), molybdenum (M
o) Silicides of other high melting point metals such as platinum (Pt) can also be used.

Next, as shown in FIG. 4, only the peripheral circuit portion is covered with a resist 15.

Next, as shown in FIG. 5, the high melting point noble silicide 10 in the memory cell portion is etched away using, for example, reactive ion etching (R.I.E.).

Subsequently, as shown in FIG. 6, after forming a resist pattern 16 for the gate electrode using photolithography, the R.I. I. The high melting point metal silicide 10 and gate polysilicon 4 are etched using E to form a gate electrode.

Thereafter, the impurity diffusion layer 5, the capacitive element section, the contact, the bit line 12, the aluminum wiring 14, etc. are sequentially formed to obtain the structure of the semiconductor memory device shown in FIGS. 1 and 2.

FIGS. 7 to 10 are longitudinal sectional views showing the main steps of a second embodiment of the present invention.

After forming a field oxide film 2, a gate insulating film 3, and a gate polysilicon 4 on a semiconductor substrate 1 in the same manner as in the first embodiment, an oxide film 17 is formed on the entire surface by, for example, the CVD method, as shown in FIG. do. Using the resist 15 as a mask, the oxide film 17 is removed only from the peripheral circuit portion by dry etching or wet etching using hydrofluoric acid (HF).

Next, as shown in FIG. 8, after removing the resist 15, a high melting point metal 18 such as tungsten (W) or titanium (Ti) is formed by sputtering, and then a high melting point metal 18 is formed by lamp annealing using an infrared lamp. metal 18
and gate polysilicon 4 are reacted to form polysilicon. At this time, the refractory metal 18 on the oxide film is not silicided and remains unreacted, such as tungsten (W) or titanium (T).
i) remains.

Next, as shown in FIG. 9, the unreacted high melting point metal 18 (tungsten or titanium) is treated with, for example, a mixed solution of aqueous ammonia (NH3OH) and hydrogen peroxide (H2O2) or hydrofluoric acid (HF). Remove by etching. Furthermore, the oxide film 17 is removed using hydrofluoric acid (HF).

Thereafter, a resist pattern 16 for the gate electrode is formed by photolithography (FIG. 10).
.

Thereafter, gate electrodes, capacitor elements, bit lines 12, contacts, aluminum interconnections 14, etc. are formed in the same manner as in the first embodiment to complete the semiconductor memory device shown in FIGS. 1 and 2.

[0027]

As explained above, in the present invention, the gate electrode in the peripheral circuit part has a polycide structure of high melting point metal silicide 10 and gate polysilicon 4, and in the memory cell part, the gate electrode has a polycide structure of high melting point metal silicide 10 and gate polysilicon 4. By forming polysilicon 4, it is possible to lower the gate resistance in the peripheral circuit area, increasing the speed of circuit operation, and at the same time, reducing the step difference in the gate electrode in the memory cell area, making it possible to reduce the gate resistance in the peripheral circuit area. This facilitates processing of the capacitance storage electrode 7 of the capacitor cell.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a memory cell portion of a first embodiment.

FIG. 2 is a sectional view showing a peripheral circuit section of the first embodiment.

FIG. 3 is a cross-sectional view showing the first step of the manufacturing method for obtaining the structure of the first example.

FIG. 4 is a cross-sectional view showing the second step of the manufacturing method for obtaining the structure of the first embodiment.

FIG. 5 is a sectional view showing the third step of the manufacturing method for obtaining the structure of the first example.

FIG. 6 is a sectional view showing the fourth step of the manufacturing method for obtaining the structure of the first example.

FIG. 7 is a sectional view showing the first step of another manufacturing method for obtaining the structure of the first embodiment.

FIG. 8 is a cross-sectional view showing the second step of another manufacturing method for obtaining the structure of the first embodiment.

FIG. 9 is a sectional view showing the third step of another manufacturing method for obtaining the structure of the first embodiment.

FIG. 10: Fourth example of another manufacturing method for obtaining the structure of the first embodiment.
It is a sectional view showing a process.

FIG. 11 is a cross-sectional view showing a conventional memory cell section.

FIG. 12 is a sectional view showing a peripheral circuit section of a conventional example.

[Explanation of symbols]

1 Semiconductor substrate 2 Field oxide film 3 Gate oxide film 4 Gate polysilicon 5 Impurity diffusion layer 6 Interlayer insulating film 7 Capacitive storage electrode 8 Capacitive insulating film 9 Capacitive counter electrode 10 Refractory metal silicide 11 Interlayer insulating film 12 Bit line 13 Interlayer insulation Film 14 Aluminum wiring 15, 16 Resist 17 Oxide film 18 High melting point metal

Claims (1)

[Claims] 1. A memory cell comprising a field effect transistor on a semiconductor substrate and a capacitor having a storage electrode on the gate electrode of the field effect transistor, and a peripheral circuit for accessing information in the memory cell. In the semiconductor memory device in which the field effect transistor of the memory cell is formed, the gate electrode of the field effect transistor is formed only of a polycrystalline silicon film, and the gate electrode of the field effect transistor constituting the peripheral circuit is formed of a polycrystalline silicon film and a high melting point metal. A semiconductor memory device characterized by having a polycide structure in which a silicide film is laminated.