JP2000332105A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a resistance increase in a connection hole. SOLUTION: After a contact hole 24 is bored in a semiconductor substrate 1, a Ti film 26 is adhered in the contact hole 24 and thermally processed and a silicide layer 27 is formed at the part contacting the semiconductor substrate 1. Then a TiN film 28 is adhered in the contact hole 24 and then a heat treatment is carried out to remove moisture, oxygen, etc., in the contact hole 24. Then a tungsten film 29 is formed in the contact hole 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a technique for embedding a conductive film in a connection hole.

[0002]

2. Description of the Related Art The technique of embedding a conductor film in a connection hole studied by the present inventors is as follows, for example. That is, after a connection hole through which a part of the semiconductor substrate is exposed is formed in an insulating film formed on a semiconductor substrate, a conductive film for a barrier is formed in the connection hole, and tungsten is further formed in the connection hole. Is formed by a CVD (Chemical Vapor Deposition) method or the like.

[0003] As for the electrode / conductor forming technology, for example, Press Journal Co., Ltd., November 1, 1991
JP, "Semiconductor World Special Issue No. '92 Latest Semiconductor Process Technology", p327-p333,
A technique for forming a contact electrode using a CVD-plug is disclosed.

[0004]

However, the present inventor has found that there is the following problem in the technique of embedding the conductive film in the connection hole.

[0005] That is, in the above-described connection hole filling technology, since the barrier conductor film is used, the conditions of the tungsten CVD process are the resistance in the connection hole (the contact resistance between the conductor film and the semiconductor substrate in the connection hole and the contact resistance). Although it was thought that the resistance was not related to the electric resistance of the conductor film in the connection hole, the high temperature heat treatment (for example, 600 ° C. or higher) after the step of embedding the conductor film caused the resistance, particularly the resistance of the conductor film in the connection hole to p. The problem is that the contact resistance with the ⁺ type semiconductor region increases according to the conditions of the tungsten CVD process.

An object of the present invention is to provide a technique capable of suppressing an increase in resistance in a connection hole.

Another object of the present invention is to provide a technique capable of suppressing a resistance in a connection hole from changing for each process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the method of manufacturing a semiconductor device according to the present invention comprises: (a) a step of forming a connection hole in an insulating film; (b) a step of performing a first heat treatment after the step (a); The method includes a step of burying a conductive film in the connection hole after the step (b) and a step of performing a second heat treatment at 600 ° C. or higher after the step (c).

Further, a method of manufacturing a semiconductor device according to the present invention
(A) a step of forming a connection hole in an insulating film; (b) a step of forming a first conductor film in the connection hole; and (c) a second step in the connection hole after the step (b). A step of embedding a conductor film, (d) a step of performing a first heat treatment after the step (a) and before the step (c), and (e) a second heat treatment at 600 ° C. or higher after the step (c). And a step of applying

Further, a method of manufacturing a semiconductor device according to the present invention
The atmosphere for the first heat treatment is a reducing gas atmosphere or an inert gas atmosphere.

Further, a method of manufacturing a semiconductor device according to the present invention
The first heat treatment is performed in a chamber for forming the second conductive film.

Further, in the method of manufacturing a semiconductor device according to the present invention, the temperature at the time of the first heat treatment and the temperature at the time of forming the second conductor film are made substantially equal.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

In this embodiment, a p-channel type MISFET (Metal Insulator Semiconductor) is used.
Field Effect Transistor) is abbreviated as pMIS, and an n-channel MISFET is abbreviated as nMIS.

In the present embodiment, the present invention is applied to, for example, a DRAM (Dynamic Random Access Memory) or an FRAM.
A case where the present invention is applied to a method of manufacturing an eRAM (Ferroelectric RAM) will be described. FIG. 1 is a fragmentary cross-sectional view of the semiconductor device of the present embodiment during a manufacturing step thereof. The semiconductor substrate 1 is made of, for example, a p-type silicon single crystal. DRA
M memory cells are formed on the main surface of the semiconductor substrate 1 by p.
Formed in the mold well 2. The p-type well 2 in the region (memory array) in which the memory cells are formed is doped with, for example, boron to prevent noise from entering from an input / output circuit or the like formed in another region of the semiconductor substrate 1. Are electrically separated from the semiconductor substrate 1 by an n-type semiconductor region 3 formed thereunder. For example, phosphorus or arsenic is introduced into the n-type semiconductor region 3.

A DRAM memory cell has a stacked structure in which an information storage capacitor is arranged above a memory cell selection MISFET Qs. M for memory cell selection
The ISFET Qs is formed of an n-channel MISFET and is formed in the p-type well 2. The peripheral circuits of the DRAM include an n-channel MISFET Qn and a p-channel M
ISFET Qp. n-channel type MI
The SFET Qn is formed in a p-type well 2, and the p-channel MISFET Qp is formed in an n-type well 4. n
For example, phosphorus or arsenic is introduced into the mold well 4.

The element isolation region surrounding the active region is constituted by an element isolation groove 6 formed by embedding a silicon oxide film 5 in a shallow groove opened in the semiconductor substrate 1. The silicon oxide film 5 buried in the element isolation trench 6 is flattened so that its surface is almost the same height as the surface of the active region. An element isolation region constituted by such an element isolation groove 6 has a bird's beak (birk) at an end of the active region.
Since d's beak) cannot be performed, the effective area can be increased as compared with an element isolation region (field oxide film) of the same size formed by the LOCOS (selective oxidation) method.

The memory cell selecting MISFET Qs mainly includes a gate oxide film 7, a gate electrode 8A, a source,
It is constituted by a pair of n-type semiconductor regions 9 constituting a drain. The gate electrode 8A is formed integrally with the word line WL, and extends linearly in a predetermined direction with the same width and the same space. Gate electrode 8A
The (word line WL) includes, for example, a low-resistance polycrystalline silicon film doped with an n-type impurity such as P (phosphorus) and a barrier metal layer made of a WN (tungsten nitride) film and the like formed thereon. W formed on the top
It has a polymetal structure composed of a high melting point metal film such as a (tungsten) film. Since the gate electrode 8A (word line WL) having a polymetal structure has a lower electric resistance than a gate electrode formed of a polycrystalline silicon film or a polycide film, the signal delay of the word line can be reduced.
However, the gate electrode 8A may be composed of, for example, a single film of a low-resistance polycrystalline silicon film, or may have a so-called polycide structure in which a silicide film such as tungsten silicide is stacked on the low-resistance polycrystalline silicon film. Is also good.

N-channel type M of the peripheral circuit of the DRAM
The ISFET Qn is mainly composed of a gate oxide film 7, a gate electrode 8B, and a pair of n ⁺ type semiconductor regions 10 and 10 constituting a source and a drain. Also,
The p-channel type MISFET Qp is mainly constituted by a gate oxide film 7, a gate electrode 8C, and a pair of p ⁺ -type semiconductor regions 11, 11 constituting a source and a drain. Gate electrodes 8B and 8C have the same polymetal structure as gate electrode 8A (word line WL).
N-channel MISFETs Qn and p constituting the peripheral circuit
The channel type MISFET Qp is manufactured with a looser design rule than a memory cell.

A silicon nitride film 12 is formed above the gate electrode 8A (word line WL) of the memory cell selecting MISFET Qs. The upper and side walls of the silicon nitride film 12 and the gate electrode 8A (word line WL) are formed. The silicon nitride film 13 is formed on the side wall. A silicon nitride film 12 is formed on the gate electrodes 8B and 8C of the MISFET of the peripheral circuit.
On the side walls of B and 8C, sidewall spacers 13s made of the silicon nitride film 13 are formed.

The silicon nitride film 12 and the silicon nitride film 13 of the memory array are used as memory cell selecting MISFETs Qs
Is used as an etching stopper when a contact hole is formed in a self-aligned (self-aligned) manner above the source and drain (n-type semiconductor regions 9 and 9). Also,
The sidewall spacer 13s of the peripheral circuit is a so-called LDD in which the source and drain of the n-channel MISFET Qn and the source and drain of the p-channel MISFET Qp are formed of a low impurity concentration region and a high impurity concentration region.
(Lightly Doped Drain) Used to make a structure.

Memory cell selecting MISFET Qs, n-channel MISFET Qn and p-channel MISFET
The SOG film 16 is formed on the ETQp. Further, two layers of silicon oxide films 17 and 18 are formed further above the SOG film 16, and the upper silicon oxide film 18 is formed such that the surface thereof is substantially the same in the entire area of the semiconductor substrate 1. It has been flattened.

The silicon oxide films 18 and 17 and the SOG film 1 are formed on a pair of n-type semiconductor regions 9 and 9 constituting the source and the drain of the memory cell selecting MISFET Qs.
6 are formed. Plugs 21 made of a low-resistance polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) are embedded in these contact holes 19 and 20.

The diameters of the bottoms of the contact holes 19 and 20 in a predetermined direction (width direction of the word line WL) are equal to those of the silicon nitride film 13 on one side wall of the two opposing gate electrodes 8A (word line WL) and the other. It is defined by the space with the silicon nitride film 13 on the side wall. That is, the contact holes 19 and 20 are connected to the gate electrode 8A (word line WL).
Are formed in a self-aligned manner.

The diameter of one of the pair of contact holes 19, 20 in the word line extending direction is substantially the same as the dimension of the active region in the word line extending direction. On the other hand, the other contact hole 19
The diameter of the contact line on the n-type semiconductor region 9 shared by the two memory cell selecting MISFETs Qs in the word line extending direction is larger than the dimension of the active region in the word line extending direction. That is, the contact hole 19
Is formed in a substantially rectangular plane pattern whose diameter in the word line extending direction is larger than the diameter in the word line width direction, and a part thereof extends from the active region onto the element isolation groove 6. . By configuring the contact hole 19 with such a pattern, when the bit line BL and the n-type semiconductor region 9 are electrically connected via the contact hole 19,
The memory cell size can be reduced because the width of the bit line does not have to be partially increased to extend to the upper part of the active region, or part of the active region does not need to extend in the bit line direction. Becomes On top of the silicon oxide film 18, a silicon oxide film 22 is formed. A through hole 23 is formed in the silicon oxide film 22 above the contact hole 19.

For such a semiconductor substrate 1, first,
As shown in FIGS. 2 and 3, by removing the silicon oxide films 22, 18, 17, the SOG film 16 and the gate oxide film 7 of the peripheral circuit by dry etching using a photoresist film (not shown) as a mask. , N-channel type M
The upper part of the n ⁺ type semiconductor region 10 (source and drain) of the ISFET Qn and the p of the p channel type MISFET Qp
^A contact hole (connection hole) 24 is formed above the ⁺ type semiconductor region 11 (source, drain). At the same time, a contact hole (connection hole) 25 is formed above the gate electrode 8C of the p-channel MISFET Qp, and similarly, a contact hole (not shown) is formed above the gate electrode 8B of the n-channel MISFET Qn. In addition,
FIG. 3 is an enlarged sectional view of the contact hole 24 as a representative of the sectional views of the contact holes 24 and 25 in FIG.

As described above, the etching for forming the through holes 22 and the etching for forming the contact holes 24 and 25 are performed in separate steps, so that when forming the deep contact holes 24 and 25 in the peripheral circuit, the memory array is formed. Plug 2 exposed at bottom of shallow through hole 22
1 can be prevented from being cut deeply. The formation of the through hole 22 and the formation of the contact holes 24 and 25 may be performed in the reverse order.

Next, as shown in FIGS. 4 and 5, a Ti film 26 is deposited on the silicon oxide film 23 including the insides of the contact holes 24 and 25 and the through hole 22.
The Ti film 26 is deposited by using a highly directional sputtering method such as a collimation sputtering method or an ionization sputtering method so that the Ti film 26 is deposited with a certain thickness on the bottoms of the contact holes 24 and 25 having a large aspect ratio. FIG. 5 is an enlarged sectional view of the contact hole 24 of FIG.

Subsequently, a heat treatment is performed in an inert gas atmosphere such as Ar (argon) without exposing the Ti film 26 to the atmosphere. By this heat treatment, the contact holes 24, 2
5 reacts with the Si substrate at the bottom of the n-type MISFET Qn, the surface of the n ⁺ -type semiconductor region 10 (source, drain) and the p ⁺ -type semiconductor of the p-channel MISFET Qp as shown in FIG. Region 11 (source,
A TiSi ₂ layer 27 is formed on the surface of the (drain).
At this time, the plug 21 at the bottom of the through hole 22
A TiSi ₂ layer 27 is also formed on the surface of the substrate by a reaction between the polycrystalline silicon film constituting the plug 21 and the Ti film 26.

By forming the above-described TiSi ₂ layer 27 at the bottom of the contact hole 24, the plug formed inside the contact hole 24 in the next step and the source and drain (n ⁺⁾ of the MISFET of the peripheral circuit are formed. Since the contact resistance at the portion where the semiconductor region 10 is in contact with the p ⁺ type semiconductor region 11) can be reduced, the DRA
High-speed operation of peripheral circuits such as a sense amplifier and a word driver constituting the peripheral circuit of M is promoted. Note that TiS
The Ti film 26 after the formation of the i ₂ layer 27 may be removed. The silicide layer at the bottom of the contact hole 24 is T
Refractory metal silicide other than iSi ₂ such as CoSi
₂ (cobalt silicide), TaSi ₂ (tantalum silicide), MoSi ₂ (molybdenum silicide), or the like.

Next, as shown in FIG. 8 and FIG.
A TiN film (first conductor film) 28 is deposited on the film 26 by a CVD method or the like. FIG. 9 shows the contact hole 2 of FIG.
4 is an enlarged sectional view of FIG. The TiN film 28 is a barrier conductor film having a function of suppressing the erosion of Si when a later-described tungsten film is formed by a CVD method. The barrier conductor film is not limited to the TiN film but can be variously modified. For example, tungsten nitride or tungsten may be used. However, when tungsten is used as the barrier conductor film, the tungsten is formed by a sputtering method or the like. CVD of TiN film
Since the step coverage is higher than that of the sputtering method, the contact holes 24 and 25 having a large aspect ratio have a T.sub.
This is because the iN film 28 can be deposited.

Subsequently, a cleaning process is performed on the semiconductor substrate 1. This is mainly intended to remove chlorine generated at the time of forming the TiN film 28. This is because if this chlorine remains in the contact holes 24 and 25, the oxidation phenomenon of the Si substrate described later will be increased. After the formation of the TiN film 28, the process can be shifted to a film forming process of tungsten by a CVD method through a heat treatment process of the present invention without opening to the atmosphere.

After that, the semiconductor substrate 1 is carried into a CVD apparatus for forming a tungsten film, and then, in the CVD apparatus, the semiconductor substrate 1 is subjected to, for example, 300 ° C. or more (preferably) before the tungsten film is formed. Is 450 ° C
The above heat treatment is performed. In this embodiment, for example, heat treatment is performed at 475 ° C. for about 2 minutes in a hydrogen gas atmosphere.

This heat treatment is a treatment for removing moisture and oxygen on the surface of the semiconductor substrate 1, especially the contact holes 24 and 25 and the through hole 23. That is,
Surface of semiconductor substrate 1, especially contact holes 24, 25
If oxygen (including moisture) is left in the through hole 23, the oxygen is subjected to a high-temperature heat treatment (for example, information storage) after the process of embedding tungsten in the contact holes 24, 25 and the through hole 22. The formation of the SiO ₂ film by reacting with the semiconductor substrate 1 in the step of forming the capacitive insulating film of the capacitive element for use (oxidation of the Si substrate) can be suppressed. Therefore, an increase in resistance (contact resistance and electric resistance) at contact holes 24 and 25 and through hole 22 can be suppressed. Therefore, the operation speed of the semiconductor device can be improved. In addition, contact holes 24 and 2
5 and the resistance in the through hole 22 can be suppressed from changing for each process. For this reason, it is possible to improve the performance and reproducibility in function of the semiconductor device.

By setting the atmosphere during the heat treatment to a hydrogen gas atmosphere, oxygen (O) of TiO on the surface of the TiN film 28 can be removed by hydrogen. Therefore, contact holes 24 and 25 and through hole 2
3 can be reduced. Further, the atmosphere during the heat treatment may be an inert gas atmosphere such as argon. This makes it possible to remove moisture and oxygen from the surface of the semiconductor substrate 1, especially the contact holes 24 and 25 and the through hole 23, without causing unnecessary chemical reaction during the heat treatment.

Further, by performing this heat treatment in a CVD device for the subsequent tungsten film formation, the heat treatment can be performed without being conscious of the addition. The heat treatment temperature is, for example, 300 ° C. or more, specifically, for example, 475 ° C.
This is because the temperature at the time of forming a tungsten film to be described later following this heat treatment is approximately 300 ° C. to 500 ° C., which is effective in achieving temperature consistency with the treatment. That is, it is possible to smoothly shift from the heat treatment to the CVD film forming process of tungsten. However, the heat treatment temperature can be set to, for example, about 600 ° C. or 700 ° C. In that case, the heat treatment time can be reduced. Also, the heat treatment temperature can be lower than, for example, 300 ° C., in which case the heat treatment time is lengthened. The relationship between the heat treatment temperature and time and the resistance in the contact holes 24 and 25 will be described later in detail.

Next, in the same CVD apparatus as in the above heat treatment, for example, tungsten hexafluoride (WF ₆ ), hydrogen and C using monosilane (SiH ₄ ) as a source gas are used.
By the VD method, as shown in FIGS.
A tungsten film 29 is deposited on the N film 28, and the insides of the contact holes 24 and 25 and the through hole 23 are completely filled with the tungsten film 29. FIG. 11 shows FIG.
FIG. 3 is an enlarged sectional view of a contact hole 24 of No. 0;

Subsequently, the tungsten film 29, the TiN film 28, and the Ti film 27 on the silicon oxide film 23 are removed (polished back) by using the CMP method, and as shown in FIG. 25
And the above-mentioned tungsten film 2 inside the through hole 23.
9. A plug 30 composed of the TiN film 28 and the Ti film 27 is formed.

The plug 30 removes the tungsten film 29, the TiN film 28 and the Ti film 26 on the silicon oxide film 23 by dry etching (etch back).
It may be formed by doing. Also, plug 30
May be constituted mainly by the TiN film 28 without using the tungsten film 29. That is, the plug 30 may be formed by burying a thick TiN film 28 in the contact holes 24 and 25 and the through hole 23. In this case, the resistance of the plug 30 is somewhat higher than in the case where the tungsten film 29 is mainly used, but the tungsten film 29 deposited on the silicon oxide film 23 in the next step is dry-etched to form the bit line BL. Since the TiN film 28 serves as an etching stopper when forming the first layer wiring of the peripheral circuit, the margin of misalignment between the first layer wiring and the contact holes 24 and 25 is remarkably improved. The degree of freedom in the layout of the wiring in the layer is greatly improved.

Next, as shown in FIGS. 13 and 14, a DRAM is manufactured. FIG. 14 is a plan view of a main part of the memory cell of FIG. Reference symbol L in FIG. 14 indicates the active region.

That is, first, a tungsten film is deposited on the silicon oxide film 22 by a sputtering method, and then the tungsten film is dry-etched using a photoresist film (not shown) formed on the tungsten film as a mask. Then, the bit line BL is formed in the memory array, and the first-layer wiring 31 is formed in the peripheral circuit. In addition,
Since the tungsten film has a high light reflectance, the photoresist film may cause halation at the time of exposure, and the dimensional accuracy of the pattern (width and space) may be reduced. To prevent this, a thin anti-reflection film may be deposited on the tungsten film, and then a photoresist film may be applied. An organic material or a metal material having a low light reflectance (for example, a TiN film) is used for the antireflection film.

Subsequently, for example, a cylindrical information storage capacitor C is formed. The information storage capacitor C is connected to the lower electrode 32.
And a capacitor insulating film 33 and an upper electrode 34.
The lower electrode 32 is made of a polycrystalline silicon film and has a plug 3
5, and is electrically connected to the plug 21. The lower electrode 32 is made of a conductive material other than polycrystalline silicon, for example, a high melting point metal such as tungsten or Ru (ruthenium) or R
It is also possible to use a conductive metal oxide such as uO (ruthenium oxide) or IrO (iridium oxide).

The capacitance insulating film 33 is made of, for example, a Ta ₂ O ₅ film, for example, pentaethoxy tantalum (Ta (OC ₂
H _{5) 5)} and is deposited by a CVD method using a source gas. The capacitance insulating film 33 is made of, for example, BST, STO, Ba
TiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT (PbZr _x Ti _1-x O ₃ ), PLT
(PbLa _x Ti ₁ -x O ₃ ), or a high (ferro) dielectric film made of a metal oxide such as PLZT.
In this case, the material of the lower electrode 32 is, for example, platinum, ruthenium, RuO (ruthenium oxide) or Ir.
O (iridium oxide) is preferably used.

The upper electrode 34 is made of, for example, a TiN film, and is deposited by using, for example, a CVD method and a sputtering method. The upper electrode 47 may be formed of a conductive film other than the TiN film, for example, a tungsten film.

In the process of forming such an information storage capacitive element C, a high-temperature heat treatment is performed. Therefore, if moisture or oxygen is left at the connection (contact hole 24) between the plug 30 and the semiconductor substrate 1, Although the resistance (contact resistance and electric resistance) at the connection part increases, in the present embodiment, since the moisture and oxygen are removed,
An increase in resistance (contact resistance and electric resistance) at the connection portion can be suppressed. In particular, the plug 30 and the p ⁺ type semiconductor region 1
1 can be reduced. Therefore, it is possible to promote the improvement of the reliability, function (particularly, operation speed) and yield of the DRAM.

Thereafter, the second-layer wiring 36, the third-layer wiring 37, and the plug 38 for electrically connecting them, and the plug for electrically connecting the third-layer wiring 37 to the upper electrode 34 are formed. Form 39. The wirings 36 and 37 are mainly composed of, for example, aluminum or an aluminum alloy. The plugs 38 and 39 are formed in the same manner as the plug 30 except for the silicide treatment, and have the same structure except for the silicide layer.

Next, the measurement results of the contact resistance (contact resistance and electric resistance; the same applies hereinafter) in the contact holes 24 and 25 according to the heat treatment temperature and time before the tungsten film is embedded in the contact holes 24 and 25 are shown. 15 to 32.

FIGS. 15 to 20 show the measurement results when the plug 30 is electrically connected to the p ⁺ type semiconductor region 11, and FIGS. 15 to 17 show the case where the diameter of the contact hole 24 is smaller. For example, FIG. 18 to FIG. 20 show the case where the diameter of the contact hole 24 is about 0.24 μm.
For example, a case of about 0.30 μm is shown.

FIGS. 15 and 18 show the results when the heat treatment atmosphere is a reducing gas atmosphere. In FIGS. 15 and 18, (a) and (b) show the results when the heat treatment temperature is 475.degree. ° C. In this case, as shown in FIGS. 15 and 18, in the heat treatment in a reducing atmosphere, the contact resistance is reduced by increasing the treatment time.

FIGS. 16 and 19 show the results when the heat treatment atmosphere is an inert gas atmosphere. In FIGS. 16 and 19, (a) and (b) show the results when the heat treatment temperature is 475.degree. ° C. In this case, as shown in FIG. 16A and FIG. 19A, in the heat treatment in an inert gas atmosphere, if the treatment time is increased (2 minutes), the contact resistance is increased. .

FIGS. 17 (a) and 20 (a) show the tungsten film formation temperature and contact resistance when the heat treatment temperature is equal to the temperature during the subsequent tungsten film formation when the heat treatment atmosphere is a reducing gas atmosphere. Shows the relationship. Also, FIG. 17 (b) and FIG. 20 (b)
Shows the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature is 475 ° C. when the heat treatment atmosphere is a reducing gas atmosphere. In each case, the variation in contact resistance due to the film formation temperature is small. From these results alone, it can be seen that a change in the contact resistance can be reduced when the heat treatment temperature and the tungsten film formation temperature are equal.

FIGS. 21 to 26 show the measurement results when the plug 30 is electrically connected to the n ⁺ -type semiconductor region 10, and FIGS. For example, FIG. 24 to FIG. 26 show the case where the diameter of the contact hole 24 is about 0.24 μm.
For example, a case of about 0.30 μm is shown.

FIGS. 21 and 24 show the results when the heat treatment atmosphere is a reducing gas atmosphere. In FIGS. 21 and 24, (a) and (b) show the results when the heat treatment temperature is 475.degree. ° C.

FIGS. 22 and 25 show the results when the heat treatment atmosphere is an inert gas atmosphere. In FIGS. 22 and 25, (a) and (b) show the results when the heat treatment temperature is 475.degree. ° C. It should be noted that the n ⁺ type semiconductor region 10 does not originally have the problem of increasing the resistance and is considered to be ineffective in the heat treatment. On the contrary, there is no side effect.

FIG. 23 (a) and FIG. 26 (a) show the tungsten film formation temperature and contact resistance when the heat treatment temperature is equal to the temperature during the subsequent tungsten film formation when the heat treatment atmosphere is a reducing gas atmosphere. Shows the relationship. FIG. 23 (b) and FIG. 26 (b)
Shows the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature is 475 ° C. when the heat treatment atmosphere is a reducing gas atmosphere. In each case, the variation in contact resistance due to the film formation temperature is small.

FIGS. 27 to 32 show measurement results when the plug 30 in the contact hole 25 is electrically connected to the gate electrode 8C. FIGS. 27 to 29 show the diameter of the contact hole 25. Is, for example, 0.24μ
30 to 32 show a case where the diameter of the contact hole 25 is, for example, about 0.30 μm. In this case, the gate electrode 8C has a polycide structure.

FIGS. 27 and 30 show the results when the heat treatment atmosphere is a reducing gas atmosphere. FIGS. 27 (a) and 30 (b) show the results when the heat treatment temperature is 475 ° C. and 450 ° C., respectively. ° C. In this case, as shown in FIGS. 27 and 30, in the heat treatment in the reducing atmosphere, it seems that there is almost no change even if the treatment time is lengthened.

FIGS. 28 and 31 show the results when the heat treatment atmosphere is an inert gas atmosphere. In FIGS. 28 and 31, (a) and (b) show the results when the heat treatment temperature is 475.degree. ° C. Also for the gate electrode 8C, there is no problem of a rise in resistance, and it is considered that the heat treatment is not effective. On the contrary, there is no side effect.

FIGS. 29A and 32A show the tungsten film formation temperature and contact resistance when the heat treatment temperature is equal to the temperature during the subsequent tungsten film formation when the heat treatment atmosphere is a reducing gas atmosphere. Shows the relationship. 29 (b) and FIG. 32 (b)
Shows the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature is 475 ° C. when the heat treatment atmosphere is a reducing gas atmosphere. In each case, the variation in contact resistance due to the film formation temperature is small.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, in the above-described embodiment, the case where the information storage capacitance element is cylindrical is described. However, the present invention is not limited to this, and various changes can be made. For example, the capacitance may be formed on the surface of the protruding lower electrode. A structure in which an upper electrode is attached via an insulating film may be employed.

In the above embodiment, the case where the contact hole is filled with tungsten via the barrier film has been described. However, the present invention is not limited to this. For example, silicide may be formed at the bottom of the contact hole as in the above embodiment. After forming the layer, titanium nitride or tungsten nitride can be embedded. In this case, too, moisture and oxygen in the contact holes are removed by performing the same heat treatment as in the above embodiment before forming the titanium nitride or the tungsten nitride.

In the above description, the invention made mainly by the inventor has been described in terms of the DRA which is the application field in which the background was used.
Although the case where the present invention is applied to the manufacturing method of M has been described, the present invention is not limited thereto. For example, an SRAM (Static R)
andom Access Memory), Flash Memory (EEPR)
A semiconductor device having another memory circuit such as OM (Electric Erasable Read Only Memory), a semiconductor device having a logic circuit such as a microprocessor, or a semiconductor device having a memory circuit and a logic circuit provided on the same semiconductor substrate. Can also be applied.

[0066]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, by performing heat treatment prior to the process of forming the second conductor film, moisture and oxygen remaining in the connection holes can be removed. It is possible to suppress an increase in resistance (contact resistance and electric resistance) in the connection hole due to the above.

(2) According to the above (1), it is possible to promote the improvement of the operation speed of the semiconductor device.

(3) According to the present invention, by performing a heat treatment prior to the film forming process of the second conductor film, it is possible to remove moisture, oxygen, and the like remaining in the connection hole. It is possible to suppress the resistance (contact resistance and electric resistance) in the connection hole due to the above-mentioned fluctuations from process to process.

(4) According to the above (3), it is possible to improve the performance and the reproducibility in function of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention during a manufacturing step thereof;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2;

FIG. 4 is an explanatory diagram showing a technical idea of the present invention and schematically showing a part of a circuit;

FIG. 5 is an explanatory diagram schematically showing a circuit in a technique studied by the present inventors.

FIGS. 6A and 6B are plan views of a semiconductor device according to an embodiment of the present invention.

FIG. 7 is an explanatory diagram schematically showing an arrangement of wiring systems and switch elements in the semiconductor device of FIG. 6;

FIG. 8 is an explanatory diagram schematically showing a modification of FIG. 7;

9 is an explanatory diagram of the semiconductor device of FIG. 6 during a test.

FIG. 10 is an explanatory diagram of a switch element at the time of testing the semiconductor device of FIG. 6;

11 is an explanatory diagram of a switch element during operation of the semiconductor device of FIG. 6;

FIG. 12 is an explanatory diagram schematically showing a modified example of the semiconductor device of FIG. 6;

13 (a) and (b) show one of the technical ideas of the present invention.
FIG. 4 is an explanatory view schematically showing a means for stabilizing well potential.

FIGS. 14A and 14B are explanatory diagrams schematically showing a modification of FIG.

FIG. 15 is a graph showing a relationship between a heat treatment time in a heat treatment in a reducing gas atmosphere and a contact resistance of a contact having a diameter of 0.24 μm, where (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 16 is a graph showing a relationship between a heat treatment time by a heat treatment in an inert gas atmosphere and a contact resistance of a contact having a diameter of 0.24 μm, wherein (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 17A is a graph showing a relationship between a tungsten film forming temperature and a contact resistance when a heat treatment temperature and a subsequent tungsten film forming temperature are equal in a heat treatment in a reducing gas atmosphere, and FIG. The case where the heat treatment temperature is 475 ° C. is shown.

FIG. 18 is a graph showing a relationship between a heat treatment time by a heat treatment in a reducing gas atmosphere and a contact resistance of a 0.30 μm-diameter contact, wherein (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 19 is a graph showing a relationship between a heat treatment time by a heat treatment in an inert gas atmosphere and a contact resistance of a contact having a diameter of 0.24 μm, where (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 20A is a graph showing the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature and the subsequent tungsten film formation temperature are equal in the heat treatment in a reducing gas atmosphere; The case where the heat treatment temperature is 475 ° C. is shown.

FIG. 21 is a graph showing a relationship between a heat treatment time by a heat treatment in a reducing gas atmosphere and a contact resistance of a contact having a diameter of 0.24 μm, wherein (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 22 is a graph showing a relationship between a heat treatment time by a heat treatment in an inert gas atmosphere and a contact resistance of a contact having a diameter of 0.24 μm, wherein (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 23A is a graph showing the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature and the subsequent tungsten film formation temperature are equal in the heat treatment in a reducing gas atmosphere, and FIG. The case where the heat treatment temperature is 475 ° C. is shown.

FIG. 24 is a graph showing a relationship between a heat treatment time in a heat treatment in a reducing gas atmosphere and a contact resistance of a 0.30 μm-diameter contact, wherein (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 25 is a graph showing a relationship between a heat treatment time by a heat treatment in an inert gas atmosphere and a contact resistance of a 0.30 μm-diameter contact, wherein (a) shows a case where the heat treatment temperature is 475 ° C. b) is a heat treatment temperature of 45.
The case of 0 ° C. is shown.

FIG. 26A is a graph showing the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature and the subsequent tungsten film formation temperature are equal in the heat treatment in a reducing gas atmosphere, and FIG. The case where the heat treatment temperature is 475 ° C. is shown.

FIG. 27 is a graph showing a relationship between a heat treatment time in a heat treatment in a reducing gas atmosphere and a contact resistance,
(A) shows the case where the heat treatment temperature is 475 ° C, and (b) shows the case where the heat treatment temperature is 450 ° C.

FIG. 28 is a graph showing a relationship between a heat treatment time by a heat treatment in an inert gas atmosphere and a contact resistance,
(A) shows the case where the heat treatment temperature is 475 ° C, and (b) shows the case where the heat treatment temperature is 450 ° C.

FIG. 29A is a graph showing the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature and the subsequent tungsten film formation temperature are equal in the heat treatment in a reducing gas atmosphere; The case where the heat treatment temperature is 475 ° C. is shown.

FIG. 30 is a graph showing a relationship between a heat treatment time in a heat treatment in a reducing gas atmosphere and a contact resistance,
(A) shows the case where the heat treatment temperature is 475 ° C, and (b) shows the case where the heat treatment temperature is 450 ° C.

FIG. 31 is a graph showing a relationship between a heat treatment time by a heat treatment in an inert gas atmosphere and a contact resistance,
(A) shows the case where the heat treatment temperature is 475 ° C, and (b) shows the case where the heat treatment temperature is 450 ° C.

FIG. 32 (a) is a graph showing the relationship between the tungsten film formation temperature and the contact resistance when the heat treatment temperature is equal to the subsequent tungsten film formation temperature in the heat treatment in a reducing gas atmosphere; The case where the heat treatment temperature is 475 ° C. is shown.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 p-type well 3 n-type semiconductor region 4 n-type well 5 silicon oxide film 6 element isolation groove 7 gate oxide film 8A to 8C gate electrode 9 n-type semiconductor region 9 an n ^- type semiconductor region 10 n ⁺ type semiconductor region Reference Signs List 11 p ⁺ type semiconductor region 12 silicon nitride film 13 silicon nitride film 13 s sidewall spacer 14 n ⁻ type semiconductor region 15 p ⁻ type semiconductor region 16 SOG film 17 silicon oxide film 18 silicon oxide film 19 contact hole 20 contact hole 21 plug 22 Silicon oxide film 23 Through hole 24 Contact hole 25 Contact hole 26 Ti film 27 TiSi ₂ film 28 TiN film 29 Tungsten film 30 Plug 31 First layer wiring 32 Lower electrode 33 Capacitive insulating film 34 Upper electrode 35 Plug 36 Second layer Eye wiring 37 Third layer wiring 38 Plug 39 Plug Qn N-channel MISFET Qp P-channel MISFET Qs MISFET for memory cell selection L Active area

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/10 451 H01L 27/10 451 27/108 621C 21/8242 651 21/8247 29/78 371 29/788 29 / 792 (72) Inventor Yoshitaka Nakamura 3-16-1, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Akira Sato 5-2-12-1 Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi ULSI Systems (reference) 4M104 BB01 BB04 BB06 BB18 BB20 BB25 BB26 BB27 BB30 BB40 CC01 CC05 DD16 DD19 DD21 DD37 DD43 DD78 DD84 FF18 FF22 GG16 HH15 5F001 AG09 AG17 AG08 JJ03H19HJ JJ23H19H JJ29 JJ30 JJ33 JJ34 KK01 KK08 NN06 NN07 NN40 PP04 PP06 PP15 QQ03 QQ09 QQ38 QQ48 QQ70 QQ73 QQ92 QQ93 QQ98 RR04 RR06 RR09 TT02 TT08 VV16 WW03 XX09 5F083 AD24 JA05 PR03 MA20

Claims (7)

[Claims] (A) forming a connection hole in an insulating film; (b) performing a first heat treatment after the step (a); and (c) forming a connection hole in the connection hole after the step (b). And (d) performing a second heat treatment at a temperature of 600 ° C. or higher after the step (c). 2. A step of forming a connection hole in an insulating film; a step of forming a first conductive film in the connection hole; and a step of forming the first conductive film in the connection hole. (D) after the step (a), performing a first heat treatment before the step (c), and (e) at 600 ° C. or higher after the step (c). Performing the second heat treatment of the above. 3. The method of manufacturing a semiconductor device according to claim 2, wherein after the step of forming the first conductive film, the process shifts to a step of forming a second conductive film without opening to the atmosphere. Device manufacturing method. 4. The method for manufacturing a semiconductor device according to claim 2, wherein said first conductor film is titanium nitride formed by a chemical vapor deposition method, and said second conductor film is a A method for manufacturing a semiconductor device, comprising tungsten formed by a vapor deposition method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the atmosphere of the first heat treatment is a reducing gas atmosphere or an inert gas atmosphere. Manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 1, wherein a processing temperature of the first heat treatment is 300 ° C. or higher. 7. The method of manufacturing a semiconductor device according to claim 1, wherein a lower semiconductor substrate is exposed from said connection hole in said step of forming said connection hole. Device manufacturing method.