JP2002076306A - Semiconductor integrated circuit and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent peel-off at the interface between a platinum-family metal film for composing the lower electrode of a capacitive element and a silicon oxide film. SOLUTION: On the inner wall of a groove 29 opened in the silicon oxide film 24, the lower electrode 32 of the capacitive element C for accumulating information is formed. At the interface between an Ru film 32a for composing the lower electrode 32 and the silicon oxide film 24, the bonding layer composed by a TaN film 30 is interposed for preventing the interface between the Ru film 32a and silicon oxide film 24 from peeling off when the dielectric film 34 deposited on the lower electrode 32 is heat-treated. Also, the upper end section of the TaN film 30 for composing the bonding layer is recessed to the lower portion than the opening end section of the groove 29, and is completely covered with the Ru film 32a for composing the lower electrode 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
(c) Random Access Memory).

[0002]

2. Description of the Related Art Generally, memory cells of a DRAM are arranged at intersections of a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. One memory cell is connected to one MISFET (Metal
Insulator Semiconductor Field Effect Transistor)
And one information storage capacitor (capacitor) connected in series to the MISFET.

A memory cell selecting MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate insulating film, a gate electrode integrally formed with a word line, and a pair of semiconductors forming a source and a drain. It is composed of regions. MISFET for memory cell selection
Usually, two are formed in one active region, and these two MIs
One of the source and the drain (semiconductor region) of the SFET is shared in the center of the active region.

The bit line is connected to the memory cell selecting MIS.
It is arranged above the FET and is electrically connected to one of a source and a drain (semiconductor region) (a semiconductor region shared by two MISFETs) through a connection hole in which a plug made of polycrystalline silicon or the like is embedded. The information storage capacitor is disposed above the bit line, and is electrically connected to the other of the source and drain (semiconductor region) of the memory cell selection MISFET through a connection hole in which a plug made of polycrystalline silicon or the like is embedded. Connected to.

As described above, in recent DRAMs, as a countermeasure to compensate for the decrease in the amount of stored charge due to the miniaturization of memory cells,
A three-dimensional structure in which an information storage capacitor is arranged above a bit line is employed. However, in the case of a large-capacity DRAM of 256 megabits or more, in which the miniaturization of memory cells is further advanced, it is considered that it is difficult to compensate for a decrease in the amount of stored charges only by making the information storage capacitor three-dimensional.

Therefore, tantalum oxide (Ta ₂ O ₅ ), strontium titanate (STO), and barium strontium titanate (B) are used as the dielectric film of the information storage capacitor.
The use of a high dielectric (ferroelectric) material such as ST) has been studied. That is, since tantalum oxide has a relative dielectric constant of about 40 and STO and BST of about 200 to 500, these high (ferro) dielectric materials can be used as a dielectric film to form silicon nitride (relative dielectric constant). = 7
This is because a large increase in the amount of stored charges can be expected as compared with the case where the above-described (8) and the like are used for the dielectric film.

However, these high (ferro) dielectric materials are:
Simply forming a film does not provide a high relative dielectric constant and a large leak current. Therefore, it is necessary to improve crystallization and film quality by performing a heat treatment in an oxygen atmosphere at 750 ° C. or more after the film formation. There is. Therefore, when a high (ferro) dielectric material is used for the dielectric film of the information storage capacitor element, there arises a problem such as a change in the characteristics of the MISFET due to the high-temperature heat treatment.

Therefore, when a high (ferro) dielectric material is used for the dielectric film, a platinum group metal such as Ru (ruthenium), Pt (platinum), and Ir (iridium) is used for the lower electrode serving as a base. Is done. When a high (ferro) dielectric film is deposited on these metal surfaces,
Since the crystallization of the film and the improvement of the film quality can be achieved by a heat treatment at a temperature lower by 100 ° C. or more than the ordinary heat treatment such as the temperature of ℃, the amount of heat treatment in the whole manufacturing process can be reduced, and the characteristic fluctuation of the MISFET can be prevented.

[0009]

SUMMARY OF THE INVENTION
In developing a mega-bit DRAM or later, a thick silicon oxide film is deposited on top of a bit line, and then the silicon oxide film is etched to form a deep groove, and then a platinum group metal film is deposited on the inner wall of the groove. We are now studying a process to form a lower electrode with a large surface area.

However, a platinum group metal such as Ru generally has poor adhesion to an insulating film such as silicon oxide. Therefore, in a heat treatment step after a high (ferro) dielectric film is deposited on a lower electrode, a metal film is used. When a volume change occurs in
There is a problem that separation easily occurs at the interface with the silicon oxide film. Therefore, in a DRAM having a capacitor in which the dielectric film is made of a high (ferro) dielectric material and the underlying electrode is made of a platinum group metal such as Ru, Pt or Ir, a platinum group metal film and a silicon oxide It is essential to take measures to prevent separation at the interface with the film.

Japanese Patent Application No. 12-63735 filed in Japan by the same applicant as the present invention as a technique for solving the above-mentioned problem.

An object of the present invention is to provide a technique for improving the adhesion between a platinum group metal film and a silicon oxide film constituting a lower electrode of a capacitor.

Another object of the present invention is to increase a surface area of a capacitive element and increase a dielectric constant of a dielectric film, thereby ensuring a desired value of accumulated charge even when a memory cell is miniaturized. It is to provide the technology that can do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a semiconductor integrated circuit device according to the present invention, a capacitive element comprising a first electrode, a dielectric film and a second electrode is formed inside a groove or hole formed in an insulating film on a main surface of a semiconductor substrate. A TaN layer is interposed between the side wall of the groove or hole and the first electrode.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, an insulating film is formed on a main surface of a semiconductor substrate, a groove or a hole is formed in the insulating film, and a T or T is formed on a sidewall of the groove or the hole.
The method includes a step of forming an aN layer, and a step of forming a capacitive element including a first electrode made of a metal film, a dielectric film, and a second electrode on the TaN layer.

According to the above-described means, it is possible to prevent a problem that the first electrode is separated from the insulating film when the dielectric film of the capacitor is subjected to a high-temperature heat treatment.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a first insulating film is formed on a main surface of a semiconductor substrate, and a plurality of grooves or holes are formed in the first insulating film. Forming a TaN layer on the side wall of the hole, selectively removing the TaN film on the first insulating film by dry etching in an atmosphere containing chlorine, Forming a capacitive element comprising a first electrode made of a metal film, a dielectric film and a second electrode.

According to the above-described means, the first etching is performed by dry-etching the TaN film in an atmosphere containing chlorine.
Since the etching selectivity of the TaN film with respect to the insulating film is increased, the loss of the first insulating film that occurs when the TaN film is etched can be reduced.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG.
FIG. 2 is an overall plan view of a silicon chip 1A on which a RAM is formed. On the main surface of the rectangular silicon chip 1A, for example, 2
A DRAM having a storage capacity of 56 Mbit (megabit) to 1 Gbit (gigabit) is formed. This DRAM
Is composed of a storage section divided into a plurality of memory arrays (MARY) and a peripheral circuit section (PC) arranged around the storage section. At the center of the main surface of the silicon chip 1A, control circuits such as a word driver WD and a data line selection circuit, input / output circuits, bonding pads BP, and the like are arranged. A sense amplifier SA is arranged between the memory arrays (MARY).

The memory array (MARY) is composed of a plurality of word lines and bit lines arranged in a matrix and a plurality of memory cells arranged at intersections thereof. 2 and 3 are cross-sectional views of a silicon substrate (hereinafter, simply referred to as a substrate) 1 showing a part of a memory array (MARY) of a DRAM.

One memory cell for storing one bit of information is composed of one memory cell selecting MISFET Qs formed in the p-type well 3 of the substrate 1 and one information storing serially connected thereto. And a capacitance element (capacitor) C. The memory cell selecting MISFET Qs mainly includes a gate electrode 6 (word line WL), a source and a drain (n-type semiconductor region 8), and a gate insulating film 5 not shown in these figures. One of the source and drain (n-type semiconductor region 8) of the memory cell selection MISFET Qs is electrically connected to the information storage capacitor C, and the other is electrically connected to the bit line BL.

As shown in the figure, the memory cell includes an information storage capacitor C, which is an information storage capacitor, and a memory cell selection M.
A stacked capacitor structure arranged above the ISFET Qs is employed. The information storage capacitor C includes a lower electrode (storage node) 32 made of a metal containing Ru (ruthenium) as a main component;
A dielectric film 34 formed on the lower electrode 32 and containing Ta ₂ O ₅ (tantalum oxide) as a main component;
And an upper electrode (plate electrode) 35 made of a metal containing a Ru film and a W (tungsten) film as main components. The information storage capacitor C is formed inside a high aspect ratio groove 29 formed in the thick silicon oxide film 24 on the upper part of the memory cell selection MISFET Qs.

The lower electrode 32 of the information storage capacitor C and one of the source and drain (n-type semiconductor region 8) of the memory cell selecting MISFET Qs are connected to the contact hole 12
And is electrically connected through a through hole 19 on the upper portion thereof. Plugs 13 and 22 made of a polycrystalline silicon film are embedded in each of contact hole 12 and through hole 19.

At the interface between the lower electrode 32 of the information storage capacitive element C and the plug 22 embedded in the through hole 19 below it, Ru and the plug 22 forming the lower electrode 32 are disposed.
A barrier layer 25 made of TaN (tantalum nitride) or the like is formed in order to prevent an undesired silicide reaction from being caused by the heat treatment performed during the manufacturing process with the polycrystalline silicon constituting. Also, the lower electrode 32
A TaN film 30 is formed on the inner wall of the groove 29 in which the TaN film 30 is formed as an adhesive layer for preventing separation of Ru constituting the lower electrode 32 and the silicon oxide film 24.

Next, a method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to FIGS. In the DRAM manufacturing process described below, a memory cell selecting MISFET Qs is formed on the main surface of the substrate 1, and then a bit line BL is formed on the memory cell selecting MISFET Qs.
The steps up to the formation of
No. 166320 (Matsuoka et al.) Has a detailed description. Therefore, in the present embodiment, the outline of the steps up to the formation of the bit line BL will be described, and the steps of manufacturing the information storage capacitor C, which is a main component, will be described in detail. Note that the steps up to the formation of the bit line BL are not limited to the steps described below.

First, FIG. 4 (a plan view of a main part of the memory array), FIG. 5 (a cross-sectional view along the line AA in FIG. 4), FIG.
As shown in FIG. 4 (cross-sectional view along line BB in FIG. 4) and FIG. 7 (cross-sectional view along line CC in FIG. 4), the main surface of the substrate 1 made of, for example, p-type single crystal silicon The element isolation groove 2 is formed in the element isolation region. The element isolation groove 2 is formed by etching the surface of the substrate 1 to form a groove having a depth of about 300 to 400 nm. Then, the CVD (C) is formed on the substrate 1 including the inside of the groove.
After depositing a silicon oxide film 4 (thickness of about 600 nm) by a chemical vapor deposition (chemical vapor deposition) method, the silicon oxide film 4 is subjected to chemical mechanical polishing (CMP).
It is formed by polishing and flattening by a method. The silicon oxide film 4 is deposited by a plasma CVD method using, for example, oxygen (or ozone) and tetraethoxysilane (TEOS) as a source gas, and then is subjected to dry oxidation at about 1000 ° C. to densify the film (densification). ).

As shown in FIG. 4, by forming the element isolation grooves 2, a large number of elongated island-shaped active regions (L) surrounded by the element isolation grooves 2 are simultaneously formed. As described later, each of these active regions (L) is formed with two memory cell selecting MISFETs Qs sharing one of a source and a drain.

Next, a p-type well 3 is formed by ion-implanting B (boron) into the substrate 1 and then p-type well 3 is formed.
After cleaning the surface of the p-type well 3 with a HF (hydrofluoric acid) -based cleaning solution, the substrate 1 is thermally oxidized to form a silicon oxide-based clean gate insulating film 5 on the surface of the active region (L) of the p-type well 3. (Thickness: about 6 nm). Note that the gate insulating film 5 is not only a silicon oxide-based insulating film formed by thermal oxidation of the substrate 1, but also a silicon nitride-based insulating film and a metal oxide-based insulating film (a tantalum oxide film, an oxide Titanium film). These high dielectric insulating films are formed on the substrate 1 by a CVD method or a sputtering method.

Next, as shown in FIGS. 8 to 10, a gate electrode 6 is formed on the gate insulating film 5. The gate electrode 6 is connected to the word line (WL) in a region other than the active region (L).
Function as The gate electrode 6 (word line WL) is made of, for example, an n-type polycrystalline silicon film (about 70 nm thick) doped with P (phosphorus) or the like on the gate insulating film 5, WN
(Tungsten nitride) or TiN (titanium nitride) barrier metal film (about 5 nm to 10 nm thick), W
After sequentially depositing a (tungsten) film (thickness of about 100 nm) and a silicon nitride film 7 (thickness of about 150 nm), these films are formed by dry etching using a photoresist film as a mask. The polycrystalline silicon film and the silicon nitride film 7 are deposited by a CVD method, and the barrier metal film and the W film are deposited by a sputtering method.

Next, as shown in FIGS. 11 to 13, As (arsenic) or P (phosphorus) is ion-implanted into the p-type well 3 to form an n-type semiconductor region in the p-type well 3 on both sides of the gate electrode 6. 8 (source, drain) is formed. Through the steps so far, the memory cell selecting MISFET Qs is substantially completed.

Next, as shown in FIGS. 14 to 17, a silicon nitride film 9 (thickness: 50 nm) and a silicon oxide film 10 (thickness: approximately 600 nm) are deposited on the substrate 1 by the CVD method. After the surface of the silicon film 10 is flattened by a chemical mechanical polishing method, the silicon oxide film 10 and the silicon nitride film 9 are dry-etched using a photoresist film (not shown) as a mask, thereby forming a memory cell selecting M.
Contact holes 11 and 12 are formed above the source and drain (n-type semiconductor region 8) of ISFET Qs.
The etching of the silicon oxide film 10 is performed under the condition that the selectivity to silicon nitride is large, and the etching of the silicon nitride film 9 is performed under the condition that the etching selectivity to silicon or silicon oxide is large. Thereby, the contact holes 11 and 12 can be formed by self-alignment (self-alignment) with the gate electrode 6 (word line WL).

Next, as shown in FIGS. 18 and 19,
A plug 13 is formed inside the contact holes 11 and 12. To form the plug 13, the silicon oxide film 10
P-doped n-type polycrystalline silicon film on top of
Contact holes 11 and 12
After the n-type polycrystalline silicon film is embedded in the inside of the substrate, the n-type polycrystalline silicon film outside the contact holes 11 and 12 is removed by a chemical mechanical polishing method (or dry etching).

Next, CVD is performed on the silicon oxide film 10.
After depositing a silicon oxide film 14 (having a thickness of about 150 nm) by a method, as shown in FIGS. 20 to 22, a photoresist film (not shown) is used as a mask to form the silicon oxide film 14 over the contact hole 11. By dry etching, a through hole 15 for connecting a bit line (BL) formed in a later step and the contact hole 11 is formed.
To form

Next, as shown in FIGS. 23 and 24,
A plug 16 is formed inside the through hole 15. In order to form the plug 16, a barrier metal film made of TiN is deposited on the silicon oxide film 14 by, for example, a sputtering method, and then W is deposited on the barrier metal film by a CVD method.
After embedding these films inside the through holes 15 by depositing films, these films outside the through holes 15 are removed by chemical mechanical polishing.

Next, as shown in FIGS. 25 to 28, a bit line BL is formed on the silicon oxide film 14. In order to form the bit line BL, for example, a TiN film (about 10 nm thick) is deposited on the silicon oxide film 14 by a sputtering method, and then a W film (about 50 nm thick) is formed on the TiN film by a CVD method. Are deposited, these films are dry-etched using the photoresist film as a mask. The bit line BL is connected to the source / drain (n-type semiconductor region 8) of the memory cell selection MISFET Qs via the plug 16 embedded in the lower through hole 15 and the plug 13 embedded in the lower contact hole 11. Is electrically connected to one of them.

Next, as shown in FIGS. 29 to 32, a silicon oxide film 17 having a thickness of about 300 nm and a silicon nitride film 18 having a thickness of about 200 nm are deposited on the bit line BL by CVD. Resist film (not shown)
The silicon nitride film 18 and the silicon oxide film 17 are dry-etched using
A through hole 19 is formed above the contact hole 11 in which is embedded.

The through hole 19 is formed such that its diameter is smaller than the diameter of the contact hole 11 below it. Specifically, the CVD is performed on the silicon nitride film 18.
After a polycrystalline silicon film 20 is deposited by a method and a hole is formed by dry-etching the polycrystalline silicon film 20 in a region where a through hole 19 is to be formed, the polycrystalline silicon film 20 is formed.
A polycrystalline silicon film (not shown) is further deposited on the upper surface. Next, a sidewall spacer 21 is formed on the side wall of the hole by anisotropically etching the polycrystalline silicon film on the polycrystalline silicon film 20. Subsequently, the polycrystalline silicon film 20 and the sidewall spacer 21 are masked. The silicon nitride film 18 and the silicon oxide film 17 at the bottom of the hole are dry-etched.

As shown in FIGS. 29 and 32,
The center of the through hole 19 is offset from the center of the lower contact hole 11 in a direction away from the bit line BL. As described above, the diameter of the through hole 19 is made smaller than the diameter of the contact hole 11 thereunder, and the center thereof is offset in a direction away from the bit line BL, so that even when the memory cell size is reduced, self-alignment is achieved. Contact (Self Align Contac
t; SAC) without using the through hole 19
(A plug 22 embedded inside) and the bit line BL can be prevented from being short-circuited. Further, by making the diameter of the through hole 19 smaller than the diameter of the contact hole 11 therebelow, a sufficient contact area between them can be ensured even if their centers are shifted.

Next, after the mask (polycrystalline silicon film 20 and side wall spacer 21) used for forming through hole 19 is removed by dry etching, the inside of through hole 19 is removed as shown in FIGS. The plug 22 is formed. To form the plug 22, first, a P-doped n-type polycrystalline silicon film is deposited on the silicon nitride film 18 by a CVD method to bury the polycrystalline silicon film in the through hole 19, and then, The polycrystalline silicon film outside the through hole 19 is removed by a chemical mechanical polishing method (or dry etching). At this time, the height of the surface of the plug 22 is lowered below the upper end of the through hole 19 by overpolishing (or overetching) the polycrystalline silicon film.

Next, as shown in FIGS. 35 and 36,
A barrier layer 25 is formed on the plug 22. To form the barrier layer 25, a TaN film is deposited on the silicon nitride film 18 by a sputtering method, and then the TaN film outside the through hole 19 is removed by a chemical mechanical polishing method (or dry etching). The barrier layer 25 is formed in order to prevent an undesired silicide reaction between Ru forming the lower electrode 32 and polycrystalline silicon forming the plug 22 by a heat treatment performed during a manufacturing process described later.

Next, as shown in FIGS. 37 and 38,
A silicon oxide film 24 is deposited on the silicon nitride film 18 by a CVD method. Lower electrode 32 of information storage capacitor C
Is a groove 29 formed in the silicon oxide film 24 in the next step.
Is formed inside. Accordingly, since the thickness of the silicon oxide film 24 defines the height of the lower electrode 32, in order to increase the surface area of the lower electrode 32 and increase the amount of accumulated charges, the silicon oxide film 24 must be formed as a thick film of about 2 μm. Deposit thick. The silicon oxide film 24 is deposited by a plasma CVD method using, for example, oxygen and tetraethoxysilane (TEOS) as a source gas, and then, if necessary, its surface is flattened by a chemical mechanical polishing method.

Next, as shown in FIGS. 39 and 40,
The film thickness 2 is formed on the silicon oxide film 24 by a sputtering method.
After a W film 26 having a thickness of about 00 nm is deposited and an antireflection film 27 is applied on the W film 26, a photoresist film 28 is formed on the antireflection film 27. The W film 26 is used as a mask for etching the thick silicon oxide film 24 because the W film 26 has a larger etching selectivity to the silicon oxide film 24 than the photoresist film.

Next, as shown in FIGS. 41 and 42,
A mask pattern for etching the silicon oxide film 24 by dry-etching the anti-reflection film 27 using the photoresist film 28 as a mask and then dry-etching the W film 26 as shown in FIGS. (W film 28) is formed.

Next, after removing the photoresist film 28 and the antireflection film 27, the silicon oxide film 24 is dry-etched using the W film 28 as a mask, as shown in FIGS. Then, a deep groove 29 exposing the surface of the barrier layer 25 in the through hole 19 is formed. For forming the groove 29, for example, C ₅ F ₈ + O ₂ + Ar
The silicon oxide film 24 is anisotropically dry-etched using a parallel plate type reactive ion etching apparatus using (argon) gas as an etching gas. As shown in FIG. 47, the trench 29 is formed of a rectangular planar pattern having a long side in the extending direction of the word line WL and a short side in the extending direction of the bit line BL.

Although not particularly limited, in this embodiment,
The silicon oxide film 24 is dry etched to form the groove 29
Is formed, a hydrofluoric acid-based etchant (HF: NH ₄
F = 1: 200), the silicon oxide film 24 on the inner wall of the groove 29 is wet-etched. By performing this wet etching, the inner wall of the groove 29 is isotropically etched, and the diameter of the groove 29 is slightly increased.
As shown in FIG. 8 and FIG. 49, the silicon oxide film 24 between the lower end of the side wall of the groove 29 and the bottom surface (region indicated by the arrow in the figure) is rounded. In order to effectively add this roundness, the silicon oxide film 24 is dry-etched to form the groove 29.
When forming the trench 29, the diameter near the bottom of the groove 29 is made smaller in advance than the upper diameter by reducing the etching amount at the bottom of the groove 29, and then the silicon oxide film 24 on the inner wall of the groove 29 is wet-etched. Good to do.

As described above, by rounding the silicon oxide film 24 between the lower end portion of the side wall and the bottom surface portion of the groove 29, an adhesive layer (T) deposited inside the groove 29 in a later step is formed.
Even when the volume of the aN film 30) or the lower electrode material (Ru film 32a) changes due to the subsequent heat treatment, the separation does not occur in the region between the lower end of the sidewall of the groove 29 and the bottom surface.

Next, after removing the W film 26 used as an etching mask for the silicon oxide film 24 with a hydrogen peroxide solution, the silicon oxide film 24 including the inside of the groove 29 is removed as shown in FIGS. On top, T with a thickness of about 15 nm
An aN film 30 is deposited by a sputtering method. TaN film 3
No. 0 has a feature that it has a high adhesiveness to both the lower electrode material (Ru film 32a) and the silicon oxide film 24 deposited in the groove 29 in a later step, and therefore, the lower electrode material (Ru film 32a ) And the silicon oxide film 24 function as an adhesive layer for preventing separation at the interface.

Next, as shown in FIGS. 52 and 53,
After depositing the insulating film 31 inside the groove 29, the TaN film 30 outside the groove 29 is removed by dry etching.
Since the insulating film 31 is used as a mask for preventing the TaN film 30 at the bottom of the groove 29 from being etched by etching ions, it is not necessary to embed the insulating film 31 in the entire inside of the groove 29, and the film covers at least the vicinity of the bottom of the groove 29. What is necessary is just to deposit in thickness. The insulating film 31 is made of, for example, a photoresist or spin-on-glass. When the insulating film 31 is made of a photoresist, a positive photoresist film is formed in the groove 29.
After the spin coating is performed on the silicon oxide film 24 including the inside of the groove 29, the entire surface is exposed and developed to remove the exposed portion outside the groove 29 and leave the unexposed portion inside the groove 29.

FIG. 54 (a) is an enlarged view of the upper end portion of the side wall of the groove 29. As shown, the TaN film 3 outside the groove 29
When removing 0 by dry etching, the TaN film 30 at the upper end of the side wall of the groove 29 is also removed, and the upper end of the TaN film 30 is recessed (recessed) below the opening end of the groove 29 and is tapered. Process into The recess amount at the upper end of the TaN film 30 is, eg, about 100 nm, and the taper angle (θ) is, eg, 45 ° or less. Further, in order to secure a sufficient etching selectivity of the TaN film 30 with respect to the silicon oxide film 24, a gas for etching the TaN film 30 is chlorine gas or a mixed gas of chlorine gas and Ar (argon).

Next, after the insulating film 31 inside the groove 29 is removed by ashing or the like, as shown in FIGS. 55, 56 and 54B, the silicon oxide film 24 including the inside of the groove 29 is removed. A Ru film 32a is deposited on the upper part. Ru
The film 32a has a thickness of 15 nm deposited by a sputtering method.
It is composed of a laminated film of a film having a thickness of about 35 nm and a film having a thickness of about 35 nm deposited by the CVD method. Ru deposited by sputtering
The film is characterized in that it has better adhesion to the silicon oxide film 24 than the Ru film deposited by the CVD method. On the other hand, CV
Since the Ru film deposited by the method D has better step coverage than the Ru film deposited by the sputtering method, the bottom and side walls of the deep groove 29 can be covered with a substantially uniform film thickness.

Next, after performing a heat treatment at 700 ° C. for about 1 minute to densify (densify) the Ru film 32a, FIG.
As shown in FIG. 7 and FIG.
3 is buried, and the Ru film 32a outside the groove 29 is removed by dry etching. The insulating film 33 is used as a mask for preventing the Ru film 32a at the bottom of the groove 29 from being etched by etching ions, and is made of, for example, a photoresist or spin-on glass.

As described above, in this embodiment, TaN
The upper end of the film 30 is recessed below the opening end of the groove 29. Therefore, as shown in the enlarged view of FIG. 54C, when the Ru film 32a outside the groove 29 is removed, the groove 29 is removed.
The TaN film 30 is not exposed at the upper end of the Ru film 32a remaining on the side wall of the substrate. Further, since the upper end of the TaN film 30 is processed into a tapered shape, the thickness of the Ru film 32a does not become thin near the upper end of the TaN film 30.

Next, as shown in FIGS. 59 and 60,
The insulating film 33 embedded in the groove 29 is removed by ashing or the like. By the steps so far, the groove 29
Electrode 32 composed of a Ru film 32a on the inner wall of
Is formed. The lower electrode 32 is electrically connected to the other one of the n-type semiconductor regions 8 (source and drain) of the memory cell selecting MISFET Qs through the lower through hole 19 and the lower contact hole 12.

Next, as shown in FIGS. 61 and 62,
The inner wall of the groove 29 where the lower electrode 32 is formed and the surface of the silicon oxide film 24 have a thickness of 10 nm made of tantalum oxide.
A degree of dielectric film 34 is deposited. The tantalum oxide film is formed, for example, by using pentaethoxy tantalum (Ta (OC ₂
H _{5) 5)} and with oxygen, the temperature 430 ° C., the pressure 50Pa
Then, a heat treatment of about 650 ° is performed in an oxygen atmosphere in order to achieve crystallization of the film and improvement of the film quality.

In this embodiment, the upper end of the TaN film 30 is recessed below the opening end of the groove 29, and the TaN film 3
0 is completely covered with the Ru film 32a.
As shown in FIG. 3D, when the dielectric film 34 made of tantalum oxide is deposited on the inner wall of the groove 29 and the surface of the silicon oxide film 24, the TaN film 30 and the dielectric film 34 come into contact with each other. There is no.

Thus, when the tantalum oxide film is heat-treated in an oxygen atmosphere, oxygen in the tantalum oxide film does not diffuse into the TaN film 30, so that the shape abnormality caused by oxidation of the TaN film 30 ( Blistering) and peeling at the interface with the silicon oxide film 24 can be prevented. In addition, it is possible to prevent an increase in leakage current due to the reduction of the tantalum oxide film to metal tantalum having conductivity.

Next, as shown in FIGS. 63 and 64,
A Ru film 35a having a thickness of about 100 nm is deposited on the dielectric film 34 by a sputtering method and a CVD method.
65 and 66 after depositing about m of the W film 35b.
As shown in (1), the upper electrode 35 is formed by removing the W film 35b and the Ru film 35a in a region other than the memory array (MARY) by dry etching using the photoresist film 36 as a mask. When performing this etching, as shown in FIG. 65, it is preferable to process the end of the photoresist film 35 into a round shape. This makes it difficult for the reaction product of the etching to adhere to the end side walls of the W film 35b and the Ru film 35a, thereby improving the etching controllability of these films.

By the steps up to this point, the information storage capacitor C composed of the lower electrode 32, the dielectric film 34 and the upper electrode 35 is completed, and the memory cell selection as shown in FIGS. A memory cell composed of the MISFET Qs for use and the information storage capacitor C connected in series to the MISFET Qs is substantially completed.

Thereafter, about two layers of Al wiring are formed above the information storage capacitive element C with an interlayer insulating film interposed therebetween, and a passivation film is formed above the uppermost Al wiring.
Illustration of these is omitted.

As described above in detail, according to the present embodiment, when the lower electrode 32 of the information storage capacitor C is formed on the inner wall of the groove 29 formed in the silicon oxide film 24, the lower electrode 32 is formed. Ru film 32a and silicon oxide film 2
By interposing an adhesive layer composed of the TaN film 30 at the interface with the film 4, the peeling of the Ru film 32a can be reliably prevented.

The groove 2 formed in the silicon oxide film 24
An adhesive layer (TaN film 30) deposited inside the groove 29 by rounding between the lower end portion of the side wall and the bottom surface portion 9
Even when the volume of the lower electrode material (Ru film 32 a) changes due to the subsequent heat treatment, separation does not occur in the region between the lower end of the side wall of the groove 29 and the bottom surface.

Also, the upper end of the TaN film 30 constituting the adhesive layer is recessed below the opening end of the groove 29, and
By completely covering the N film 30 with the Ru film 32a, Ta
Since the contact between the N film 30 and the dielectric film 34 can be reliably prevented, the abnormal shape (bulging) and peeling of the TaN film 30 can be prevented, and an increase in the leak current of the dielectric film 34 can be prevented. can do.

The material of the lower electrode of the information storage capacitor C is not limited to Ru used in the present embodiment, but may be Ru, such as Pt (platinum) or Ir (iridium).
It can also be composed of other platinum group metals. When Ru used in the present embodiment is heat-treated in an excessive oxidizing atmosphere, Ru itself is oxidized to form ruthenium oxide,
Pt has the advantage that it does not form such oxides, although problems may occur in later steps.

The material of the dielectric film of the information storage capacitor C is not limited to the tantalum oxide used in the present embodiment, but may be barium titanate, strontium titanate, barium strontium titanate, or lead titanate. And a high (ferro) dielectric made of a perovskite-type metal oxide such as lead zirconate titanate or a laminate thereof. Even when these high (ferro) dielectric materials are used, a heat treatment step of crystallizing or modifying the film after film formation is essential, and the same effects as those of the embodiment using tantalum oxide can be obtained.

Further, the material of the upper electrode of the information storage capacitor C is not limited to the laminate of Ru and W used in the present embodiment, but may be a metal such as W, Ru, Pt, Ir or the like. And a laminate of the above metal and TiN.

(Embodiment 2) In the manufacturing method of this embodiment, a groove 29 is formed in a silicon oxide film
The TaN film 3 is formed on the silicon oxide film 24 including the inside of
Since the steps up to depositing 0 (the steps in FIGS. 4 to 51) are the same as those in the first embodiment, description thereof will be omitted, and only the subsequent steps will be described.

First, following the step shown in FIG. 51, as shown in FIG. 67, an insulating film 31 is deposited inside the groove 29, and the TaN film 30 outside the groove 29 is removed by dry etching. As the etching gas, chlorine gas or a mixed gas of chlorine gas and Ar (argon) is used.

Next, after the insulating film 31 inside the trench 29 is removed by ashing or the like, as shown in FIG. 68, a Ru film 32b is formed on the surface of the TaN film 30 remaining inside the trench 29. The Ru film 32b is formed by a selective CVD method utilizing the property that Ru selectively grows on the surface of a metal and does not grow on the surface of an insulating film such as silicon oxide. Through the steps so far, the lower electrode 32 composed of the Ru film 32b is formed on the inner wall of the groove 29.

Next, as shown in FIG.
A dielectric film 34 of tantalum oxide is deposited on the inner wall of the groove 29 in which is formed and the surface of the silicon oxide film 24 in the same manner as in the first embodiment, and subsequently, the film is crystallized and the film quality is improved. Is performed in an oxygen atmosphere at about 650 °.

Here, the relationship between the etching amount of the TaN film 30 performed in the step shown in FIG. 67 and the characteristics of the dielectric film 34 will be described with reference to FIG.

FIG. 70A shows that when the TaN film 30 outside the trench 29, that is, the TaN film 30 on the silicon oxide film 24 is removed by dry etching, the underlying silicon oxide film 24 is removed.
Is selected, and the upper surface of the silicon oxide film 24 is etched to some extent. In this case, the groove 29
The upper end of the TaN film 30 remaining inside the silicon oxide film 24 projects above the upper surface of the silicon oxide film 24.

In this state, the Ru film 3 is formed on the surface of the TaN film 30.
When 2b is selectively grown, the Ru film 32b selectively grown on the upper end of the TaN film 30 projects above the upper surface of the silicon oxide film 24. Therefore, the electric field concentrates in this region, and the leakage current of the dielectric film 34 deposited thereafter increases in this region.

FIG. 70 (b) shows a case where the TaN film 30 is etched so that the upper end thereof is at the same height as the upper surface of the silicon oxide film 24. Also in this case, the Ru film 32b selectively grown on the upper end of the TaN film 30 is
Is projected above the upper surface of the dielectric film 34, and the leakage current of the dielectric film 34 deposited thereafter increases in this region.

FIG. 70C shows the case where the etching is performed so that the upper end of the TaN film 30 is recessed below the upper surface of the silicon oxide film 24. The recess amount here is R
The thickness is approximately equal to the thickness (for example, 50 nm) of the u film 32b.

In this case, the upper end of the Ru film 32b selectively grown on the upper end of the TaN film 30 has the same height as the upper surface of the silicon oxide film 24 and does not protrude upward. Therefore, since the electric field does not concentrate on the upper end of the Ru film 32b, the leakage current of the subsequently deposited dielectric film 34 does not increase in this region.

FIG. 70 (d) shows the same Ta value as in FIG.
In this case, the etching is performed so that the upper end of the N film 30 is recessed below the upper surface of the silicon oxide film 24. The recess amount is set to be equal to or larger than the thickness of the Ru film 32b. In this case, the electric field does not concentrate on the upper end of the Ru film 32b selectively grown on the upper end of the TaN film 30, as in FIG. It does not increase in the area. However, the TaN film 30
Is increased, the recess amount of the Ru film 32b selectively grown on the surface of the TaN film 30 is increased.
The surface area of the lower electrode 32 constituted by the Ru film 32b decreases, and the amount of charge stored in the information storage capacitor C decreases accordingly.

As described above, when etching the TaN film 30 in the step shown in FIG. 67, the upper end of the TaN film 30 is positioned lower than the upper surface of the silicon oxide film 24 from the viewpoint of reducing the leakage current. Need to be recessed. At this time, the recess amount of the TaN film 30 is at least TaN.
The amount by which the upper end of the Ru film 32b selectively grown on the upper end of the film 30 does not protrude above the upper surface of the silicon oxide film 24, that is, the Ru which is selectively grown on the surface of the TaN film 30.
The thickness is set to be equal to or larger than the thickness of the film 32b. On the other hand, from the viewpoint of minimizing the decrease in the accumulated charge amount, the upper limit of the recess amount is determined by the Ru film 3.
3b or less, more preferably 2 times or less (Ru
When the thickness of the film 32b is 50 nm, it is preferable that the thickness be 100 nm or less.

Thereafter, as shown in FIG. 71, the dielectric film 3 is formed in accordance with the steps shown in FIGS.
By forming the upper electrode 35 on the upper part of 4, the information storage capacitance element C constituted by the lower electrode 32, the dielectric film 34 and the upper electrode 35 is completed, and is connected in series with the memory cell selecting MISFET Qs. A memory cell composed of the information storage capacitor C thus completed is substantially completed.

According to the present embodiment, the same effects as in the first embodiment can be obtained, and in addition, the silicon oxide film 24
The number of steps of embedding the insulating film in the groove 29 formed in the first embodiment is reduced from two times in the first embodiment to one time, and the step of etching the Ru film 32b is not required.
The manufacturing process of M can be shortened.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

In the first and second embodiments, as a method for preventing the contact between the adhesive layer (TaN film 30) for preventing separation of the lower electrode and the dielectric film, the TaN film 3 forming the adhesive layer is used.
0 to recess (Embodiment 1) or TaN
Although the method (Embodiment 2) of selectively growing the lower electrode material on the surface of the film 30 is used, these methods can be applied to the case where a material other than TaN, for example, TiN or Ti is used as the adhesive layer. it can.

In the first and second embodiments, the case where the present invention is applied to a DRAM and its manufacturing process has been described. However, the present invention can be applied not only to a general-purpose DRAM, but also to a logic embedded DRAM, an FeRAM, or the like.

[0086]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) According to the present invention, even when the miniaturization of the memory cell further advances and the misalignment between the lower electrode of the capacitive element and the connection hole thereunder becomes unavoidable, the inside of the connection hole is patterned when the lower electrode is patterned. Can prevent the problem that the surface of the silicon plug is exposed by etching the barrier layer. (2) According to the present invention, when a dielectric film formed on a lower electrode of a capacitor is subjected to a heat treatment in an oxygen atmosphere, oxygen transmitted through the lower electrode oxidizes the barrier layer itself, resulting in high resistance and low dielectric constant. The problem of forming an oxide layer with a high efficiency can be prevented. (3) According to the present invention, the adhesiveness between the platinum group metal film and the silicon oxide film constituting the lower electrode of the capacitor can be improved. (4) According to the present invention, by increasing the surface area of the capacitive element and increasing the dielectric constant of the dielectric film, a desired accumulated charge amount value can be secured even when the memory cell is miniaturized. .

[Brief description of the drawings]

FIG. 1 is an overall plan view of a silicon chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate on which a DRAM according to an embodiment of the present invention is formed.

FIG. 3 is a sectional view of a main part of a semiconductor substrate on which a DRAM according to an embodiment of the present invention is formed.

FIG. 4 is a plan view of a main part of a semiconductor substrate, illustrating a method for manufacturing a DRAM according to an embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a plan view of a principal part of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 14 is a fragmentary plan view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 20 is a plan view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a DRAM according to an embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 22 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 25 is a main-portion plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 29 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing a DRAM according to an embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 32 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 37 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 39 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 40 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 41 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 42 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 43 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 44 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 45 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 46 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 47 is a main part plan view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 48 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 49 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 50 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 51 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 52 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 53 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 54 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 55 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 56 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 57 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 58 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 59 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 60 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 61 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 62 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 63 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 64 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 65 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 66 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 67 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;

FIG. 68 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;

FIG. 69 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;

FIG. 70: Etching shape of TaN film, selective CVD-R
FIG. 4 is a diagram illustrating the shape of a u film and characteristics of a tantalum oxide film.

FIG. 71 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 1A silicon chip 2 element isolation groove 3 p-type well 4 silicon oxide film 5 gate insulating film 6 gate electrode 7 silicon oxide film 8 n-type semiconductor region (source, drain) 9 silicon nitride film 10 silicon oxide film 11, 12 Contact hole 13 Plug 14 Silicon oxide film 15 Through hole 16 Plug 17 Silicon oxide film 18 Silicon nitride film 19 Through hole 20 Polycrystalline silicon film 21 Side wall spacer 22 Plug 24 Silicon oxide film 25 Barrier layer 26 W film 27 Anti-reflection film 28 Photoresist film 29 Groove 30 TaN film (adhesive layer) 31 Photoresist film 32 Lower electrode (storage node) 32a, 32b Ru film 33 Photoresist film 34 Dielectric film 35 Upper electrode (plate electrode) 35a Ru film 3 b W film 36 a photoresist film BL bit line BP bonding pads C information storage capacitor element (capacitor) L active region MARY memory array PC peripheral circuit portion Qs for memory cell selection MISFET SA the sense amplifier WD word driver WL the word line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinpei Iijima 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. 20-1 chome, Hitachi, Ltd. Semiconductor Group (72) Inventor Keiji Kuroki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Co., Ltd. Within Hitachi Semiconductor Group, (72) Inventor Takenobu Ikeda Tokyo 5-20-1, Josuihonmachi, Kodaira-shi Within Hitachi Semiconductor Co., Ltd. 1-280 Higashi-Koigakubo, Tokyo-Kokubunji-shi F-term (reference) in Central Research Laboratory, Hitachi, Ltd. 5F083 AD24 AD48 GA06 GA09 JA06 JA14 JA15 JA38 JA39 JA40 LA29 MA06 MA17 MA20 NA01 NA08 PR07 PR09 PR12 PR33 PR40

Claims (16)

[Claims] An insulating film having a groove or a hole formed on a main surface of a semiconductor substrate, a first electrode formed inside the groove or a hole, and a dielectric formed on the first electrode. A semiconductor integrated circuit device having a film and a capacitance element including a second electrode formed on the dielectric film, wherein a TaN layer is interposed between a side wall of the groove or the hole and the first electrode. And a semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said first electrode of said capacitance element is made of Ru. 3. The semiconductor integrated circuit device according to claim 1, wherein an aspect ratio of said groove or hole is 10 or more. 4. A method of manufacturing a semiconductor integrated circuit device having the following steps: (a) forming an insulating film on a main surface of a semiconductor substrate and forming a groove or hole in the insulating film; (b) Forming a TaN layer on the side wall of the groove or hole, (c).
Forming a metal film constituting a first electrode of the capacitive element on the TaN layer; (d) forming a dielectric film of the capacitive element on the Ru film, and forming the dielectric film on the dielectric film; Forming a second electrode of the capacitor; 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the metal film forming the first electrode of the capacitance element is made of Ru. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the dielectric film of said capacitance element is made of tantalum oxide. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 4, further comprising a step of heat-treating said semiconductor substrate. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the step of heat-treating the semiconductor substrate comprises:
A method of manufacturing a semiconductor integrated circuit device, comprising densifying a metal film constituting a first electrode of the capacitor. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said heat treatment step is a step of crystallizing a dielectric film of said capacitance element. . 10. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said heat treatment step is a step of modifying a dielectric film of said capacitance element. . 11. A method for manufacturing a semiconductor integrated circuit device having the following steps: (a) forming a first insulating film on a main surface of a semiconductor substrate and forming a groove or hole in the first insulating film; (B) forming a TaN film on the first insulating film including the inside of the groove or the hole, and (c) performing dry etching in an atmosphere containing chlorine to form the TaN film on the first insulating film. Ta
A step of selectively removing the N film. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, further comprising, after forming said TaN film, burying a second insulating film inside said groove or hole. The method of manufacturing a semiconductor integrated circuit device, wherein the dry etching is performed in a state where the second insulating film on the first insulating film is removed. 13. A method of manufacturing a semiconductor integrated circuit device having the following steps: (a) forming a first insulating film on a main surface of a semiconductor substrate, and forming a plurality of grooves or holes in the first insulating film; (B)
T is formed on the first insulating film including the inside of the groove or the hole.
forming an aN film, and (c) selectively removing the TaN film on the first insulating film located between the plurality of grooves or holes by dry etching in an atmosphere containing chlorine. (D) forming a first electrode of the capacitive element inside the groove or the hole, forming a dielectric film of the capacitive element on the first electrode, and forming a dielectric film of the capacitive element on the dielectric film; Forming a second electrode; 14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, further comprising, after forming the TaN film, burying a second insulating film inside the groove or the hole. A method for manufacturing an integrated circuit device. 15. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein said first insulating film is made of silicon oxide. 16. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein an aspect ratio of said groove or hole is 10 or more.