JPH04349636A - Impurity diffusion method - Google Patents
Impurity diffusion methodInfo
- Publication number
- JPH04349636A JPH04349636A JP15110991A JP15110991A JPH04349636A JP H04349636 A JPH04349636 A JP H04349636A JP 15110991 A JP15110991 A JP 15110991A JP 15110991 A JP15110991 A JP 15110991A JP H04349636 A JPH04349636 A JP H04349636A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- deposited
- film
- layer
- crystal substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 title claims abstract description 34
- 239000012535 impurity Substances 0.000 title claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000007547 defect Effects 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000001301 oxygen Substances 0.000 claims abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 36
- 239000010703 silicon Substances 0.000 claims description 36
- 229910052785 arsenic Inorganic materials 0.000 claims description 29
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 24
- -1 arsenic ions Chemical class 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 230000003647 oxidation Effects 0.000 description 18
- 238000007254 oxidation reaction Methods 0.000 description 18
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 6
- 229910001882 dioxygen Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005204 segregation Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明はシリコン単結晶基板上に
形成した砒素イオン注入非晶質シリコン層を酸化するこ
とによってシリコン単結晶基板上から除去するに際して
、除去後のシリコン単結晶基板表面を平滑化し欠陥のな
いものとすることを特徴とする不純物拡散法に関するも
のである。[Industrial Application Field] The present invention provides a method for removing an arsenic ion-implanted amorphous silicon layer formed on a silicon single crystal substrate from the silicon single crystal substrate by oxidizing the surface of the silicon single crystal substrate after removal. The present invention relates to an impurity diffusion method characterized by smoothing the surface and making it free from defects.
【0002】0002
【従来の技術】従来シリコン単結晶基板上に堆積した多
結晶シリコン層や砒素イオン注入多結晶シリコン層を、
950℃〜1050℃程度の温度で、湿った酸素ガス雰
囲気中で酸化すると、結晶粒界近傍での酸化速度が増速
する結果、堆積シリコン膜を酸化膜除去後のシリコン単
結晶基板表面には凹凸が生じ易くなった。特に砒素イオ
ン注入多結晶シリコン層を酸化した場合には、砒素の粒
界への偏析が増大し、酸化後のシリコン単結晶基板表面
上により大きな凹凸を発生し、好ましくなかった。この
ために、多結晶シリコンのかわりに非晶質シリコン層を
用い、酸化除去後のシリコン単結晶基板表面の凹凸を改
善するよう試みてきたが、砒素イオン注入堆積シリコン
層を用いた場合には、950℃〜1050℃の酸化温度
の場合、砒素の粒界への偏析現象のため、酸化除去後の
シリコン表面の凹凸を軽減する程度にも限度があった。[Prior Art] Conventionally, a polycrystalline silicon layer deposited on a silicon single crystal substrate or an arsenic ion-implanted polycrystalline silicon layer is
When oxidized in a moist oxygen gas atmosphere at a temperature of about 950°C to 1050°C, the oxidation rate near the grain boundaries increases, resulting in a deposited silicon film on the silicon single crystal substrate surface after the oxide film is removed. Irregularities are more likely to occur. In particular, when an arsenic ion-implanted polycrystalline silicon layer is oxidized, the segregation of arsenic to the grain boundaries increases, resulting in larger unevenness on the surface of the silicon single crystal substrate after oxidation, which is undesirable. For this purpose, attempts have been made to use an amorphous silicon layer instead of polycrystalline silicon to improve the unevenness of the silicon single crystal substrate surface after oxidation removal, but when using an arsenic ion implantation deposited silicon layer, In the case of an oxidation temperature of 950° C. to 1050° C., there is a limit to the extent to which unevenness on the silicon surface after oxidation removal can be reduced due to the segregation phenomenon of arsenic to grain boundaries.
【0003】例えば950℃〜1050℃の酸化温度で
、湿った酸素ガス中で堆積多結晶シリコン膜を酸化する
と、酸化膜除去後のシリコン単結晶基板表面には、結晶
粒界効果によって凹凸が著しく形成される。多結晶シリ
コン層のかわりに堆積非晶質シリコン層を用いると、粒
界効果は緩和されて酸化後のシリコン単結晶基板面は極
めて平滑化するが、砒素を注入した砒素イオン注入堆積
非晶質シリコン層では、例えば950℃〜1050℃の
酸化温度で、湿った酸素ガス中で酸化した場合、酸化過
程で結晶粒界に砒素の偏析がおきるために、酸化膜除去
後のシリコン単結晶基板表面には凹凸が依然残る。この
凹凸の高低は1nm以上になる。しかしながら、酸化温
度を例えば1150℃の高温度にした場合、粒界への砒
素偏析は減少し、砒素イオン注入のない場合の酸化除去
後のシリコン単結晶表面状態(1nm以下)に近づく。For example, when a deposited polycrystalline silicon film is oxidized in humid oxygen gas at an oxidation temperature of 950° C. to 1050° C., the surface of the silicon single crystal substrate after the oxide film is removed becomes noticeably uneven due to grain boundary effects. It is formed. If a deposited amorphous silicon layer is used instead of a polycrystalline silicon layer, the grain boundary effect is alleviated and the surface of the silicon single crystal substrate after oxidation becomes extremely smooth. For example, when a silicon layer is oxidized in moist oxygen gas at an oxidation temperature of 950°C to 1050°C, arsenic segregation occurs at grain boundaries during the oxidation process, so the silicon single crystal substrate surface after oxide film removal There are still some unevenness left. The height of this unevenness is 1 nm or more. However, when the oxidation temperature is set to a high temperature of, for example, 1150° C., arsenic segregation at grain boundaries decreases and approaches the silicon single crystal surface state (1 nm or less) after oxidation removal without arsenic ion implantation.
【0004】しかしながら、砒素イオン注入堆積非晶質
シリコン層を例えば1150℃の高温度で酸化し、酸化
膜を除去した後のシリコン単結晶基板表面には結晶欠陥
が生じ易くなる傾向がある。However, crystal defects tend to occur on the surface of a silicon single crystal substrate after the arsenic ion implantation deposited amorphous silicon layer is oxidized at a high temperature of, for example, 1150° C. and the oxide film is removed.
【0005】[0005]
【発明が解決しようとする課題】本発明はこれらの欠点
を改善する目的で、シリコン単結晶基板上に堆積した砒
素イオン注入非晶質シリコン層を、例えば1150℃の
高温度で湿った酸素ガス中で酸化することにより、結晶
粒界に偏析し易かった砒素量を減少させ、結晶粒界にお
ける酸化速度の増大を緩和し、平滑なシリコン単結晶面
を得るところにある。また、高温度の酸化において発生
し易かった結晶欠陥の防止を、シリコン単結晶基板境界
とその上の堆積シリコン膜上に薄いシリコン酸化膜を導
入して、微小欠陥などのない平滑な表面をもつ拡散層を
形成するところにある。SUMMARY OF THE INVENTION In order to improve these drawbacks, the present invention aims to process an arsenic ion-implanted amorphous silicon layer deposited on a silicon single crystal substrate by heating it with moist oxygen gas at a high temperature of, for example, 1150°C. By oxidizing the silicon inside, the amount of arsenic that tends to segregate at grain boundaries is reduced, the increase in oxidation rate at grain boundaries is alleviated, and a smooth silicon single crystal surface is obtained. In addition, to prevent crystal defects that tend to occur during high-temperature oxidation, we have introduced a thin silicon oxide film on the silicon single crystal substrate boundary and the deposited silicon film on it, creating a smooth surface without micro defects. This is where the diffusion layer is formed.
【0006】[0006]
【課題を解決するための手段】結晶欠陥発生を防止する
目的でシリコン単結晶基板とその上の堆積非晶質シリコ
ン層間に、例えば約30Åの薄い二酸化シリコン膜を介
在させることと、更に砒素イオン注入層を酸化した時に
発生し易い微小欠陥の防止のために、砒素イオン注入前
の堆積非晶質シリコン膜上に、例えば600℃の温度で
二酸化シリコン膜を約200Å堆積したものを用いた。
イオン注入後、酸化処理し、更に拡散処理し酸化膜を除
去後、更に第2のドライブ拡散を行ない、目的の表面濃
度と拡散深さを得るようにする。[Means for Solving the Problems] In order to prevent the occurrence of crystal defects, a thin silicon dioxide film of, for example, about 30 Å is interposed between a silicon single crystal substrate and an amorphous silicon layer deposited thereon, and arsenic ions are also provided. In order to prevent micro defects that are likely to occur when the implantation layer is oxidized, a silicon dioxide film of about 200 Å was deposited at a temperature of, for example, 600° C. on the amorphous silicon film deposited before arsenic ion implantation. After ion implantation, an oxidation treatment is performed, and a further diffusion treatment is performed to remove the oxide film, and then a second drive diffusion is performed to obtain the desired surface concentration and diffusion depth.
【0007】このようなプロセスをとることによって、
結晶欠陥,微小欠陥などのない平滑化した高濃度砒素拡
散層を得ることができる。[0007] By taking such a process,
A smooth, highly concentrated arsenic diffusion layer free of crystal defects, micro defects, etc. can be obtained.
【0008】本発明の構成は下記に示す通りである。即
ち、本発明はシリコン単結晶基板上に堆積した非晶質シ
リコン膜中に砒素イオンを注入する第1の工程と、前記
砒素イオン注入非晶質シリコン層を、例えば1150℃
程度の高温度で、湿った酸素雰囲気中で酸化し、更にこ
の状態で砒素をシリコン単結晶基板中に拡散する第2の
工程と、次に前記酸化された砒素イオン注入非晶質シリ
コン層などの酸化層を除去後、所定の拡散深さまで拡散
し、拡散層を形成する第3の工程と、からなる不純物拡
散法において、シリコン単結晶基板とその上の堆積非晶
質シリコン膜間に極めて薄い二酸化シリコン膜を介在さ
せる工程と、堆積非晶質シリコン膜上に200Å程度の
二酸化シリコン膜を低温で形成する工程の実施例後に第
1,第2,第3の工程を実施することにより、結晶欠陥
と微小欠陥のほとんどない高濃度砒素拡散層を形成する
ことを特徴とする不純物拡散法である。The structure of the present invention is as shown below. That is, the present invention includes a first step of implanting arsenic ions into an amorphous silicon film deposited on a silicon single crystal substrate, and a step of implanting the arsenic ion-implanted amorphous silicon layer at, for example, 1150°C.
A second step of oxidizing in a humid oxygen atmosphere at a relatively high temperature, and further diffusing arsenic into the silicon single crystal substrate in this state, and then implanting the oxidized arsenic ions into the amorphous silicon layer, etc. In the impurity diffusion method, which consists of the third step of removing the oxide layer and then diffusing to a predetermined diffusion depth to form a diffusion layer, there is a By performing the first, second, and third steps after the step of interposing a thin silicon dioxide film and the step of forming a silicon dioxide film of about 200 Å on the deposited amorphous silicon film at a low temperature, This is an impurity diffusion method characterized by forming a highly concentrated arsenic diffusion layer with almost no crystal defects or micro defects.
【0009】[0009]
【実施例】以下図面を用いて本実施例を説明する。図2
は従来法に基づいた1実施例を示したものである。例え
ばシリコンP型(111)単結晶基板1,ボロン添加1
0Ω・cm上に約0.6μmの選択拡散用二酸化シリコ
ン膜2を写真蝕刻法によって埋込拡散領域上6の二酸化
シリコン膜部2を除去する。次に例えば減圧気相成長に
よって、例えば堆積温度520℃で非晶質シリコン膜3
を約1000Å堆積する。次に砒素イオン4を30kV
で3×1015cm−2注入した後、湿った酸素ガス中
で950℃〜1050℃の酸化温度で完全に酸化した。
この後、拡散を1150℃で10分間、N2 (4):
O2 (1)の容量比の雰囲気中でそのままの状態で実
施し、酸化物を除去し、目標の表面濃度と拡散深さにな
るまで第2のドライブ拡散を行なう。砒素の埋込拡散の
後、シリコンのエピタキシャル成長を1.5μm行ない
、成長面のモホロジーと結晶欠陥について検討した時、
微小欠陥と粒界効果による凹凸5が見られる。[Embodiment] This embodiment will be explained below with reference to the drawings. Figure 2
1 shows an example based on a conventional method. For example, silicon P type (111) single crystal substrate 1, boron addition 1
A silicon dioxide film 2 for selective diffusion with a thickness of about 0.6 μm is formed on a 0Ω·cm layer by photolithography, and the silicon dioxide film portion 2 on the buried diffusion region 6 is removed. Next, for example, an amorphous silicon film 3 is deposited at a deposition temperature of 520° C. by, for example, reduced pressure vapor phase growth.
is deposited to a thickness of approximately 1000 Å. Next, arsenic ion 4 was applied at 30kV.
After injection of 3×10 15 cm −2 at 3×10 15 cm −2 , it was completely oxidized at an oxidation temperature of 950° C. to 1050° C. in humid oxygen gas. This was followed by diffusion at 1150°C for 10 min with N2 (4):
The process is carried out as it is in an atmosphere with a capacity ratio of O2(1), the oxide is removed, and a second drive diffusion is performed until the target surface concentration and diffusion depth are achieved. After embedding arsenic and diffusion, silicon was epitaxially grown to 1.5 μm and the morphology of the growth surface and crystal defects were examined.
Unevenness 5 due to micro defects and grain boundary effects can be seen.
【0010】図1は本発明法による実施例の1例である
。第1に30Å程度の薄い二酸化シリコン膜7をシリコ
ン単結晶基板1と堆積非晶質シリコン膜3間に介在させ
る。更にケイサンエチルの化学反応によって、600℃
以下で約200Å、5分間で堆積非晶質シリコン層3上
に酸化膜を堆積させた。これに砒素イオンを30kVで
3×1015cm−2注入し、湿った酸素雰囲気中で1
150℃で約15分間酸化し、更にそのままで10分間
程度、N2 (4):O2 (1)の容量比の雰囲気で
拡散し、酸化膜2,3,7,8を除去後、N2 (4)
:O2 (1)の容量比の雰囲気中で、1150℃で2
時間第2ドライブ拡散した。この時の層抵抗は約33Ω
/口であった。
図2の従来法の場合と同様、この砒素埋込拡散層上にシ
リコンのエピタキシャル成長を行ない、表面のモホロジ
ーと結晶欠陥について検討した。高温度酸化によって、
酸化後のシリコン表面の状態は極めて平滑化しており、
結晶欠陥(転位,積層欠陥)ならびに微小欠陥の発生は
著しく減少し、改善された。FIG. 1 shows an example of an embodiment according to the method of the present invention. First, a thin silicon dioxide film 7 of about 30 Å is interposed between the silicon single crystal substrate 1 and the deposited amorphous silicon film 3. Furthermore, due to the chemical reaction of keisane ethyl, the temperature at 600℃
An oxide film of about 200 Å was deposited on the deposited amorphous silicon layer 3 for 5 minutes. Arsenic ions were injected at 3 × 1015 cm-2 at 30 kV into this, and 1
Oxidize at 150°C for about 15 minutes, and then diffuse in an atmosphere with a capacitance ratio of N2 (4):O2 (1) for about 10 minutes. After removing the oxide films 2, 3, 7, and 8, the N2 (4) )
:O2 at 1150℃ in an atmosphere with a capacity ratio of (1).
Time 2nd drive spread. The layer resistance at this time is approximately 33Ω
/It was a mouth. As in the case of the conventional method shown in FIG. 2, silicon was epitaxially grown on this arsenic buried diffusion layer, and surface morphology and crystal defects were examined. By high temperature oxidation,
The state of the silicon surface after oxidation is extremely smooth.
The occurrence of crystal defects (dislocations, stacking faults) and micro defects was significantly reduced and improved.
【0011】[0011]
【発明の効果】以上説明してきたように、砒素イオン注
入非晶質シリコン層を1150℃程度の高温度で湿った
酸素ガス中で酸化することによって、酸化された砒素イ
オン注入非晶質シリコン層が除去された後に、平滑化し
たシリコン単結晶面が得られるだけでなく、酸化膜除去
後のシリコン表面に発生し易かった結晶欠陥や微小欠陥
を減少させることが可能であり、砒素を堆積シリコン中
にイオン注入し、酸化してそれを拡散源とする方法で、
高濃度砒素拡散層を形成するのに有効であり、バイポー
ラLSI系の埋込拡散層形成などに利用されればその実
用性は顕著なものがある。Effects of the Invention As explained above, by oxidizing the arsenic ion-implanted amorphous silicon layer in moist oxygen gas at a high temperature of about 1150°C, the oxidized arsenic ion-implanted amorphous silicon layer After the oxide film is removed, not only can a smooth silicon single crystal surface be obtained, but it is also possible to reduce crystal defects and micro defects that tend to occur on the silicon surface after the oxide film has been removed. This method involves implanting ions inside, oxidizing them, and using them as a diffusion source.
It is effective for forming a high concentration arsenic diffusion layer, and its practicality will be remarkable if it is used for forming a buried diffusion layer of a bipolar LSI system.
【図1】本発明法により形成された高濃度砒素拡散層を
示した断面図である。FIG. 1 is a cross-sectional view showing a high concentration arsenic diffusion layer formed by the method of the present invention.
【図2】従来法の砒素イオン注入法を用い形成された高
濃度拡散層を示した断面図である。FIG. 2 is a cross-sectional view showing a high concentration diffusion layer formed using a conventional arsenic ion implantation method.
1 シリコン単結晶基板
2 選択拡散マスク用二酸化シリコン膜3 堆積非
晶質シリコン膜
4 砒素イオン注入用ビーム
5 酸化・拡散後のシリコン表面
6 砒素埋込拡散領域1 Silicon single crystal substrate 2 Silicon dioxide film for selective diffusion mask 3 Deposited amorphous silicon film 4 Beam for arsenic ion implantation 5 Silicon surface after oxidation and diffusion 6 Arsenic embedded diffusion region
Claims (1)
質シリコン膜中に砒素イオンを注入する第1の工程と、
前記砒素イオン注入非晶質シリコン層を例えば1150
℃程度の高温度で、湿った酸素雰囲気中で酸化し、更に
この状態で砒素をシリコン単結晶基板中に拡散する第2
の工程と、次に前記酸化された砒素イオン注入非晶質シ
リコン層などの酸化層を除去後、所定の拡散深さまで拡
散し、拡散層を形成する第3の工程とからなる不純物拡
散法において、シリコン単結晶基板とその上の堆積非晶
質シリコン膜間に極めて薄い二酸化シリコン膜を介在さ
せる工程と、堆積非晶質シリコン膜上に200Å程度の
二酸化シリコン膜を低温で形成する工程を行なった後に
第1,第2,第3の工程を実施することにより、結晶欠
陥と微小欠陥のほとんどない高濃度砒素拡散層を形成す
ることを特徴とする不純物拡散法。1. A first step of implanting arsenic ions into an amorphous silicon film deposited on a silicon single crystal substrate;
The arsenic ion-implanted amorphous silicon layer is, for example, 1150
A second process in which arsenic is oxidized in a humid oxygen atmosphere at a high temperature of about °C, and then diffused into the silicon single crystal substrate in this state.
In an impurity diffusion method, the impurity diffusion method comprises a third step of removing the oxidized arsenic ion-implanted amorphous silicon layer or the like and then diffusing to a predetermined diffusion depth to form a diffusion layer. , a process of interposing an extremely thin silicon dioxide film between a silicon single crystal substrate and an amorphous silicon film deposited on it, and a process of forming a silicon dioxide film of about 200 Å on the deposited amorphous silicon film at low temperature. An impurity diffusion method characterized in that a high concentration arsenic diffusion layer with almost no crystal defects and micro defects is formed by performing the first, second, and third steps.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15110991A JPH04349636A (en) | 1991-05-27 | 1991-05-27 | Impurity diffusion method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15110991A JPH04349636A (en) | 1991-05-27 | 1991-05-27 | Impurity diffusion method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04349636A true JPH04349636A (en) | 1992-12-04 |
Family
ID=15511553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15110991A Pending JPH04349636A (en) | 1991-05-27 | 1991-05-27 | Impurity diffusion method |
Country Status (1)
Country | Link |
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JP (1) | JPH04349636A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011077066A (en) * | 2009-09-29 | 2011-04-14 | Shin Etsu Handotai Co Ltd | Method of manufacturing semiconductor substrate |
-
1991
- 1991-05-27 JP JP15110991A patent/JPH04349636A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011077066A (en) * | 2009-09-29 | 2011-04-14 | Shin Etsu Handotai Co Ltd | Method of manufacturing semiconductor substrate |
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