JPH043491A - Plating method of circuit or lead frame - Google Patents

Plating method of circuit or lead frame

Info

Publication number
JPH043491A
JPH043491A JP10278990A JP10278990A JPH043491A JP H043491 A JPH043491 A JP H043491A JP 10278990 A JP10278990 A JP 10278990A JP 10278990 A JP10278990 A JP 10278990A JP H043491 A JPH043491 A JP H043491A
Authority
JP
Japan
Prior art keywords
plating
solder resist
tin
lead frame
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10278990A
Other languages
Japanese (ja)
Inventor
Ryoichi Tajima
良一 田嶋
Yukio Ogino
荻野 幸男
Takashi Natsume
隆 夏目
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Nikko Kyodo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd, Nikko Kyodo Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP10278990A priority Critical patent/JPH043491A/en
Publication of JPH043491A publication Critical patent/JPH043491A/en
Pending legal-status Critical Current

Links

Landscapes

  • Chemically Coating (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the corrosion of the root of a lead or the end section of a solder resist by plating a circuit or a lead frame with one kind or two kinds or more of metals having standard electrode potential less than the standard electrode potential of copper, forming a solder resist film, and plating the upper section of the circuit or lead frame except said film section with tin or a tin alloy. CONSTITUTION:It is favorable that plating is conducted in approximately the half of the thickness of plating finally required for the section or film thickness of 0.2-0.4mum or less before a solder-resist film is formed. Either one kind of a metal of a metal, which has standard electrode potential less than +0.337V at a value in an aqueous solution, such as tin, lead, zinc, indium, antimony or bismuth or metals consisting of the combination of these two kinds or more or alloy plating, etc., in which other metals are added to these metals and alloys, are employed for first plating. The printing, etc., of a solder resist are performed. The upper section of a previously plated circuit or lead frame, on which the film of the solder resist is not formed, is plated with tin or the alloy or the like.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、回路又はリードフレームのめっき方法にかか
わり、特には、例えばプリント回路基板やテープキャリ
ア等などの半導体装置や半導体チップを実装、ボンディ
ング等行うソルダーレジスト被膜部以外の回路又はリー
ドフレーム上にスズ等をめっきする方法に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for plating circuits or lead frames, and in particular, to mounting and bonding of semiconductor devices and semiconductor chips, such as printed circuit boards and tape carriers. This invention relates to a method of plating tin or the like on a circuit or lead frame other than the solder resist coating.

[従来の技術] 半導体装置をプリント回路基板の所定の位置に積載する
場合、半導体装置のリードフレームとプリント回路基板
の回路とは通常ハンダにより接続される。この場合、ハ
ンダ付は性を向上させるため、プリント回路基板のこの
接続部の回路部分にスズ等のめっきが施される。また、
最近、ポリイミド等の絶縁樹脂フィルム上に銅箔でリー
ドフレームを形成して半導体チップを実装するテープキ
ャリアの一種であるT A B (Tape Auto
mated Bonding)方式が実用化され始めた
。この方式では半導体チップのバンプと前記フィルム上
のリードフレームの一端とを熱圧着によりボンディング
するが、この熱圧着性を向上させるために、また当該リ
ードフレームの他端はハンダ付けに供されるため、この
ハンダ付は性向上のため、上記リードフレームの両端上
にスズ等のめっきが施される。
[Prior Art] When a semiconductor device is mounted at a predetermined position on a printed circuit board, the lead frame of the semiconductor device and the circuit of the printed circuit board are usually connected by solder. In this case, in order to improve soldering properties, the circuit portion of this connection portion of the printed circuit board is plated with tin or the like. Also,
Recently, TAB (Tape Auto), a type of tape carrier that mounts a semiconductor chip by forming a lead frame with copper foil on an insulating resin film such as polyimide, has been introduced.
mated bonding) method has begun to be put into practical use. In this method, the bumps of the semiconductor chip and one end of the lead frame on the film are bonded by thermocompression bonding, but in order to improve this thermocompression bonding property, and the other end of the lead frame is used for soldering. In order to improve the soldering process, both ends of the lead frame are plated with tin or the like.

従来、このようなめっきは、ハンダが他の部分に付着す
るのを防ぐためのソルダーレジスト膜を形成した後に行
われていた。
Conventionally, such plating has been performed after forming a solder resist film to prevent solder from adhering to other parts.

さらに、このめっきを行うためのスズ等のめっき浴は、
塩酸あるいはホウフッ化水素酸等の強酸をベースとし、
チオ尿素、二価のスズ等を含有するものが用いられてい
た。しかし、これらの浴では、特に、チオ尿素等、銅又
は銅合金素材を腐食する物質を含んでおり、しかも、T
AB方式に用いられるリードの巾は50μm以下と極め
て細かいために、フィルム等の基板とリードとの接触境
界部であるリードのつけ根あるいはソルダーレジストと
リードとの接触境界部であるソルダーレジスト端部が腐
食し、リードの断線が発生しやすいという問題があった
Furthermore, the plating bath such as tin for performing this plating is
Based on strong acids such as hydrochloric acid or fluoroboric acid,
Those containing thiourea, divalent tin, etc. were used. However, these baths contain substances that corrode copper or copper alloy materials, such as thiourea, and T
The width of the leads used in the AB method is extremely fine, less than 50 μm, so the base of the lead, which is the contact boundary between the lead and a substrate such as a film, or the edge of the solder resist, which is the contact boundary between the solder resist and the lead, is There was a problem in that it corroded and the leads were likely to break.

そこで、このリードのつけ根の腐食を防止する目的で、
従来のスズめっき浴に用いられる強酸に代えて有機スル
ホン酸を用いた無電解めっき浴が提案された(特開昭6
3−230883号、特開平1−184279号公報参
照)。
Therefore, in order to prevent corrosion at the base of this lead,
An electroless plating bath using an organic sulfonic acid instead of the strong acid used in conventional tin plating baths was proposed (Japanese Patent Application Laid-open No.
3-230883, JP-A-1-184279).

しかし、この浴ではソルダーレジスト端部の腐食を防止
することができなかった。
However, this bath was unable to prevent corrosion at the edges of the solder resist.

[発明が解決しようとする課題1 本発明は、上記問題点を解消すべくなされたものであり
、その目的とするところは、リードのつけ根あるいはソ
ルダーレジスト端部に腐食の発生しないめっき方法を提
供することにある。
[Problem to be Solved by the Invention 1] The present invention has been made to solve the above problems, and its purpose is to provide a plating method that does not cause corrosion at the base of the lead or at the end of the solder resist. It's about doing.

[課題を解決するための手段] 本発明は、ソルダーレジスト被膜部を有する回路又はリ
ードフレームの当該ソルダーレジスト被膜部以外の回路
又はリードフレーム上をめっきする方法において、ソル
ダーレジスト被膜を形成する前に、あらかじめ、回路又
はリードフレームの全体あるいはその一部を銅の標準電
極電位未満の標準電極電位を有する金属から選択された
1種もしくは2種以上の金属でめっきした後、ソルダー
レジスト被膜を形成し、次いで、ソルダーレジスト被膜
部以外の回路又はリードフレーム上をスズ又はスズ合金
でめっきすることからなり、特に、好ましくは、前記鋪
の標準電極電位未満の標準電極電位を有する金属が、ス
ズ、ナマリ、アエン、アンチモン、ビスマス又はインジ
ウムから選択される1種もしくは2種以上であることか
らなる回路又はリードフレームのめっき方法である。
[Means for Solving the Problems] The present invention provides a method for plating a circuit or lead frame other than the solder resist coating portion of a circuit or lead frame having a solder resist coating portion, in which, before forming the solder resist coating, , after plating the whole or a part of the circuit or lead frame with one or more metals selected from metals having a standard electrode potential lower than the standard electrode potential of copper, a solder resist film is formed. Then, the circuit or lead frame other than the solder resist coating part is plated with tin or a tin alloy, and it is particularly preferable that the metal having a standard electrode potential lower than the standard electrode potential of the plate is tin, raw metal, etc. , aene, antimony, bismuth, or indium.

本発明は、プリント回路基板、フレキシブルプリント回
路基板等の銅及び銅合金からなる回路、フラットバッグ
、チップキャリア、テープキャリア等の銅及び銅合金か
らなるリードフレーム等に好適である。
The present invention is suitable for circuits made of copper and copper alloys such as printed circuit boards and flexible printed circuit boards, lead frames made of copper and copper alloys such as flat bags, chip carriers, and tape carriers.

尚、本発明に云うソルダーレジストとは、永久レジスト
とも云われているが、ハンダが、目的部以外のところに
付着するのを防ぐための保護膜であり、一般にはエポキ
シ系樹脂、アクリレート系樹脂、ウレタン系樹脂等を用
いてレジスト膜を形成する。
The solder resist referred to in the present invention is also called a permanent resist, but it is a protective film to prevent solder from adhering to areas other than the intended part, and is generally made of epoxy resin or acrylate resin. , a resist film is formed using urethane resin or the like.

本発明の上記ソルダーレジスト被膜を形成する前に、行
うめっきは、当該部分に最終的番―めっきが必要とされ
る厚さの172以下の膜厚とすることが好ましい。17
2以上の厚さにすると回路およびリードフレーム間の絶
縁不良を起こすおそれがあるためである。尚、めっきが
必要とされる膜厚は、各回路および各リードフレームの
間隔、目的、用途等によって異なるため、−概に決める
ことはできないが、一般には、0.4〜8μm程度とさ
れるので、最初のめっきは0.2〜4μm以下の厚さに
することが好ましい。尚、この最初のめっきの膜厚は、
0.1μm以下とすると本発明の効果を充分に発揮する
ことができず、あまり好ましくない。
It is preferable that the plating performed before forming the solder resist film of the present invention has a film thickness of 172 mm or less, which is the thickness at which the final number plating is required for the part concerned. 17
This is because if the thickness is 2 or more, there is a risk of insulation failure between the circuit and the lead frame. The film thickness required for plating cannot be determined generally, as it varies depending on the spacing between each circuit and each lead frame, purpose, application, etc., but is generally set to be approximately 0.4 to 8 μm. Therefore, it is preferable that the initial plating has a thickness of 0.2 to 4 μm or less. The film thickness of this first plating is
If it is less than 0.1 μm, the effects of the present invention cannot be fully exhibited, which is not very preferable.

この最初のめっきは、従来のめっきと同じ方法、すなわ
ち、電気めっき、化学めっきの何れをも用いて行うこと
ができるが、操作の容易性等から、化学めっき、特には
置換めっきの方法で行うことが好ましい。
This initial plating can be performed using the same method as conventional plating, that is, electroplating or chemical plating, but due to ease of operation, chemical plating, especially displacement plating, is used. It is preferable.

この最初のめっきは、銅の標準電極電位未満の金属を用
いる。ここで云う標準電極電位とは水溶液中での値で、
銅の標準電極電位は+0.337Vであり、この値未満
の標準電極電位を有する金属を用いるものである。これ
以上の標準電極電位を有する金属をめっきした場合は、
後工程でのスズ或はスズ合金めっきが均一に形成されな
い。この水溶液中での標準電極電位が+0.337V未
満の金属としては、スズ、ナマリ、アエン、インジウム
、アンチモン又はビスマス等を例示でき、これらのいず
れか1種の金属或いはこれらの2種以上の組み合わせか
らなる合金、さらには、これらの金属や合金に、他の金
属を添加した合金めっき等とすることができる。最初の
めっきは上記金属の何れかが、或いは上記金属の合計量
が、50重量%以上であれば特に支障はなく、また合金
組成をも、特に問題とすることはない。
This initial plating uses a metal below the standard electrode potential of copper. The standard electrode potential referred to here is the value in an aqueous solution,
The standard electrode potential of copper is +0.337V, and a metal having a standard electrode potential below this value is used. When plating a metal with a standard electrode potential higher than this,
Tin or tin alloy plating in the subsequent process is not uniformly formed. Examples of metals whose standard electrode potential in this aqueous solution is less than +0.337V include tin, sulfur, aene, indium, antimony, bismuth, etc., and any one of these metals or a combination of two or more of these metals can be used. Further, alloy plating can be made by adding other metals to these metals or alloys. There is no particular problem in the initial plating as long as any of the above metals or the total amount of the above metals is 50% by weight or more, and the alloy composition is not particularly problematic.

またこの最初のめっきは、回路やリードフレームの全体
に渡って行っても良いが、一部でも良い。一部に行う場
合は、後工程でのめっきを行う部分を含んで、ソルダー
レジストで被覆される部分をも一部含むようにする。
Further, this initial plating may be performed over the entire circuit or lead frame, or may be performed on a portion thereof. If it is applied to a portion, it includes the portion to be plated in a subsequent process and also includes a portion of the portion covered with the solder resist.

これは、ソルダーレジストの皮膜境界の腐食を防止する
という本目的上当然である。
This is natural for the purpose of preventing corrosion at the boundaries of the solder resist film.

次に、ソルダーレジストの印刷等を行なうが、これは従
来、スクリーン印刷等の方法をそのまま適用できる。
Next, a solder resist is printed, and conventional methods such as screen printing can be applied as is.

その後、前記ソルダーレジストの被膜が形成されなかっ
た、先にめっきした回路又はリードフレーム上にスズ又
はスズ合金等によるめっきを行なう。このめっきも、従
来性われている電解めっき、化学めっき等の何れの方法
をも用いることができる。特に、従来の塩酸又はホウフ
ッ化水素酸等をベースとし、これにチオ尿素等を含んだ
スズ或いはスズ合金のめっき浴や有機スルホン酸ベース
としためっき浴等を用いる化学めっき方法は、好適に採
用しつる 〔実施例] (実施例1) 5.5CIT1平方の銅張ガラスエポキシ積層板上にラ
インアンドスペース50μmのくし型パターン(ビン数
400)を形成した。この各基板を第1表に示すめっき
浴に、同表に記載しだ液温及び時間浸漬し、パターン全
体にめっき膜厚を0.2μmとなるようにめっきした。
Thereafter, plating with tin, tin alloy, or the like is performed on the previously plated circuit or lead frame on which the solder resist film was not formed. For this plating, any conventional method such as electrolytic plating or chemical plating can be used. In particular, chemical plating methods using conventional hydrochloric acid or fluoroboric acid-based plating baths containing tin or tin alloys containing thiourea, etc., and organic sulfonic acid-based plating baths are preferably employed. Shitsuru [Example] (Example 1) A comb-shaped pattern (number of bins: 400) with a line and space of 50 μm was formed on a 5.5 CIT 1 square copper-clad glass epoxy laminate. Each of the substrates was immersed in the plating bath shown in Table 1 at the temperature and time shown in the same table to plate the entire pattern to a plating film thickness of 0.2 μm.

上記めっき後のパターンにピンの両端が約1mm出るよ
うにソルダーレジスト(日本合成化学、エポグレーズN
−506KG)を印刷し、加熱硬化(130℃、60分
)した。その後、第2表の浴組成を有するスズめっき浴
に液温70℃で5分間浸漬し、パターン上に膜厚が0.
7μmとなるようにスズめっきした。これらの基板につ
いて、本パターンの断面を観察したところ、ソルダーレ
ジスト端部には全く腐食等の異常は観察されなかった。
Apply solder resist (Nippon Gosei Kagaku, Epoglaze N
-506KG) was printed and heat-cured (130°C, 60 minutes). Thereafter, the pattern was immersed in a tin plating bath having the bath composition shown in Table 2 at a temperature of 70°C for 5 minutes to form a film with a thickness of 0.
Tin plating was performed to a thickness of 7 μm. When the cross-sections of the patterns of these substrates were observed, no abnormality such as corrosion was observed at the edges of the solder resist.

また、これらの基板を80℃で、3時間加熱し、次いで
、22℃の温度で、相対湿度60%の環境下に168時
間曝した。この結果、いずれの基板にもスズのウィスカ
ーの発生等の異常は全く認められなかった。
Further, these substrates were heated at 80° C. for 3 hours, and then exposed to an environment of 22° C. and 60% relative humidity for 168 hours. As a result, no abnormalities such as the formation of tin whiskers were observed on any of the substrates.

(以下余白) 第2表 スズめっき浴 (単位gハ) (実施例2) 巾3 cm、3cm毎に正方形(lcnl)の穴を有す
るポリイミドテープに電解銅箔をエポキシ系接着剤で張
り合わせた。本テープにラインアンドスペース50μm
のくし型パターン(ビン数160)をピンの先端が2m
m穴の中に突き出るように形成した。本テープを第1表
のめっき浴に同表に記載しだ液温及び時間で浸漬し、パ
ターン全体に、膜厚が0.2μmとなるようにめっきし
た。このめっき後のパターンに、ポリイミドテープ上穴
の4辺から1mlTl外側の領域を除きソルダーレジス
ト(日本合成化学、エボグレーズN−504JG)を印
刷し、加熱硬化(130℃、60分)した。その後、第
2表のスズめっき浴に液温70℃で、5分間浸漬し、パ
ターン上に膜厚が0.7μmのスズめっきした。本パタ
ーンの断面を観察したところ、リードのつけ根とソルダ
ーレジスト端部には全く腐食等の異常は観察されなかっ
た。また、これらのテープを80℃で、3時間加熱し、
次いで、22℃の温度で、相対湿度60%の環境下に1
68時間曝した。この結果、いずれの基板にもスズのウ
ィスカーの発生等の異常は全く認められなかった。
(The following is a blank space) Table 2 Tin plating bath (unit: g) (Example 2) An electrolytic copper foil was attached to a polyimide tape having a width of 3 cm and having square (lcnl) holes every 3 cm using an epoxy adhesive. Line and space 50μm on this tape
A comb-shaped pattern (160 bins) with a pin tip of 2 m.
It was formed to protrude into the m hole. This tape was immersed in the plating bath shown in Table 1 at the bath temperature and time shown in the same table, and the entire pattern was plated to a film thickness of 0.2 μm. A solder resist (Evoglaze N-504JG, manufactured by Nippon Gosei Kagaku) was printed on the pattern after plating except for the area outside 1 ml Tl from the four sides of the upper hole of the polyimide tape, and was cured by heating (130° C., 60 minutes). Thereafter, it was immersed in the tin plating bath shown in Table 2 at a liquid temperature of 70° C. for 5 minutes to plate the pattern with tin to a thickness of 0.7 μm. When the cross section of this pattern was observed, no abnormalities such as corrosion were observed at the bases of the leads and the ends of the solder resist. In addition, these tapes were heated at 80°C for 3 hours,
Then, at a temperature of 22°C and an environment of 60% relative humidity,
Exposure was made for 68 hours. As a result, no abnormalities such as the formation of tin whiskers were observed on any of the substrates.

(実施例3) 実施例2で用いたテープを第2表のめっき浴に液温40
℃で、5分間浸漬し、パターン全体に、膜厚が0.2μ
mのめつきした。これを、τソルダーレジストを印刷し
、加熱硬化した。その後、第3表のスズめっき浴に液温
8O℃で5分間浸漬し、パターン上に膜厚が0゜7μm
になるようにスズめっきした。本パターンの断面を観察
したところ、リードのつけ根とソルダーレジスト端部に
は全く腐食等の異常は観察されなかった。また、これら
のテープを80℃で、3時間加熱し、次いで、22℃の
温度で、相対湿度60%の環境下に168時間曝した。
(Example 3) The tape used in Example 2 was placed in the plating bath shown in Table 2 at a liquid temperature of 40°C.
℃ for 5 minutes, and the entire pattern was coated with a film thickness of 0.2μ.
I looked at m. A τ solder resist was printed on this and cured by heating. After that, it was immersed in the tin plating bath shown in Table 3 at a liquid temperature of 80℃ for 5 minutes to form a film with a thickness of 0.7μm on the pattern.
It was tin-plated to make it look like this. When the cross section of this pattern was observed, no abnormalities such as corrosion were observed at the bases of the leads and the ends of the solder resist. These tapes were also heated at 80° C. for 3 hours and then exposed to a temperature of 22° C. and a relative humidity of 60% for 168 hours.

この結果、いずれの基板にもスズのウィスカーの発生等
の異常は全く認められなかった。
As a result, no abnormalities such as the formation of tin whiskers were observed on any of the substrates.

(比較例1) 実施例1で用いた基板に、パターン全体へのめっきを行
なわず、ソルダーレジストを印刷し、加熱硬化した。そ
の後、第2表のめつき浴に液温70℃で5分間浸漬し、
パターン上に膜厚は0.7μmのスズめっきした。本パ
ターンの断面を観察したところ、ソルダーレジスト端部
に深さ4μmの腐食が観察された。
(Comparative Example 1) A solder resist was printed on the substrate used in Example 1 without plating the entire pattern, and was cured by heating. After that, it was immersed in the plating bath shown in Table 2 for 5 minutes at a liquid temperature of 70°C.
Tin plating with a film thickness of 0.7 μm was performed on the pattern. When the cross section of this pattern was observed, corrosion with a depth of 4 μm was observed at the end of the solder resist.

(比較例2) 実施例2で用いたテープにパターン全体へのめっきを行
なわず、ソルダーレジストを印刷し、加熱硬化した。そ
の後、第2表のスズめっき浴に液温70’Cで5分間浸
漬し、パターン上に膜厚が0.7μmになるようにスズ
めっきした。本パターンの断面を観察したところ、リー
ドのつけ根とソルダーレジスト端部にそれぞれ深さ2μ
mと4μmの腐食が観察された。
(Comparative Example 2) A solder resist was printed on the tape used in Example 2 without plating the entire pattern, and the tape was cured by heating. Thereafter, it was immersed in the tin plating bath shown in Table 2 at a liquid temperature of 70'C for 5 minutes to plate the pattern with tin to a film thickness of 0.7 μm. When we observed the cross section of this pattern, we found that there was a depth of 2μ at the base of the lead and at the end of the solder resist.
Corrosion of m and 4 μm was observed.

(比較例3) 実施例2で用いたテープにパターン全体へのめっきを行
なわず、ソルダーレジストを印刷し、加熱硬化した。そ
の後、第3表のスズめっき浴に液温80℃で5分間浸漬
し、パターン上に膜厚が0.7μmになるようにスズめ
っきした。本パターンの断面を観察したところ、ソルダ
ーレジスト端部に深さ6μmの腐食が観察された。
(Comparative Example 3) A solder resist was printed on the tape used in Example 2 without plating the entire pattern, and the tape was cured by heating. Thereafter, it was immersed in the tin plating bath shown in Table 3 at a liquid temperature of 80° C. for 5 minutes to plate the pattern with tin to a film thickness of 0.7 μm. When the cross section of this pattern was observed, corrosion with a depth of 6 μm was observed at the end of the solder resist.

[発明の効果] 以上説明したように、本発明に係るめっき法は、回路あ
るいはリードフレームのスズ等のめっき工程で発生する
リードのつけ根あるいはソルダーレジスト端部の腐食防
止に格別の効果を有し、特に、TAB等のリード巾が極
めて細かく、リード腐食が製品の致命的損傷となり得る
場合において極めて有効なものである。
[Effects of the Invention] As explained above, the plating method according to the present invention has a special effect on preventing corrosion of the base of the lead or the end of the solder resist, which occurs during the plating process of tin, etc. of a circuit or lead frame. This is particularly effective in cases where the lead width of a TAB or the like is extremely narrow and lead corrosion can cause fatal damage to the product.

Claims (2)

【特許請求の範囲】[Claims] (1)ソルダーレジスト被膜部を有する回路又はリード
フレームの当該ソルダーレジスト被膜部以外の回路又は
リードフレーム上をめっきする方法において、ソルダー
レジスト被膜を形成する前に、あらかじめ、回路又はリ
ードフレームの全体あるいはその一部を銅の標準電極電
位未満の標準電極電位を有する金属から選択された1種
もしくは2種以上の金属でめっきした後、ソルダーレジ
スト被膜を形成し、次いで、ソルダーレジスト被膜部以
外の回路又はリードフレーム上をスズ又はスズ合金でめ
っきすることを特徴とする回路又はリードフレームのめ
っき方法。
(1) In a method of plating a circuit or lead frame other than the solder resist coated part of a circuit or lead frame having a solder resist coat, before forming the solder resist coat, the entire circuit or lead frame or After plating a part with one or more metals selected from metals having a standard electrode potential lower than the standard electrode potential of copper, a solder resist film is formed, and then the circuits other than the solder resist film part are plated. Or a method for plating a circuit or lead frame, which comprises plating the lead frame with tin or a tin alloy.
(2)請求項(1)の銅の標準電極電位未満の標準電極
電位を有する金属が、スズ、ナマリ、アエン、アンチモ
ン、ビスマス又はインジウムであることを特徴とする回
路又はリードフレームのめっき方法。
(2) A method for plating a circuit or lead frame, characterized in that the metal having a standard electrode potential lower than the standard electrode potential of copper according to claim (1) is tin, namali, aene, antimony, bismuth, or indium.
JP10278990A 1990-04-20 1990-04-20 Plating method of circuit or lead frame Pending JPH043491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10278990A JPH043491A (en) 1990-04-20 1990-04-20 Plating method of circuit or lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10278990A JPH043491A (en) 1990-04-20 1990-04-20 Plating method of circuit or lead frame

Publications (1)

Publication Number Publication Date
JPH043491A true JPH043491A (en) 1992-01-08

Family

ID=14336890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10278990A Pending JPH043491A (en) 1990-04-20 1990-04-20 Plating method of circuit or lead frame

Country Status (1)

Country Link
JP (1) JPH043491A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997000753A1 (en) * 1995-06-20 1997-01-09 Matsushita Electric Industrial Co., Ltd. Solder, and soldered electronic component and electronic circuit board
JP2006032484A (en) * 2004-07-13 2006-02-02 Seiko Epson Corp Manufacturing method of wiring circuit board
JP2006032483A (en) * 2004-07-13 2006-02-02 Seiko Epson Corp Manufacturing method of wiring circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997000753A1 (en) * 1995-06-20 1997-01-09 Matsushita Electric Industrial Co., Ltd. Solder, and soldered electronic component and electronic circuit board
US5962133A (en) * 1995-06-20 1999-10-05 Matsushita Electric Industrial Co., Ltd. Solder, electronic component mounted by soldering, and electronic circuit board
CN1080616C (en) * 1995-06-20 2002-03-13 松下电器产业株式会社 Solder and soldered electronic component and electronic circuit board
JP2006032484A (en) * 2004-07-13 2006-02-02 Seiko Epson Corp Manufacturing method of wiring circuit board
JP2006032483A (en) * 2004-07-13 2006-02-02 Seiko Epson Corp Manufacturing method of wiring circuit board

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