JPH04348067A - Cmos semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To adjust the impedance of an interconnection and to restrain a reflected noise in an interconnection at the inside by a method wherein resistances which connect a part near the impedance mismatching part of the interconnection to the side of a power supply and to the side of a ground are formed together with an interconnection which is connected between CMOS circuits. CONSTITUTION:A part near an impedance mismatching part such as a contact hole or a through hole part is terminated by using a resistance which is constituted of a diffusion layer, a polycrystalline silicon layer or a well. Resistances 5, 7 which are constituted of a diffusion layer, a polycrystalline silicon layer or a well are formed together with an interconnection 12. A part near the impedance mismatching part of the interconnection 12 is connected to a power supply 6 via the resistance 5, and it is connected a ground 8 via the resistance 7 so that the impedance of the interconnection 12 can be adjusted. Consequently, the impedance mismatching part of the interconnection can be removed or its mismatching can be suppressed. A CMOS semiconductor integrated circuit which is operated at high speed can be obtained without a problem such as a malfunction due to a reflected noise.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a CMOS configuration.

0002

2. Description of the Related Art FIG. 2 is a diagram showing an example of a conventional semiconductor integrated circuit having a CMOS configuration. In the figure, 1 is CMOS
2 is a NOT gate that receives the output of the CMOS circuit 1 via wiring 11; 3 is a NOT gate that receives the output of NOT gate 2 via wiring 12; 4 is a NOT gate that receives the output of NOT gate 2 via wiring 12;
is C which receives the output of NOT gate 3 via wiring 13.
It is a MOS circuit.

Next, the operation will be explained. The signal output from the CMOS circuit 1 becomes information inverted by the NOT gate 2, and is inverted again by the NOT gate 3, logically converting into CMOS circuit 1.
The signal becomes a signal having the same logic as the logic output from the MOS circuit 1 and is input to the CMOS circuit 4.

By the way, in the design of a CMOS circuit, in order to make any gate less susceptible to noise, the CMOS circuit is
The size ratio of the P-channel MOS transistor and the N-channel MOS transistor constituting the OS gate is adjusted. With this adjustment, C
A MOS circuit is configured.

[0005]

[Problem to be Solved by the Invention] Conventional CMOS semiconductor integrated circuits are configured as described above, but as the scale of circuits increases, the wiring used within the integrated circuits includes long wires. Therefore, if you try to further increase the speed, you will be affected by noise that cannot be eliminated by paying attention only to the setting of the logical threshold as described above. In other words, in the case where the impedance changes on the wiring between circuits, for example, when the wiring is composed of multiple metal layers,
When a through-hole section that connects different metal layers, or when wiring is formed of a single metal layer, there is a problem in that the influence of reflected noise that occurs in the portion where the wiring width changes becomes large.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a CMOS semiconductor integrated circuit that can suppress reflection noise from internal wiring.

[0007]

[Means for solving the problem] CMOS according to the present invention
In a semiconductor integrated circuit, a resistor made of a diffusion layer, a polycrystalline silicon layer, or a well is provided along with wiring connecting the output of a first CMOS circuit and the input of a second CMOS circuit, and the impedance mismatch between the wirings is provided. The vicinity is connected to the power supply side and the ground side via the above-mentioned resistor.

[0008]

[Operation] In this invention, in addition to the wiring connecting between the CMOS circuits, a resistor is provided to connect the vicinity of the impedance mismatching point of the wiring to the power supply side and the ground side, so that the impedance of the wiring can be adjusted. ,
Reflection noise from internal wiring can be suppressed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a CMOS semiconductor integrated circuit according to an embodiment of the present invention. In the diagram, the same components as those in FIG. 2 are given the same reference numerals, and their explanations will be omitted. 5 is a resistor that connects the vicinity of the impedance mismatched portion of the wiring 12 and the power supply 6; 7 is a resistor that connects the vicinity of the impedance mismatched portion and the ground 8; Its value is set so that impedance mismatch is reduced.

Next, the operation will be explained. The signal transmission operation is the same as the conventional one. That is, information output from the CMOS circuit 1 is input to the NOT gate 2 via the wiring 11, and logically inverted information is output from the NOT gate 2. The information output from NOT gate 2 is sent to wiring 1
2 to the NOT gate 3. Information input to the NOT gate 3 is inverted at the NOT gate 3 and input to the CMOS circuit 4 via the wiring 13.

The operation of the present invention will be described below, focusing on the wiring 12. NOT gate 2 and NOT gate 3 are located very far from each other on the integrated circuit, and interconnect 12 is actually composed of multiple metal layers. Therefore, the wiring 12 is provided with holes called contact holes or through holes at several locations for connecting different metal layers.

[0012] Here, impedance mismatching generally occurs at contact holes or through holes. A resistor formed of a diffusion layer, a polycrystalline silicon layer, or a well is used to terminate the vicinity of a point where impedance mismatch occurs, such as a contact hole or a through hole portion. That is, by connecting the vicinity of the point where the mismatch occurs to the power supply side or the ground side via a resistor, it becomes possible to remove the point where the mismatch occurs.

As described above, in this embodiment, resistors 5 and 7 made of a diffusion layer, a polycrystalline silicon layer, or a well are provided together with the wiring 12, and the vicinity of the portion of the wiring 12 where the impedance mismatch occurs is connected via the resistor 5. Since it is connected to the power supply 6 and to the ground 8 via the resistor 7, and the impedance of the wiring 12 can be adjusted, it is possible to remove or suppress mismatching points on the wiring, and it operates at high speed. This has the effect that a CMOS semiconductor integrated circuit that does not have the problem of malfunction due to reflected noise can be obtained.

[0014] In the above embodiment, the wiring 12 is made of a plurality of metal layers.
It is also applicable to wiring made of metal layers. In other words,
If the wiring width changes along the way, impedance mismatch will still occur, and it is possible to suppress impedance mismatch by connecting a predetermined part of the wiring to the power supply side and ground side via a resistor. becomes.

[0015]

[Effects of the Invention] As described above, according to the present invention, CM
In addition to the wiring that connects the OS circuits, we installed a resistor that connects the impedance mismatch points of the wiring to the power supply side and the ground side, making it possible to adjust the impedance of the wiring, thereby reducing reflection noise from internal wiring. It is possible to obtain a CMOS semiconductor integrated circuit which is capable of suppressing noise, is capable of high-speed operation, and has no problem of malfunction due to reflected noise during operation.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a CMOS semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor integrated circuit with a conventional CMOS configuration.

[Explanation of symbols]

1 First CMOS circuit 2 NOT gate 3 NOT gate 4 Second CMOS circuit 5 Resistance 6 Power supply 7 Resistance 8 Grand 12 Wiring

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a CMOS configuration, comprising first and second CMOS gates, and a conductive wiring layer connecting the output of the first CMOS gate and the input of the second CMOS gate. , comprising a diffusion layer, a polycrystalline silicon layer, or a well, and a resistor connecting the vicinity of the impedance mismatched portion of the wiring layer of the conductor to the power supply side and the ground side; A CMOS semiconductor integrated circuit characterized by adjustable impedance.