JPS6346009A - Ic device with built-in impedance matching resistor - Google Patents
Ic device with built-in impedance matching resistorInfo
- Publication number
- JPS6346009A JPS6346009A JP18877486A JP18877486A JPS6346009A JP S6346009 A JPS6346009 A JP S6346009A JP 18877486 A JP18877486 A JP 18877486A JP 18877486 A JP18877486 A JP 18877486A JP S6346009 A JPS6346009 A JP S6346009A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- impedance matching
- buffer
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims abstract description 43
- 238000010586 diagram Methods 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ＩＣ装置、特に入出力端子間のインピーダン
ス整合用の抵抗を内蔵したＩＣ装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC device, and particularly to an IC device that includes a built-in resistor for impedance matching between input and output terminals.
［従来の技術］
従来のこの種ＩＣ装置は、各ＩＣ装置を接続するに際し
ては、例えば第４図に示すように、信号を正しく伝達す
るためにインピーダンス整合用の抵抗を付けていた。す
なわち、ＩＣＩの出力バッファＡからＩＣ２の入力バッ
ファＢに入出力端子Ｐａおよびｐｂを介して信号を伝達
する場合、抵抗Ｒａを直列に、抵抗Ｒｂおよび抵抗Ｒｃ
を並列に接続し、インピーダンスの整合をはかっていた
。[Prior Art] In conventional IC devices of this type, when connecting each IC device, a resistor for impedance matching is attached in order to properly transmit signals, as shown in FIG. 4, for example. That is, when transmitting a signal from output buffer A of ICI to input buffer B of IC2 via input/output terminals Pa and pb, resistor Ra is connected in series, resistor Rb and resistor Rc
were connected in parallel to match impedance.
従って、従来のこの種ＩＣ装置を基板上に組んだ場合、
ＩＣ装置間に外付けのインピーダンス整合用の抵抗が必
要であり、多大な面積を必要としその高密度配置が不可
能であった。また、コスト的にも外付は抵抗分高価にな
らざるを得なかったのである。Therefore, when a conventional IC device of this type is assembled on a board,
An external impedance matching resistor is required between the IC devices, which requires a large area and makes it impossible to arrange it in high density. Also, in terms of cost, external connections had to be expensive due to the resistance.
［発明か解決しようとする問題点］
そこで、本発明の目的は、上述の従来装置の欠点を除去
し、インピーダンス整合用の抵抗をＩＣ装置に内蔵する
ことによりその高密度配置を可能ならしめ、かつ、安価
なＩＣ装置を提供することにあ−る。[Problems to be Solved by the Invention] Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks of the conventional device, and to enable high-density arrangement of impedance matching resistors by incorporating them into an IC device. Another object of the present invention is to provide an inexpensive IC device.
［問題点を解決するための手段］
上記目的を達成するために、本発明は、入出力端子と、
入出力端子に接続されたインピーダンス整合用抵抗と、
入出力端子に対してインピーダンス整合用抵抗を介して
直列に接続された出力バッファと、入出力端子とインピ
ーダンス整合用抵抗との接続点に接続された入力ハッコ
アとを備え、侶号出ノ月１、νには、インピーダンス整
合用抵抗が出力ハッコアと直列に接続され、信号入力時
にはインピータンス整合用抵抗か入力バッファと並列に
接続されるようにしたことを特徴とする。[Means for Solving the Problems] In order to achieve the above object, the present invention provides an input/output terminal;
An impedance matching resistor connected to the input/output terminal,
It is equipped with an output buffer connected in series to the input/output terminal via an impedance matching resistor, and an input buffer connected to the connection point between the input/output terminal and the impedance matching resistor. , ν is characterized in that an impedance matching resistor is connected in series with the output core, and when a signal is input, the impedance matching resistor or the input buffer is connected in parallel.
［作用］
上記構成になる本発明の詳細な説明する。一方のＩＣ装
置の出力バッファから信号を出力し、他方のＩＣ装置の
入力バッファに伝達するときには、一方のＩＣ装置の出
力バッファと入出力端子との間に直列に接続したインピ
ーダンス整合用の抵抗が信号伝達経路に対して直列に接
続され、また、他方のＩＣ装置の出力バッファと入出力
端子との間に直列に接続したインピーダンス整合用の抵
抗が入力バッファに対して並列となることから、インピ
ーダンスのマツチングがとれて反射が起こらず損失なく
信号を伝達することができる。[Operation] The present invention having the above configuration will be explained in detail. When outputting a signal from the output buffer of one IC device and transmitting it to the input buffer of the other IC device, an impedance matching resistor connected in series between the output buffer of one IC device and the input/output terminal is connected. Since the impedance matching resistor, which is connected in series to the signal transmission path and also connected in series between the output buffer and the input/output terminal of the other IC device, is parallel to the input buffer, the impedance Since the signals are matched, reflections do not occur and signals can be transmitted without loss.
［実施例］
以下、本発明の実施例につき添附図面を参照して説明す
る。[Examples] Examples of the present invention will be described below with reference to the accompanying drawings.
第１図は、本発明の実施例を示す回路図であり、ＩＣ装
置ＩＣＩおよびＩＣ装置ＩＣ２がそれぞれ入出力端子Ｐ
１および入出力端子Ｐ２を介して接続される（破線示）
。FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which an IC device ICI and an IC device IC2 each have an input/output terminal P.
1 and connected via input/output terminal P2 (shown by broken line)
.
なお、入出力端子は複数個存在し、本図は、その１部の
みを示すものである。■および八２は出力バッファであ
り、それぞれ動作のイネーブル制御用入力端子ａ１およ
びａ２が接続されている。Note that there are a plurality of input/output terminals, and this figure shows only a portion of them. 2 and 82 are output buffers, to which operation enable control input terminals a1 and a2 are connected, respectively.
旧およびＲ２は、それぞれ出力バッファＡ１および八２
と直列に接続されたインピーダンス整合用の抵抗であり
、信号伝達経路射が起こらないように相互にインピーダ
ンス整合がとられている。old and R2 are output buffers A1 and 82 respectively
This is an impedance matching resistor connected in series with the signal transmission path, and the impedances are matched to each other so that signal transmission path radiation does not occur.
口１および口２は、それぞれ出力バッファＡｌと抵抗Ｒ
１および出力バッファＡ２と抵抗Ｒ２に対して並列に接
続された入力バッファであり、それぞれ制御用入力端子
ｂｌおよびｂ２が接続されている。Port 1 and port 2 are connected to output buffer Al and resistor R, respectively.
1 and output buffer A2 are input buffers connected in parallel to the resistor R2, and are connected to control input terminals bl and b2, respectively.
上記構成において、今、ＩＣＩからＩＣ２に信号を伝達
する場合について説明する。In the above configuration, the case where a signal is transmitted from the ICI to the IC2 will now be described.
この場合は、ＩＣＩの出力バッファＡ１の制御用入力端
子ａ１には、出力バッファＡ１をイネーブルにする信号
か入力されており、制御用入力端子ｂ１には、入力バッ
ファ８１の出力をハイインピーダンスにする信号が入力
されている。一方、ＩＣ２の出力バッファΔ２の制御用
入力端子ａ２には出力バッファ八２の出力をハイレベル
あるいはローレベルに固定する信号が入力され（以下の
説明ではハイレヘル固定とする）、制御用入力端子ｂ２
には入力バッフアロ２をイネーブルにする信号が入力さ
れている。In this case, a signal that enables the output buffer A1 is input to the control input terminal a1 of the output buffer A1 of the ICI, and a signal that enables the output buffer A1 is input to the control input terminal b1, which sets the output of the input buffer 81 to high impedance. A signal is being input. On the other hand, a signal that fixes the output of the output buffer 82 to a high level or a low level is input to the control input terminal a2 of the output buffer Δ2 of the IC2 (in the following explanation, it is assumed that the output is fixed to a high level), and the control input terminal b2
A signal for enabling input buffer allo 2 is input to .
従って、このときの等価回路は、第２図に示すように抵
抗Ｒ１が信号伝達経路に直列に、抵抗Ｒ２が並列に接続
されることになり、両抵抗Ｒ１，Ｒ２には反射が起こら
ないように選ばれたインピーダンス整合用の抵抗である
ので、損失を伴わずに信号の伝達ができるのである。Therefore, in the equivalent circuit at this time, as shown in Figure 2, the resistor R1 is connected in series with the signal transmission path, and the resistor R2 is connected in parallel, so that no reflection occurs in both resistors R1 and R2. The impedance matching resistor is selected to allow signal transmission without loss.
逆に、ＩＣ２からＩＣＩに信号を伝達する場合には、各
制御用入力端子ａｌ、ｂｌ、ａ２．ｂ２への入力を切換
える。すなわち、出力バッファＡ２および入力バッファ
Ｂ１がイネーブル状態となり、入力バッファＢ２の出力
がハイインピーダンスで、出力バッファＡｌの出力がハ
イレベルに固定されるように信号が入力される。Conversely, when transmitting a signal from IC2 to ICI, each control input terminal al, bl, a2 . Switch the input to b2. That is, output buffer A2 and input buffer B1 are enabled, and a signal is input so that the output of input buffer B2 is at high impedance and the output of output buffer Al is fixed at high level.
このときの等価回路は、第３図に示すようになり、前述
の如くインピーダンスの整合が行なわれるのである。The equivalent circuit at this time is as shown in FIG. 3, and impedance matching is performed as described above.
尚、内蔵する抵抗は、ポリシリコンあるいは拡散層の抵
抗等の形態として、上述の入力および出力バッファと一
体に集積回路化することがてき、ＩＣ装置のチップ面積
に与える影習は極めて少ない。Note that the built-in resistor can be in the form of a polysilicon resistor, a resistor in a diffusion layer, or the like, and can be integrated into an integrated circuit with the above-mentioned input and output buffers, so that the impact on the chip area of the IC device is extremely small.
［発明の効果］
以上の説明から明らかなように、本発明によればインピ
ータンス整合用の抵抗をＩＣ装置に内蔵することにより
、基板上にそのＩＣ装置をより高密度に配置することか
可能となり、かつ、安価に製造できる。[Effects of the Invention] As is clear from the above description, according to the present invention, by incorporating a resistor for impedance matching into an IC device, it is possible to arrange the IC device on a substrate at a higher density. and can be manufactured at low cost.
第１図は本発明の実施例を示す回路図、第２図はＩＣＩ
からＩＣ２に信号を伝達する場合の等価回路図、
第３図はＩＣ２からＩＣＩに信号を伝達する場合の等価
回路図、
第４図は従来のＩＣ装置の接続状態を示す回路図である
。
八１．Ａ２・・・出力ハッコア、
Ｉｌｌ、ｌＩ２・・・入力バッファ、
Ｉｌｌ、１１２・・・インピーダンス整合用抵抗、ａｌ
、ａ２．ｂｌ、ｂ２・・・制御用入力端子。
突旅竹ソＥホす回路口
第１図
ＩＣ７かうＩＣ２にイ富号とイ云σしする針の等イ山四
つ８称図第２図Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2 is an ICI
FIG. 3 is an equivalent circuit diagram when transmitting a signal from IC2 to IC2, FIG. 3 is an equivalent circuit diagram when transmitting a signal from IC2 to ICI, and FIG. 4 is a circuit diagram showing the connection state of a conventional IC device. 81. A2... Output core, Ill, lI2... Input buffer, Ill, 112... Impedance matching resistor, al
, a2. bl, b2...control input terminals. Tsukuba Takeso E Hosu Circuit Exit Fig. 1 IC7 IC2 has a needle that says I Tomigo Fig. 2
Claims (1)
、 前記入出力端子に対して前記インピーダンス整合用抵抗
を介して直列に接続された出力バッファと、 前記入出力端子と前記インピーダンス整合用抵抗との接
続点に接続された入力バッファとを備え、信号出力時に
は、前記インピーダンス整合用抵抗が前記出力バッファ
と直列に接続され、信号入力時には前記インピーダンス
整合用抵抗が前記入力バッファと並列に接続されるよう
にしたことを特徴とするインピーダンス整合用抵抗内蔵
ＩＣ装置。[Scope of Claims] An input/output terminal; an impedance matching resistor connected to the input/output terminal; an output buffer connected in series to the input/output terminal via the impedance matching resistor; an input buffer connected to a connection point between an input/output terminal and the impedance matching resistor; when a signal is output, the impedance matching resistor is connected in series with the output buffer; when a signal is input, the impedance matching resistor is connected in series with the output buffer; An IC device with a built-in resistor for impedance matching, characterized in that the input buffer is connected in parallel with the input buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18877486A JPS6346009A (en) | 1986-08-13 | 1986-08-13 | Ic device with built-in impedance matching resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18877486A JPS6346009A (en) | 1986-08-13 | 1986-08-13 | Ic device with built-in impedance matching resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6346009A true JPS6346009A (en) | 1988-02-26 |
Family
ID=16229546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18877486A Pending JPS6346009A (en) | 1986-08-13 | 1986-08-13 | Ic device with built-in impedance matching resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6346009A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04348067A (en) * | 1990-06-28 | 1992-12-03 | Mitsubishi Electric Corp | Cmos semiconductor integrated circuit |
| US6873179B2 (en) | 1993-12-28 | 2005-03-29 | Hitachi, Ltd. | Signal transmitting device suited to fast signal transmission |
-
1986
- 1986-08-13 JP JP18877486A patent/JPS6346009A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04348067A (en) * | 1990-06-28 | 1992-12-03 | Mitsubishi Electric Corp | Cmos semiconductor integrated circuit |
| US6873179B2 (en) | 1993-12-28 | 2005-03-29 | Hitachi, Ltd. | Signal transmitting device suited to fast signal transmission |
| US7015717B2 (en) * | 1993-12-28 | 2006-03-21 | Hitachi, Ltd. | Signal transmitting device suited to fast signal transmission |
| US7123048B2 (en) * | 1993-12-28 | 2006-10-17 | Hitachi, Ltd. | Signal transmitting device suited to fast signal transmission |
| US7295034B2 (en) | 1993-12-28 | 2007-11-13 | Hitachi, Ltd. | Signal transmitting device suited to fast signal transmission |
| US7372292B2 (en) * | 1993-12-28 | 2008-05-13 | Hitachi, Ltd. | Signal transmitting device suited to fast signal transmission |
| US7911224B2 (en) | 1993-12-28 | 2011-03-22 | Hitachi, Ltd. | Signal transmitting device suited to fast signal transmission |
| US8106677B2 (en) | 1993-12-28 | 2012-01-31 | Lg Electronics Inc. | Signal transmitting device suited to fast signal transmission |
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