JPH05341892A - Information processor - Google Patents

Abstract

PURPOSE:To attain an impedance matching by the same terminating resistance for an entire system constitution. CONSTITUTION:At the time of mounting a card 15 being a bus load on a system bus, a load capacity for the unit length of a bus signal line can be constant by mounting a dummy load 16 having the load capacity equivalent to the other card on an empty slot, and the characteristic impedance of the signal line can be constant and uniform. Thus, even in any card mounting situation, the impedance matching can be attained by the same terminating resistance 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for transmitting high-speed signals without error on a system bus of a computer in which a plurality of cards are mounted.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a system bus according to the prior art, in which a signal driver 10, a system bus signal line 11,
Card mounting slot 1 to which the bus load card 15 is connected
2 and the terminating resistor 13. FIG. 4A is a diagram showing a state where the card is not mounted. Slots 12 which slot into not implemented card also includes, when the characteristic impedance of the signal line in the state Z _0a, by connecting the terminating resistor 13 having an impedance equal to Z _0a the end of the signal line , Impedance matching can be achieved, and the signal driven by the driver 10 is transmitted through the system bus signal line 11 without being reflected.

However, the system is usually constructed by combining various cards, and the characteristic impedance does not always become Z _0a . For example,
FIG. 4B is a diagram showing a conventional example in which cards are mounted in all the slots 12. When a card 15 that becomes a bus load is mounted in all the slots 12 as shown in FIG. 4B to form a system, since a bus load that can be regarded as a load capacity is connected to the signal line 11, the inductance per unit length is The characteristic impedance of the signal line determined by the capacitance ratio changes to Z _0b .

Further, FIG. 4 (c) shows that the cards are arranged at wide intervals (1
FIG. 4 is a diagram showing a conventional example implemented by every slot), FIG.
(D) is a diagram showing a conventional example in which there are sparse and dense card mountings. In the case of FIG. 4C, since the mounting interval is wider than that of the state of FIG. 4B, the increase of the load capacitance per unit length is small, and the special impedance of the signal line changes to Z _0c (however, Z _0b). <Z _0c <Z _0a ). As shown in FIG. 4D, when the card 15 is mounted on the system bus signal line 11 in a dense portion 17 and a sparse portion 18, the characteristic impedance of the signal line is Z _0b in the dense portion 17. , Sparse part 1
In the case of 8, the point becomes Z _0c, and a change point of the characteristic impedance occurs at a point 19 in the signal line 11.

[0005]

According to the conventional technique, as shown in FIG.
As shown in (b) and (4), the characteristic impedance of the signal line is different in the system in which the mounting condition of the card that is the bus load is different. Therefore, the impedance matching should be performed by the same termination method for all different systems. In addition, in FIG. 4 (d), the mounting interval of the card is not uniform, so that there is a change point of the characteristic impedance in the signal line.

If there is an impedance mismatch portion at the line end of the signal line or in the line, the signal driven by the driver is reflected there and appears as a distorted waveform on the receiving side, and high speed operation is required. And the possibility of malfunction increases. Therefore, in order to realize high-speed operation of the system, it is necessary to eliminate impedance mismatching points.

The present invention has been made in view of the above-mentioned problems of the prior art. In the system in which the mounting state of the card is different and the characteristic impedance of the signal line is different, impedance mismatching is performed by the same termination method. The object is to provide an information processing device to be excluded.

[0008]

In order to achieve the above object, the first invention is such that when a card which becomes a bus load is mounted on a system bus, an empty slot has a load capacity equivalent to that of other cards. It is characterized by connecting a dummy load. 2nd invention is a dummy load of 1st invention, Comprising:
It is characterized in that it is connected to a slot via a switch.

A third invention is characterized in that, in the dummy load of the first invention, a dummy load card is mounted by removing a card internal circuit from a card which becomes a bus load.

[0010]

According to the first aspect of the present invention, by combining the load of the connected card and the dummy load, the load capacitance per unit length added to the bus signal line is all Similar to the case where a card is mounted in a slot, the characteristic impedance of the signal line is constant regardless of the system configuration and is uniform everywhere on the line.

In the second invention, the switch is opened in association with the mounting of the card, so that the load is always connected to all the slots. According to the third aspect of the invention, by mounting dummy load cards in empty slots, loads are connected to all slots.

[0012]

The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an information processing apparatus according to the present invention.
FIG. 1A is a diagram showing an embodiment in which cards are mounted in all the slots 12. The characteristic impedance of the signal line in this case is Z _0b , and an impedance Z equal to this is Z _0b.
Impedance matching is _achieved by the terminating resistor 14 having _0b . The other constituent elements are the same as those in FIG.

FIG. 1 (b) is a view showing an embodiment of the present invention in which cards are mounted at wide intervals (every other slot), and FIG. 1 (c) is an embodiment of the present invention in which the cards are mounted unevenly. FIG. 1 (b) is shown in FIG. 4 (c) and FIG. 1 (c).
4 has the same system configuration as that of FIG.
3 is replaced by a terminating resistor 14 having an impedance Z _0b, and a dummy load 16 is connected to an empty slot.

When the cards 15 are mounted every other slot as shown in FIG. 1B, a dummy load 16 having the same impedance as the card 15 is connected to the empty slots, and the characteristic impedance of the signal line is Z. _{Since 0b} remains unchanged, impedance matching is achieved by the same terminating resistor 14 as in the case of FIG. Even when the card is unevenly mounted as shown in FIG. 1C, the dummy load 16 is connected to the empty slot so that the characteristic impedance of the signal line is maintained at Z _0b. It is aligned.

FIG. 2 is a block diagram of a first embodiment for connecting a dummy load. It comprises a system bus signal line 20, a dummy load 21, a switch 22, and a card mounting slot 23, and the dummy load 21 is connected to the slot 23 via the switch 22. As shown in FIG. 2 (a),
When the card 24 is not mounted in the slot 23, the switch 22 is closed, and the signal line 20 is connected to the dummy load 21.
Are connected. As shown in FIG. 2B, when the card 24 is mounted in the slot 23, the switch 22 is opened in association with this, and the dummy load 21 is disconnected from the signal line 20 at the same time when the card 24 is mounted. When the load capacity of the dummy load 21 is made equal to that of a normal card, the load capacity per slot always has a constant value. Since the slots 23 are normally arranged on the motherboard of the system bus at equal intervals, the load capacity per unit length of the bus signal line 20 is constant.

FIG. 3 is a block diagram of a second embodiment for connecting a dummy load. In FIG. 3A, a normal card 27 which becomes a bus load is a card side connector 29, a bus interface element 30 common to all cards, and a card internal circuit 3
1 and is connected to the mother board 25 via a mother board side connector 26. Figure 3
In (b), the dummy load card 28 has a configuration in which the card internal circuit 31 is removed from the card 27, and the dummy load card 28 is also connected to the motherboard board 25 via the motherboard side connector 26 when mounted. .. Bus interface element 30 in the dummy load card 28
The output on the system bus side is always off so that it does not affect the system bus other than load.

By mounting the dummy load card 28 in empty slots, the same load by the same bus interface element is connected to all slots.

[0018]

As described above, according to the first invention,
By connecting a dummy load to an empty slot of the system bus, the load capacitance per unit length of the bus signal line becomes constant, so the characteristic impedance of the bus signal line becomes constant even in various card configurations, and the line It is uniform at any point. Therefore, impedance matching can be achieved with the same signal line terminating resistance for all system configurations, and impedance mismatch in the middle of the signal line is eliminated. Furthermore, because the impedance mismatch disappears, the reflection of the transmission waveform disappears.
There is no waveform distortion on the signal receiving side, and the signal can be transmitted more accurately and at higher speed.

According to the second invention, since the dummy load according to the first invention is connected to the bus signal line via the switch, it is not necessary to forget to connect the dummy load. According to the third invention, since the dummy load according to the first invention is mounted as a dummy load card to connect to the bus signal line, impedance matching can be achieved without modifying the card mounting slot.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing device according to the present invention.

FIG. 2 is a configuration diagram showing a first embodiment of dummy load connection.

FIG. 3 is a configuration diagram showing a second embodiment of dummy load connection.

FIG. 4 is a configuration diagram of an information processing device according to a conventional technique.

[Explanation of symbols]

 10 signal driver 11 system bus signal line 12 card mounting slot 13 terminating resistor 14 terminating resistor 15 normal bus load card 16 dummy load 17 card mounting interval dense part 18 card mounting interval sparse part 19 change in characteristic impedance Point 20 System bus signal line 21 Dummy load 22 Switch 23 Card mounting slot 24 Normal bus load card 25 Motherboard board 26 Motherboard side connector 27 Normal bus load card 28 Dummy load card 29 Card side connector 30 Bus interface element 31 Card internal circuit

Claims (3)

[Claims] 1. An information processing apparatus that constitutes a system by mounting cards in a plurality of slots provided on a motherboard of a system bus, wherein a terminating resistor provided at the end of the system bus and a slot in the slot. 2. An information processing apparatus, comprising: a dummy load for connecting the card to an unmounted slot and matching impedance with the terminating resistor. 2. The information processing apparatus according to claim 1,
The information processing apparatus, wherein the dummy load is normally closed for each slot and is connected to a system bus through a switch opened by mounting the card. 3. The information processing apparatus according to claim 1, wherein
The information processing apparatus, wherein the dummy load is configured as a dummy load card obtained by removing a card internal circuit from the card.