JPH0434786B2 - - Google Patents
Info
- Publication number
- JPH0434786B2 JPH0434786B2 JP58108984A JP10898483A JPH0434786B2 JP H0434786 B2 JPH0434786 B2 JP H0434786B2 JP 58108984 A JP58108984 A JP 58108984A JP 10898483 A JP10898483 A JP 10898483A JP H0434786 B2 JPH0434786 B2 JP H0434786B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- ecc code
- exclusive
- circuit
- ecc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 10
- 208000011580 syndromic disease Diseases 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58108984A JPS603046A (ja) | 1983-06-17 | 1983-06-17 | 記憶制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58108984A JPS603046A (ja) | 1983-06-17 | 1983-06-17 | 記憶制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS603046A JPS603046A (ja) | 1985-01-09 |
JPH0434786B2 true JPH0434786B2 (de) | 1992-06-09 |
Family
ID=14498632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58108984A Granted JPS603046A (ja) | 1983-06-17 | 1983-06-17 | 記憶制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS603046A (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0756640B2 (ja) * | 1985-03-01 | 1995-06-14 | 株式会社日立製作所 | 記憶装置 |
US4918695A (en) * | 1988-08-30 | 1990-04-17 | Unisys Corporation | Failure detection for partial write operations for memories |
JP4339914B2 (ja) | 2006-01-31 | 2009-10-07 | 富士通株式会社 | エラー訂正コード生成方法及びメモリ管理装置 |
JP7269466B2 (ja) | 2018-12-28 | 2023-05-09 | シブヤパッケージングシステム株式会社 | 容器包装装置 |
-
1983
- 1983-06-17 JP JP58108984A patent/JPS603046A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS603046A (ja) | 1985-01-09 |
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