JPH043456A - Formation of active layer laminated element - Google Patents

Abstract

PURPOSE:To simplify and shorten manufacturing steps by forming columnar tungsten in contact holes having different depths by one tungsten CVD. CONSTITUTION:A contact hole having 2.6mum of depth at a position of a source 4 of a lower layer transistor, a contact hole having 1.7mum of depth at a position of a gate wiring 5a, and the last contact hole having 1.5mum of depth at a position of a source 8 of an upper transistor are sequentially formed. Then, a silicon thin film 15 having 0.1mum of thickness is deposited on the entire surface by an LPCVD. Tungsten is not grown on a silicon oxide film, but deposited only on a part where the silicon film exists while eroding the silicon film. If the thickness is so set that the film 15 is eliminated by the eroding, even if the depths of the holes are different, columnar tungstens 17, 17a, 17b can be simultaneously formed in all the holes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming an active layer stacked device formed by stacking active layers.

[Conventional technology]

Conventionally, wiring for an element in which two active layers are laminated has been formed as follows. FIGS. 2(a) to 2(e) are cross-sectional views schematically showing a method for forming an active multilayer device manufactured by a conventional technique in the order of steps.

First, a drain 3 . Source 4. After forming a lower transistor consisting of a gate 5° and a gate wiring 5a, an oxide film 6, which is a first insulating film, is formed over the entire surface. Next, a planarizing agent is applied, and the surface of the oxide film 6 is planarized by constant-speed etch-back of the planarizing agent 9M M6, and then a single crystal silicon film and a polycrystalline silicon film are formed on the oxide M6. , using these films, drain 7, source 8° gate 9
．． Then, an upper layer transistor consisting of a gate wiring 9a is formed, and an oxide film 10, which is a second insulating film, is formed on the entire surface. As a result, a device having the shape shown in FIG. 2(a) is obtained.

Note that the gates 9, 5 of the upper and lower layer transistors cannot be formed with contact holes in these areas, so the oxide film 6.5 is formed from the gate 9.5. Contact holes are formed on the gate wiring 9a extended over the element isolation oxidation [2] and the gate wiring 5a. Furthermore, these gate wiring 9a and gate wiring 5a may be used as independent wiring.

Next, as shown in FIG. 2(b), contact holes for forming vertical wiring are formed in the oxide films 10 and 6 on the source 4 of the lower transistor by an exposure process using a photoresist and a dry etching process. .

Next, tungsten is deposited in this contact hole by CVD.
The columnar tungsten 11 is formed by embedding. After that, a nitride film 12 is formed on the entire surface, and the columnar tacksten 11 is
Cover the top. The purpose of this nitride film 12 is to prevent the columnar tungsten 11 from being etched during the subsequent acid treatment during the photoresist process for forming contact holes. Next, as shown in Figure 2 (C),
Contact holes for forming vertical wiring are formed in the oxide films 10 and 6 on the gate wiring 5a by an exposure process using a photoresist and a dry etching process.

Next, CVD of tungsten is applied in this contact hole.
The columnar tungsten 11a is formed by embedding using the D method.

Thereafter, a nitride film 13 is formed on the entire surface to cover the columnar tungsten lla. Next, as shown in FIG. 2(d), contact holes for forming vertical interconnections are formed in the oxide film 10 on the source 8 of the upper layer transistor by an exposure process using a photoresist and a dry etching process.

Subsequently, tungsten is buried in this contact hole by the CVD method to form columnar tungsten 11b. Finally, as shown in FIG. 2(e), the nitride film 13
．． 12 is removed by etching, and columnar tungsten 11. l
After exposing la, llb, deposit aluminum,
The wiring 14 was formed by patterning.

[Problem to be solved by the invention]

In the conventional example, sources 4, 5, . and gate wiring 5a
We have explained the formation of three types of contact holes for the drain 3 of the lower layer transistor in the conventional active layer stacked device.
．． The source 4, the gate wiring 5a of the lower transistor,
Drain 7, source 8 of the upper layer transistor. Three types of contact holes are formed and the columnar tungsten 11. It is necessary to form lla and llb separately. For this reason, the manufacturing process becomes long and problems with device performance increase accordingly.

Furthermore, when embedding tungsten into the contact hole using the CVD method, the source 4. The silicon of the gate wiring 5a and the source 8 is eroded, resulting in a decrease in junction breakdown voltage, an increase in junction leakage, or a decrease in the columnar tungsten 1.
1 and source 4 columnar tungsten lla and gate arrangement II
5 a , fluctuations in contact resistance between the columnar tungsten llb and the source 8 are likely to occur.

In addition, when active layers including devices with complex structures are laminated, the unevenness on the element surface becomes much larger than that of a normal semiconductor device, and as a result, disconnections in the wiring [10] are likely to occur where the element surface has large steps. Become.

[Means to solve the problem]

The method for forming an active layer stacked device of the present invention includes forming a lower layer transistor using a semiconductor substrate and a polycrystalline silicon film, and forming a lower transistor on the entire surface in forming an active layer stacked device formed by stacking two active layers. A process of forming a first insulating film and flattening its surface, forming an upper layer transistor using the semiconductor film and polycrystalline silicon film formed thereon, and depositing a second insulating film of a predetermined thickness over the entire surface. Then, contact holes for forming vertical wiring with different hole depths were formed by etching several times, and a thin silicon film was applied over the entire surface using LPC.
The process of depositing using the VD method, the process of spin-coating a planarizing agent on the entire surface and etching back the entire surface until the planarizing agent and silicon thin film are removed except in the contact hole, and the planarizing process that remains in the contact hole. The method includes the steps of removing the agent, performing selective CVD growth of tungsten on the silicon thin film, and burying tungsten into the contact hole.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(h) are schematic cross-sectional views in the order of manufacturing steps for explaining one embodiment of the present invention. In this embodiment, the first. A silicon oxide film was used as the second insulating film, and a polystyrene solution was used as the planarizing agent.

A film with a thickness of 0.8 cm was formed on the silicon substrate 1 using the LOCO8 method.
After forming an element isolation oxide film 2 of 0.5 μm in thickness, a gate 5 made of polycrystalline silicon with a thickness of 0.5 μm is inserted through a gate oxide film.
．． and extending from the gate 5 on the element isolation oxide film 2 (
A gate 5a made of polycrystalline silicon with a thickness of 0.5 μm (or as an independent wiring) is formed, and then impurities are introduced to form a drain 3 and a source 4, thereby forming a lower transistor.

Next, an oxide film 11116, which is a first insulating film and is made of a silicon oxide film and has a thickness of 1 to 2 μm, is then formed on the entire surface. Thereafter, the surface of the oxide film 6 is flattened by spin coating a polystyrene solution and constant-speed etch-back of the polystyrene and silicon oxide films, and the thickness of the oxide film 6 is reduced to 0.2 μm on the contact formation position of the gate wiring 5a. I will make it happen.

Next, a film thickness of 0 is applied to the upper layer transistor formation region on the oxide film 6.
．． After depositing a 5 μm polycrystalline silicon film and converting it into a single crystal silicon film using a method such as laser annealing, a gate 9 made of polycrystalline silicon with a film thickness of 05 μm is formed on top of this through a gate oxide film. At the same time, a gate wiring 9a made of polycrystalline silicon with a film thickness of 0.5 μm is formed on the oxide film 6, extending from the gate 9 (or serving as an independent wiring), and then the above-mentioned single crystal silicon is formed. Impurities are introduced into the silicon film to form a drain 7 and a source 8, thereby forming an upper layer transistor.

Subsequently, an oxide film 10a having a thickness of 1.5 μm made of a silicon oxide film, which is a second insulating film, is deposited on the entire surface.
The structure shown in FIG. 1(a) is obtained.

Here, the thickness of the oxide film 10a needs to be sufficiently thick (1.0 μm or more) to exceed the step difference from the oxide film 6 to the gate 9.

Next, contact holes for forming vertical interconnections with a hole size of 1.5 μm are formed. First, the depth of the source 4 (or drain 3) of the lower layer transistor is 2.6μ.
m contact hole, then a contact hole with a depth of 1.7 μm at the position of the gate wiring 5a (of the lower layer transistor), and finally a contact hole with a depth of 1.7 μm at the position of the source 8 (or drain 7, or gate wiring 9a) of the upper layer transistor. .5
A .mu.m contact hole is sequentially formed by an exposure process using a photoresist and a dry etching process, and is processed into the shape shown in FIG. 1(b).

After that, as shown in Figure 1(c), the film thickness is 0 over the entire surface.
．． A 1 μm silicon thin film 15 is deposited by LPCVD.

Next, a flattening agent 16 made of a polystyrene solution is spin-coated over the entire surface. As shown in FIG. 1(d), the spin-applied planarizing agent 16 fills contact holes of three different depths, and its surface becomes flat.

Next, flattening agent 16. Silicon fi! 15. Oxide film 10
The entire surface is etched back under conditions where the etching speed is close to that of a. As shown in FIG. 1(e), this etch-back is performed by removing the planarizing agent 16 in areas other than the contact hole.
This is done to a depth where the silicon thin layer 11115 is removed. As a result, the silicon thin film 15 can be left only on the side walls and bottom of the contact hole, and at the same time, the entire surface can be flattened.

Thereafter, the planarizing agent 16 remaining in the contact hole is removed by acid treatment, resulting in a shape in which the silicon thin film 15 remains only on the side walls and bottom of the contact hole, as shown in FIG. 1(f). It will be done.

Next, CVD growth of tungsten is performed in an environment at a temperature of 300° C. using a mixed gas of WF6 and SiH4 at a mixing ratio of 1.1 with H2 as a carrier gas. Under these conditions, tungsten does not grow on the silicon oxide film, but instead erodes the silicon film and is deposited only where the silicon film was present. Therefore, the deposition of tungsten in the contact hole progresses by growing using the silicon thin film 15 on the side wall and bottom of the contact hole as a generation nucleus. If the film thickness is set so that the silicon thin film 15 disappears due to erosion when the columnar tungsten 17.17a, 17b in the contact hole is formed, even if the depth of the contact hole is different, the same as shown in FIG. As shown in (g), columnar tungsten 17.17a, 17b can be formed simultaneously in all contact holes.

Finally, as shown in FIG. 1(h), aluminum is deposited and patterned to form wiring 14.

In this example, as shown in FIG. 1(g), the entire surface of the device is flattened, so when a plurality of such devices are bonded together to create an active layer multilayer device with two or more layers, Easy to match.

In this example, a silicon oxide film was used as the first and second insulating films, and a polystyrene solution was used as the planarizing agent, but other types of insulating films may be used.

Even if other types of flattening agents are used, it will not become uneven.

Further, although this embodiment deals with three types of contact holes having different depths, the present invention can be applied even if the number of types of contact holes having different depths increases.

〔Effect of the invention〕

As explained above, in the present invention, columnar tungsten in contact holes with different depths can be formed by tungsten CVD only once, so the manufacturing process can be simplified and shortened, and as a result, the length of the manufacturing process can be reduced. This effectively functions to reduce defects in device performance that increase with the increase in performance.

Furthermore, when embedding tungsten into the contact hole, the silicon thin film present at the bottom of the contact hole prevents the silicon of the source, drain, and gate wiring from being eroded and destroyed. It is possible to suppress a decrease in junction breakdown voltage, an increase in junction leakage, and a variation in contact resistance between the columnar tungsten and the source, drain, and gate wirings caused by this.

Furthermore, even when active layers including devices with complex structures are laminated, the unevenness on the element surface is flattened by etching back using a flattening agent, so it is possible to prevent wiring breakage.

[Brief explanation of drawings]

FIGS. 1(a) to (h) are schematic cross-sectional views in the order of manufacturing steps for explaining one embodiment of the present invention, and FIGS. 2(a) to (e)
) are schematic cross-sectional views in the order of manufacturing steps showing a conventional method for forming an active layer stacked device. 1... Silicon substrate, 2... Element isolation oxide film, 37
...Drain, 4.8...Source, 5,9...Kate, 5a, 9a=...Gate wiring, 6,10. :toa・・
・Oxide film, 11. lla, llb, 17.17a, 17
b...Columnar tungsten, 1213...Nitride film, 1
4... Wiring, 15... Silicon thin film, 16... Flattening agent.

Claims (1)

[Claims] In the formation of an active layer stacked device formed by stacking two active layers, a lower transistor is formed using a semiconductor substrate and a polycrystalline silicon film, and a first insulating film is coated on the entire surface. forming an upper layer transistor using the semiconductor film formed on the first insulating film and the polycrystalline silicon film,
A process of depositing a second insulating film with a predetermined thickness on the entire surface, forming contact holes for forming vertical wiring with different depths several times, and then applying LPC to deposit a silicon thin film on the entire surface.
a step of depositing by a VD method; a step of spin-coating a planarizing agent on the entire surface and etching back the entire surface until the planarizing agent and the silicon thin film are removed except in the contact hole; A method for forming an active multilayer device, comprising the steps of removing the remaining planarizing agent, performing selective CVD growth of tungsten on the silicon thin film, and burying tungsten in the contact hole.