JPH04340748A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04340748A JPH04340748A JP11202691A JP11202691A JPH04340748A JP H04340748 A JPH04340748 A JP H04340748A JP 11202691 A JP11202691 A JP 11202691A JP 11202691 A JP11202691 A JP 11202691A JP H04340748 A JPH04340748 A JP H04340748A
- Authority
- JP
- Japan
- Prior art keywords
- film
- cvd method
- protective film
- deposited
- protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 230000001681 protective effect Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000000992 sputter etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000009499 grossing Methods 0.000 claims abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 abstract description 11
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 5
- 239000010410 layer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多層配線上の保護膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a protective film on multilayer wiring.
【０００２】0002
【従来の技術】従来の半導体装置の製造方法は、図３に
示すように、半導体基板（図示せず）上に設けた絶縁膜
の上に下層のアルミニウム配線２を設け、アルミニウム
配線２の上に層間絶縁膜３を設けてコンタクトホールを
設け、コンタクトホールのアルミニウム配線２と接続す
る上層のアルミニウム配線４を設ける。次に、アルミニ
ウム配線４を含む表面に常圧ＣＶＤ法によりリンを約４
ｍｏｌ％含むＰＳＧ膜５を１μｍの厚さに堆積し、次に
、プラズマＣＶＤ法により窒化シリコン膜６を０．３〜
０．５μｍの厚さに堆積して保護膜を形成していた。2. Description of the Related Art As shown in FIG. 3, a conventional method for manufacturing a semiconductor device is to provide a lower layer of aluminum wiring 2 on an insulating film provided on a semiconductor substrate (not shown), and to An interlayer insulating film 3 is provided to provide a contact hole, and an upper layer aluminum wiring 4 is provided to connect to the aluminum wiring 2 in the contact hole. Next, about 4 phosphorus is applied to the surface including the aluminum wiring 4 by atmospheric pressure CVD.
A PSG film 5 containing mol% is deposited to a thickness of 1 μm, and then a silicon nitride film 6 is deposited to a thickness of 0.3 to 1 μm by plasma CVD.
It was deposited to a thickness of 0.5 μm to form a protective film.
【０００３】なお、保護膜としてプラズマＣＶＤ法によ
り酸窒化シリコン膜を１．３〜１．５μｍの厚さに設け
る場合もある。[0003] In some cases, a silicon oxynitride film is provided as a protective film by plasma CVD to a thickness of 1.3 to 1.5 μm.
【０００４】0004
【発明が解決しようとする課題】この従来の半導体装置
の製造方法では、ガスの反応により保護膜となる絶縁膜
を順次積層して形成するため、半導体基板上の段差が厳
しい部分、特に微細なコンタクトホール上の配線を被覆
する保護膜は積層する絶縁膜が段々にひさし状になり段
差部への反応ガスの到達を阻害し、絶縁膜の堆積が充分
に行われない。従って、図３に示すような空洞部７を生
じて耐湿性を低下させ断線等を発生し易いという問題点
があった。[Problems to be Solved by the Invention] In this conventional semiconductor device manufacturing method, insulating films that serve as protective films are sequentially stacked and formed by gas reactions. In the protective film that covers the wiring above the contact hole, the laminated insulating film gradually becomes eaves-like, which obstructs the reaction gas from reaching the stepped portion, and the insulating film is not deposited satisfactorily. Therefore, there is a problem in that a cavity 7 as shown in FIG. 3 is formed, the moisture resistance is reduced, and wire breakage is likely to occur.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に設けた多層配線を含む表面に
ＣＶＤ法により第１の保護膜を堆積する工程と、前記第
１の保護膜の表面をスパッタエッチして平滑化する工程
と、前記第１の保護膜の上にＣＶＤ法により第２の保護
膜を堆積する工程とを含んで構成される。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes the steps of: depositing a first protective film by CVD on a surface including multilayer wiring provided on a semiconductor substrate; The method includes a step of smoothing the surface of the film by sputter etching, and a step of depositing a second protective film on the first protective film by CVD.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【０００７】図１（ａ）〜（ｄ）は本発明の第１の実施
例を説明するための工程順に示した半導体チップの断面
図である。FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
【０００８】まず、図１（ａ）に示すように、半導体基
板（図示せず）の上に設けた絶縁膜１の上に下層のアル
ミニウム配線２を設け、アルミニウム配線２を含む表面
に層間絶縁膜３を堆積してコンタクトホールを設ける。
次にコンタクトホールを含む表面にアルミニウム層を堆
積してパターニングし、コンタクトホールのアルミニウ
ム配線２と接続する上層のアルミニウム配線４を形成す
る。次に、常圧ＣＶＤ法によりＰＨ３ ，ＳｉＨ４ ，
Ｏ２ を約４００℃で反応させて約４ｍｏｌ％のリンを
含有するＰＳＧ膜５を０．５μｍの厚さ（所望の保護膜
の約１／２の厚さ）に堆積させる。First, as shown in FIG. 1(a), a lower layer of aluminum wiring 2 is provided on an insulating film 1 provided on a semiconductor substrate (not shown), and an interlayer insulation layer is formed on the surface including the aluminum wiring 2. A film 3 is deposited to provide contact holes. Next, an aluminum layer is deposited on the surface including the contact hole and patterned to form an upper layer aluminum wiring 4 to be connected to the aluminum wiring 2 of the contact hole. Next, PH3, SiH4,
A PSG film 5 containing about 4 mol % of phosphorus is deposited to a thickness of 0.5 μm (about 1/2 the thickness of the desired protective film) by reacting O2 at about 400°C.
【０００９】次に図１（ｂ）に示すようにＡｒガス雰囲
気約１０−３Ｔｏｒｒの真空チャンバ内の平行平板電極
を用いてＡｒイオン９を発生させ３００〜７００Ｖ程度
で１〜３分のスパッタエッチを行いＰＳＧ膜５の表面を
平滑する。Next, as shown in FIG. 1(b), Ar ions 9 are generated using parallel plate electrodes in a vacuum chamber with an Ar gas atmosphere of approximately 10 −3 Torr, and sputter etching is performed at approximately 300 to 700 V for 1 to 3 minutes. to smooth the surface of the PSG film 5.
【００１０】次に、図１（Ｃ）に示すように、常圧ＣＶ
Ｄ法にてＰＳＧ膜５ａを０．５μｍの厚さに堆積する。Next, as shown in FIG. 1(C), normal pressure CV
A PSG film 5a is deposited to a thickness of 0.5 μm using method D.
【００１１】次に、図１（ｄ）に示すように、プラズマ
ＣＶＤ法により０．３〜０．４Ｔｏｒｒの圧力下におい
て、ＳｉＨ４ ，ＮＨ３ を約３００℃で反応させて、
厚さ０．３〜０．５μｍの窒化シリコン膜６を形成する
。Next, as shown in FIG. 1(d), SiH4 and NH3 are reacted at about 300° C. under a pressure of 0.3 to 0.4 Torr by plasma CVD method.
A silicon nitride film 6 having a thickness of 0.3 to 0.5 μm is formed.
【００１２】図２（ａ）〜（ｃ）は本発明の第２の実施
例を説明するための工程順に示した半導体チップの断面
図である。FIGS. 2A to 2C are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.
【００１３】図２（ａ）に示すように第１の実施例と同
様の工程で上層の配線４を形成した後、プラズマＣＶＤ
法により０．３〜０．４Ｔｏｒｒの圧力下においてＳｉ
Ｈ４ ，ＮＨ３ ，Ｎ２ Ｏを約３００℃で反応させ、
酸窒化シリコン膜８を０．８μｍの厚さに堆積する。As shown in FIG. 2(a), after forming the upper layer wiring 4 in the same process as in the first embodiment, plasma CVD
Si under a pressure of 0.3 to 0.4 Torr by method
H4, NH3, N2O are reacted at about 300°C,
A silicon oxynitride film 8 is deposited to a thickness of 0.8 μm.
【００１４】次に、図２（ｂ）に示すように、Ａｒイオ
ン９により酸窒化シリコン膜８の表面をスパッタエッチ
ングして平滑化する。Next, as shown in FIG. 2B, the surface of the silicon oxynitride film 8 is sputter-etched and smoothed using Ar ions 9.
【００１５】次に、図２（ｃ）に示すように、酸窒化シ
リコン膜８ａを堆積して保護膜を形成する。Next, as shown in FIG. 2C, a silicon oxynitride film 8a is deposited to form a protective film.
【００１６】[0016]
【発明の効果】以上説明したように本発明は、保護膜の
堆積とスパッタエッチを交互に組み合わせて保護膜を積
層することにより、保護膜の突出部分を少なくし、段差
の厳しい部分特にコンタクトホール上部の段差被覆性を
向上させることにより、保護膜の耐湿性を向上させて半
導体装置の信頼性を向上させる（約３０％上昇）という
効果を有する。As explained above, the present invention reduces the protruding parts of the protective film by laminating the protective film by alternately combining the deposition of the protective film and the sputter etching. Improving the coverage of the upper step has the effect of improving the moisture resistance of the protective film and improving the reliability of the semiconductor device (approximately 30% increase).
【図１】本発明の第１の実施例を説明するための工程順
に示した半導体チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための工程順
に示した半導体チップの断面図。FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.
【図３】従来の半導体装置の製造方法を説明するための
半導体チップの断面図。FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device.
【符号の説明】 １ 絶縁膜 ２，４ アルミニウム配線 ３ 層間絶縁膜 ５，５ａ ＰＳＧ膜 ６ 窒化シリコン膜 ７ 空洞 ８ 酸窒化シリコン膜 ９ Ａｒイオン[Explanation of symbols] 1 Insulating film 2,4 Aluminum wiring 3 Interlayer insulation film 5,5a PSG film 6 Silicon nitride film 7 Hollow 8 Silicon oxynitride film 9 Ar ion
Claims (1)
表面にＣＶＤ法により第１の保護膜を堆積する工程と、
前記第１の保護膜の表面をスパッタエッチして平滑化す
る工程と、前記第１の保護膜の上にＣＶＤ法により第２
の保護膜を堆積する工程とを含むことを特徴とする半導
体装置の製造方法。1. Depositing a first protective film by CVD on a surface including multilayer wiring provided on a semiconductor substrate;
A step of smoothing the surface of the first protective film by sputter etching, and forming a second protective film on the first protective film by CVD.
A method for manufacturing a semiconductor device, comprising the step of depositing a protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11202691A JPH04340748A (en) | 1991-05-17 | 1991-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11202691A JPH04340748A (en) | 1991-05-17 | 1991-05-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04340748A true JPH04340748A (en) | 1992-11-27 |
Family
ID=14576143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11202691A Pending JPH04340748A (en) | 1991-05-17 | 1991-05-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04340748A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5987834A (en) * | 1982-11-11 | 1984-05-21 | Toshiba Corp | Forming method of thin-film |
-
1991
- 1991-05-17 JP JP11202691A patent/JPH04340748A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5987834A (en) * | 1982-11-11 | 1984-05-21 | Toshiba Corp | Forming method of thin-film |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970722 |