JPH04340149A - Failure diagnostic system - Google Patents

Abstract

PURPOSE:To obtain a failure diagnostic system capable of easily and rapidly executing the failure diagnosis of a bus conversion module, the division of a fault position, etc., only by the bus conversion module alone without connecting an adaptor or the like to an extended bus. CONSTITUTION:In the failure diagnostic system of the bus conversion module 3 connected between a basic bus 2 for connecting a CPU 1 to a memory 6 and the extended bus 4 connected to an adaptor 5 so as to extend the bus, a bus control part on the extended bus side in the module 3 is separated into a master control part 35 and a slave control part 36 so as to independently operate them and an address and diagnostic data from the master control part 35 are sent to the slave control part 36 through the extended bus 4 and the diagnostic data are sent to the memory 6 by means of DMA transfer to execute the failure diagnosis of the bus conversion module 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault diagnosis method, and more particularly to a fault diagnosis method that allows failure diagnosis of a bus conversion module by itself without connecting an adapter to the expansion bus side. . Such a failure diagnosis is usually performed when the system is started up or when an abnormality occurs in the device.

0002

2. Description of the Related Art FIG. 4 is a diagram showing a conventional configuration. In the figure, 1 is a CPU, 2 is a basic bus, 3 is a bus conversion module, 4 is an expansion bus, and 5 is an adapter. In such a configuration, there are two ways to diagnose the failure of the bus conversion module 3. One is to access the register in the bus conversion module 3 from the CPU 1 via the basic bus 2, and diagnose whether or not it is responding normally. In this case, the input side (basic bus side) of the bus conversion module 3 can be diagnosed using normal data without using any particular diagnostic data. The second diagnosis is for the output side (expansion bus side) of the bus conversion module 3. In this case, connect adapter 5 to expansion bus 4.
If the CPU 1 connects the adapter 5, accesses the adapter 5 from the CPU 1, and operates the adapter 5 normally, it is determined that the bus conversion module 3 including the system is normal.

[0003] Such a conventional fault diagnosis method originates from the function of the bus control unit on the expansion bus side in the bus conversion module 3, and conventionally, it has been used to control and send data to the expansion bus 4 as a master. This is because a single bus control unit performs the function of receiving data from the expansion bus 4 as a slave.

0004

[Problems to be Solved by the Invention] In this way, in the conventional method, when diagnosing a failure of a bus conversion module, the diagnosis on the expansion bus side is always performed with an adapter connected to the expansion bus, and the bus conversion module alone cannot be used. can't do it. Therefore, especially when diagnosing multiple bus conversion modules, an adapter must be connected each time, which causes trouble in diagnosing failures and in isolating the location of the abnormality in the event of an error. there were.

[0005] An object of the present invention is to provide a fault diagnosis method that can easily and quickly perform fault diagnosis and isolation of a fault location using a bus conversion module alone, without connecting an adapter or the like to an expansion bus. It is in.

[0006]

[Means for Solving the Problems] FIG. 1 is a basic configuration diagram of the present invention. In FIG. 1, 31 is a bus control unit on the basic bus side, 32 is a P mode access buffer, 33 is a diagnostic register, 34 is a DMA buffer, 35 is a master control unit on the expansion bus side, and 36 is a slave control unit on the expansion bus side. . As shown in the figure, in the present invention, the bus control section on the expansion bus side is separated into a master control section 35 and a slave control section 36, and the function of transmitting data as a master and the function of receiving data as a slave are separated.

[0007]

[Operation] In the present invention, as described above, the bus control section on the expansion bus side in the bus conversion module is separated into the master control section 35 and the slave control section 36, and the adapter 5 is not connected to the expansion bus 4. It allows access within the own board within the bus conversion module 3. When the diagnostic data is written to the diagnostic register, it is automatically sent to the adapter 5 connected to the expansion bus 4 via the expansion bus 4.
The data is sent to the memory 6 on the basic bus side, making it appear as if the data has been transferred from the main bus. With this configuration, failure diagnosis can be performed by the bus conversion module alone without connecting an adapter or the like to the expansion bus 4, making failure diagnosis and isolation of the fault location much easier than in the past.

[0008]

Embodiment FIG. 2 is a block diagram of an embodiment of the bus conversion module of the present invention. In the figure, the same components as in FIG. 1 are given the same numbers. 37 is a diagnostic control section, 38 is an expansion bus arbiter 38, 39 is a system arbiter, and 40 is a register read/write control section. The diagnostic register 3 has an address register 331 and a data register 332. The diagnostic control unit 37 has registers that store control flags a, b, and c.

As shown in FIG. 2, the diagnostic register 33 has an address register for addresses and a data register for data. The diagnostic register 33 outputs the address of the address register as the address of the expansion bus, and outputs the data of the data register as the data of the expansion bus. The address of the address register specifies the address of the memory (MSU) 6 connected to the basic bus 2. The slave control unit 36 reads the address and takes in the data. When the slave control section 36 takes in the data, it performs DMA transfer of the data to the memory 6 via the DMA buffer 34 and the bus control section 31 on the basic bus side.

The processing steps of the present invention will now be described in detail. The CPU prepares diagnostic data DA and address ADD, which are passed through the P mode access buffer 32,
It is written to the address register 331 and data register 332 of the diagnostic register 33. A detection unit (not shown) of the diagnostic control unit 37 detects that address information ADD has been written to the address register 331, and sets the diagnostic activation flag of register a to “1”. When this flag becomes "1", a bus request BRQ is sent to the expansion bus arbiter 38. Address ADD and data DA of diagnostic register 33
is sent to the master control section 35, further sent to the slave control section 36 via the expansion bus 4, and taken into the DMA buffer 34.

Next, the address ADD and data DA are transferred from the DMA buffer 34 to the memory 6 via the basic bus 2. When the data transfer from the DMA buffer 34 to the memory 6 is completed, a completion notification S1 is sent to the register b of the diagnostic control unit 37, and a normal completion notification S2 is sent from the register b to the P mode access buffer 32. P mode buffer 32
is a buffer for accessing the CPU, and is a split access that temporarily releases the bus. The P-mode buffer is in contrast to the DMA buffer 34, which performs direct memory access without going through the CPU. Therefore,
When the P mode buffer 32 receives the normal end notification S2 and the abnormal end notification S3, it notifies the CPU of normality and abnormality in a split response cycle. Further, the DMA buffer 34 sends a bus request BRQ to the system arbiter 39.

Register c of the diagnostic control section 37 receives the error ER from the DMA buffer 34, master control section 35, slave control section 36, etc. and sends an abnormal processing notification S3 to the P mode buffer 32. Then, the CPU compares the diagnostic data written in advance in the memory 6 with the data written in the diagnostic register 33 and returned via the master control unit 35, slave control unit 36, and DMA buffer 34 to perform failure diagnosis. Note that a register read/write control section is provided between the P mode buffer and the register to control the register.

FIG. 3 is a processing sequence diagram of the present invention. As shown in the figure, addresses and diagnostic data are fetched from the CPU to the P-mode buffer via the basic bus, and within the bus conversion module, addresses and diagnostic data are fetched from the P-mode buffer to the diagnostic register, and then via the expansion bus to the diagnostic register. from the DMA buffer, and from the DMA buffer to the memory via the basic bus. On the other hand, normal termination and abnormal termination are transferred to the CP via the P mode buffer.
A response is sent to U.

[0014]

[Effects of the Invention] As explained above, according to the configuration of the present invention, failure diagnosis can be performed by the bus conversion module alone without connecting an adapter or the like to the expansion bus, making it extremely easy to diagnose the failure and isolate the location of the failure. This can significantly reduce the time required for fault diagnosis, especially in systems that connect multiple bus conversion modules.

Furthermore, individual operations, ie, P-mode buffer access, DMA buffer access, master control unit transfer, slave control unit transfer, etc., can be easily diagnosed.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a processing sequence diagram of the present invention.

FIG. 4 is a general system configuration diagram.

[Explanation of symbols]

1...CPU, 2...Basic bus, 3...Bus conversion module, 4...Expansion bus, 5...Adapter 31...bus control unit, 32...P mode buffer, 33...Diagnostic register, 34...DMA buffer, 35...Master control unit, 36...Slave control unit, 37...Diagnosis control unit, 38...Expansion bus arbiter, 39...System bus arbiter.

Claims (5)

[Claims] [Claim 1] A basic bus (
In a fault diagnosis method for a bus conversion module (3) that is connected between the expansion bus (4) that connects the bus conversion module 1) and the adapter and that expands the bus, the bus control unit on the expansion bus side in the bus conversion module is mastered. The control unit (35) and the slave control unit (36) are separated and can operate independently, and the address and diagnostic data from the master control unit are sent to the slave control unit via the expansion bus, and the data are transferred by DMA transfer. A fault diagnosis method characterized in that a fault diagnosis of the bus conversion module is performed by sending diagnostic data to a memory. 2. The fault diagnosis method according to claim 1, wherein a diagnostic register (33) is provided in the bus conversion module, and the diagnostic register has an address register and a data register for receiving addresses and data from the CPU. 3. A diagnostic control unit (37) is provided in the bus conversion module, and the diagnostic control unit controls the CPU so that it can determine whether the DMA transfer is normal or abnormal after all DMA transfers are completed.
2. The fault diagnosis method according to claim 1, wherein the fault diagnosis method notifies the user. 4. The failure diagnosis method according to claim 1, wherein addresses and data are transferred from the CPU to the master control unit in P mode using split access, and DMA transfer is performed from the slave control unit to the memory. 5. The failure diagnosis method according to claim 1, wherein the bus conversion module, the master control section, and the slave control section are configured on a single board.