JPH04338862A - Computer system - Google Patents

Abstract

PURPOSE:To constitute a multiprocessor computer system where the exception handling occurring in a sub-CPU is executed in a main CPU at a high speed. CONSTITUTION:If a first processor detects the occurrence of an exception by operation, an incorporated pipeline control circuit 40 receives this detection to continue execution of the instruction to be executed before the instruction, where the exception occurs, and reads out this instruction and the following instruction stored in a pipeline. Operation circuits output information required for exception detection to an exception detecting circuit. At the time of the occurrence of the exception, a second processor executes handling of the exception, which occurs in the first processor, and the following instruction if the pipeline control circuit incorporated in the first processor performs the execution processing of the instruction to be executed before the instruction where the exception occurs. Thus, the exception handling speed is increased.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system that speeds up exception processing.

0003

2. Description of the Related Art In the field of computers, it is common practice to employ multiprocessors or pipeline control that fetches and executes instructions in parallel in order to speed up arithmetic processing. In a computer system that uses a pipeline control method, when an exception occurs due to an arithmetic instruction, the pipeline is stopped by an interrupt, the instructions in the pipe are read by software, and the instruction in which the exception occurred and the instructions following it are processed. It was processed through software emulation. However, this method requires a large amount of time for exception handling. For example, an exception occurs when hardware cannot perform an extended precision operation, and the instruction in which the exception occurs is emulated by software. When an instruction following the instruction that caused the exception is in the queue, software emulation is executed even if the instruction is executable in hardware, which causes delays in exception handling. To resolve this, if an exception occurs,
The instruction that caused the exception is emulated by software, and the subsequent instructions are stored in memory again by software, loaded into the instruction queue in the same way as normal instruction execution, and executed using the hardware arithmetic circuit. In some cases, this speeds up exception handling. FIG. 3 is a flowchart showing a conventional process when an exception occurs. In this example, in a computer system with a multiprocessor configuration, an exception that occurs in a sub CPU is processed by the sub CPU according to the above-described procedure.

0004

[Problem to be Solved by the Invention] According to the conventional example described above, exceptions that occur in the sub-CPU are handled by the sub-CPU, so when an exception occurs, the instruction that caused the exception is exception handling cannot be executed until the instruction that should be executed first is completed. Therefore, there is a disadvantage that a large amount of time is required for exception processing.

[0005] The present invention was made in view of the above circumstances, and in a computer system having a multiprocessor configuration, exception handling occurring in a sub CPU is carried out by the main CPU.
The object of the present invention is to provide a computer system that can be executed at high speed on a PU.

[Configuration of the invention]

[0007]

[Means for Solving the Problems] The present invention provides a computer system in which when an exception occurs in a first processor, a second processor executes the exception handling.
The first processor includes a circuit that detects an exception due to an operation, a pipeline that holds instructions, and a control that executes an instruction that should be executed before the instruction that generated the exception when an exception occurs. The first processor has a pipeline control circuit that reads information about the instruction that caused the exception and its successor instructions in the pipeline while executing the exception, and an arithmetic circuit that supplies exception information to the exception detection circuit.
A pipeline control circuit supplies instructions to be executed by the second processor to the second processor, and when an exception occurs in the first processor, the pipeline control circuit processes instructions to be executed before the instruction in which the exception has occurred. The present invention is characterized in that it includes an instruction execution control circuit that handles exceptions and executes subsequent instructions when the instruction is executed.

[0008]

[Operation] In the computer system described above, the first
The processor detects when an exception occurs due to an operation, and upon receiving this, the pipeline control circuit continues execution of the instruction that should be executed before the instruction that caused the exception. Reads the instruction and the instructions subsequent to the instruction that caused the exception stored in the pipeline. The arithmetic circuit built into the first processor outputs information necessary for detecting an exception to the exception detection circuit. When an exception occurs in the second processor, the exception occurs in the first processor while the built-in pipeline control circuit of the first processor executes an instruction that should be executed before the instruction in which the exception occurred. handle the exception and execute the subsequent instruction. If an exception occurs in the first processor,
When an instruction that should be executed before the instruction that caused the exception is being executed inside the first processor, the exception is handled by the second processor without the instruction ending. The speed can be increased.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, numeral 1 is a memory, and a program,
Store data. Reference numeral 2 is an input/output port, to which an input/output device used by the user is connected. Execution of an instruction is started by input from this input/output port. Reference numeral 3 denotes a main CPU (second processor), which inputs and outputs data, instructions, etc. to the memory 1, input/output port 2, and sub CPU (first processor). Main CP
U3 has a function of sending instructions other than those to be executed by itself, that is, instructions to be executed by the sub-CPU 4, to the sub-CPU 4, and executing the process when an exception occurs in the sub-CPU 4. Code 4 is the sub CPU, which is the main CPU
3 receives instructions to be executed by the sub CPU 4 and executes them. When an exception occurs, the information is transmitted to the main CPU 3, and the information required by the sub CPU 3 is sent to the sub CPU 3. When an exception occurs, instructions that should be executed before the instruction in which the exception occurs are continuously executed without being hindered by the exception handling by the main CPU 3.

Reference numeral 30 is a data bus. The data bus 30 is used when the main CPU 3 exchanges data with the memory 1 and the input/output port 2. Reference numeral 39 is an address/control signal line, which is used when the main CPU 3 specifies addresses of the memory 1 and input/output ports 2, and controls read/write. Reference numeral 31 is a signal line, which connects the main CPU 3 to the sub CPU 4.
When sending an instruction to be executed by the PU 4, the instruction is exchanged via this signal line. Reference numeral 32 denotes a signal line, through which signals for control are transferred when the main CPU 3 exchanges calculation data with the sub CPU 4. Reference numeral 33 is a data line, which connects the main CPU.
3 inputs and outputs calculation data and calculation results to and from the sub CPU 4. The main CPU 3 controls the direction of data on the data line 33 using the signal line 32 . code 3
4 is a signal line, and this signal is activated when the main CPU 3 sends an instruction to be executed by the sub CPU 4 to the sub CPU 4 through the signal line 31. Reference numeral 35 is a signal line, and the signal line 35 is used to notify the main CPU 3 that the main CPU 4 is currently unable to input or output calculation data or calculation results. Reference numeral 36 is a signal line;
The sub CPU 4 currently sends a new command via the signal line 31.
The main CPU 3 is notified via this signal line 36 that it cannot be received. Reference numeral 37 is a signal line, and when the main CPU 4 detects an exception, this signal line 37
is used to send information about exceptions such as the occurrence of an exception to the main C
Notify PU3.

Reference numeral 40 is a pipeline control circuit;
Controls the pipeline built into the sub CPU 4. When an exception occurs, execution continues to be controlled prior to the instruction in which the exception occurred. At the same time, sub CPU3
also executes control to read the instruction that caused the exception and its successor instructions. Reference numeral 410 denotes an instruction queue 1 (Q1), which is a first-stage instruction queue that first receives instructions sent from the main CPU 3 through the signal line 31. Reference numeral 401 is a signal line that transfers a latch enable signal generated by the sub CPU 4. Reference numeral 411 is a signal line that outputs information transferred through the signal line 410. Reference numeral 420 denotes an instruction queue 2 (Q2), which is a second-stage instruction queue that latches the instructions sent from the instruction queue 410 through the signal line 411. Code 402 is sub-C
The latch enable signal (signal line 420) generated by PU4
). Reference numeral 421 is a signal that outputs information transferred via the signal line 420. Reference numeral 430 is instruction queue 3 (Q3), and signal line 421 is connected from instruction queue 420 to instruction queue 3 (Q3).
This is the third stage instruction queue that latches instructions sent through the . Reference numeral 440 denotes an instruction queue (Q4), which is a fourth-stage instruction queue that latches the instructions sent from the instruction queue 430 through the signal line 431. code 403
is a latch enable signal (signal line 430) generated by the sub CPU 4. Reference numeral 431 is a signal line that outputs information of the instruction queue 430. Reference numeral 450 is an instruction queue (
Q5), which is the fifth stage instruction queue that latches the instruction sent from the instruction queue 440 through the signal line 441. Reference numeral 404 is a latch enable signal for the instruction queue 440 output by the sub CPU 4. Reference numeral 441 is a signal that outputs information on the instruction queue 440.

Reference numeral 50 indicates an arithmetic circuit 1, and a signal line 41
The instruction queue 410 information received through the instruction queue 410 is used to execute operations. Here, reading the operand data,
Checks the operand data. Reference numeral 501 is a signal line, and information regarding the calculation result of the calculation circuit 1 (50) is output to this signal line. Reference numeral 502 is a signal line, and the arithmetic circuit 50 outputs information regarding the exception to this signal line. Reference numeral 503 is a signal line, and the arithmetic circuit 50 outputs information regarding selection of data to be operated on to this signal line. code 5
04 is a signal line, and the arithmetic circuit 1 (50) reads data on this signal line as data to be operated on. Reference numeral 60 is an arithmetic circuit 2, which executes an arithmetic operation following the arithmetic circuit 1 (50) based on the information of the arithmetic circuit 1 (50) received from the signal line 501 and the information of the arithmetic circuit 1 (50) received from the signal line 501. . Reference numeral 601 is a signal line, which connects the arithmetic circuit 2 (60
) is output to this signal line. Reference numeral 602 is a signal line, and the arithmetic circuit 2 (60) outputs information regarding the exception to this signal line. Reference numeral 70 denotes the arithmetic circuit 3, which executes the arithmetic circuit 2 (60) based on the information of the instruction queue 430 received via the signal line 431 and the information of the arithmetic circuit 2 (60) received via the signal line 601.
Continuing from step 0), the calculation is executed. Reference numeral 701 is a signal line, and the arithmetic circuit 3 (70) outputs information regarding its own arithmetic results to this signal line. Reference numeral 80 is an arithmetic circuit 4, which receives an instruction queue 440 via a signal line 441.
information and the arithmetic circuit 3 received via the signal line 701.
Based on the information in (70), the calculation circuit 3 (70) continues to perform calculations. Arithmetic circuit 4 (80) outputs a calculation result. Arithmetic circuits 1, 2, 3, 4 (50, 6 respectively)
0, 70, 80), the calculation is executed in a set of four.

Reference numeral 801 is a signal line, which connects the arithmetic circuit 4 (
80) outputs information for detecting an exception occurring as a result of the operation to this signal line. Reference numeral 802 is a signal line;
A control signal for storing the result of the calculation performed by the calculation circuit 4 (80) is output here. Reference numeral 803 is a signal line to which the calculation result of the calculation circuit 4 (80) is output. Reference numeral 90 is a register file, which stores data necessary for calculations and also stores calculation results. Inside the register file 90, there are a decoder, a selector, and one or more registers, and data can be input, held, and output by controlling each part. The register file 90 has one input-only port and its control input, one output-only port and its control input, and one bidirectional input/output port and its control input, and has signal lines 504 and 50, respectively.
3, 803, 802, 33, and 32.

Reference numeral 100 denotes an exception detection circuit 1, which inputs the information of the signal line 502 outputted by the arithmetic circuit 1 (50), and when an exception is detected from the information, the signal is sent to the pipeline control circuit through the signal line 101. 40 of the occurrence of the exception. Reference numeral 110 is an exception detection circuit 2, which is an arithmetic circuit 2.
(60) is inputted to the signal line 602, and when an exception is detected from the information, the pipeline control circuit 40 is notified of the occurrence of the exception through the signal line 111. Reference numeral 120 is the exception detection circuit 3, and the arithmetic circuit 4 (8
0) is input to the signal line 801, and when detected based on the information, the occurrence of an exception is notified to the pipeline control circuit 40 through the signal line 121. code 13
0 is a selector, and signal lines 411, 421, 451
The data of the instruction queues 410, 420, and 450 is inputted through the signal line 38, and is outputted to the main CPU 3 through the signal line 38. Control of which data is selected is controlled by a control signal outputted by the pipeline control circuit 40 through the signal line 406. Reference numeral 301 is a signal line, and the main CP
This is a signal line used when U3 executes exception processing and reads instructions from the instruction queue 40.

FIG. 2 is a flowchart showing an outline of the operation of the embodiment of the present invention. Specifically, the flow from reading one instruction from memory to completing execution is shown. In the figure, the symbol S0 indicates the start. Main C through input/output port 2
This process is started when the PU 3 receives an instruction to read an instruction or when executing the next instruction following the previously executed instruction. Reference numeral S1 is a step in which the main CPU 3 reads an instruction, and the main CPU 3 outputs an address and a read/write control signal to the memory 1 to read the instruction. Reference numeral S2 is a step for determining whether the instruction read in step S1 is an instruction to be executed by the main CPU 3 or an instruction to be executed by the sub CPU 4. Reference numeral S3 is a step in which the main CPU 3 executes the instruction read in step S1. The code S4 indicates that the main CPU 3 is in step S.
This step is to send the instruction read in step 1 to the sub CPU 4, and the sub CPU 4 receives this instruction in order to execute it. Reference numeral S5 is a step in which the sub CPU 4 executes the instruction received from the main CPU 3 in step S4. Reference numeral S6 is a step for detecting an exception due to the operation executed in step S5. Reference numeral S7 is a step for executing exception handling, in which the main CPU 3 executes the instruction that caused the exception and its subsequent instructions while executing the instruction that should be executed before the instruction that caused the exception in the sub CPU 4. It is read from the sub CPU 4 and executed by the main CPU 3. Reference numeral S8 is a step indicating the end of execution of one instruction.

The operation of the embodiment of the present invention will be explained in detail below. First, we will explain the operation of a normal pipeline. Initially, the entire device is in a waiting state. Main C
The PU3 outputs a control signal to the signal line 39 to indicate to the data line 30 that an operation start input is input to the input/output port 2.
It is monitored through. When a start input is received at the input/output port 2, the main CPU 3 starts reading instructions. The main CPU 3 uses a signal line 39 to read instructions.
A control signal for retrieving the contents from memory 1 is output. Next, the main CPU 3 reads the command output from the memory 1 to the data line 30. If the instruction read by the main CPU 3 is an instruction that should be executed by the main CPU 3, the main CPU 3 executes the instruction. In the embodiment of the present invention, the main CPU 3 executes data load/store instructions and integer operation instructions, and the sub CPU 4 executes floating point operations. Therefore, if the instruction is a floating point arithmetic instruction, the main CPU 3 sends the instruction to the instruction queue 1 (reference numeral 410) inside the sub CPU 4 through the signal line 31. At the same time, the main CPU 3 notifies the signal line 34 that a floating point instruction (an instruction to be executed by the sub CPU) has been sent. At this time, if instruction queue 1 (
410) is in a state where it cannot read a new instruction, it transmits information to the main CPU 3 through the signal line 35 that the pipeline control circuit 40 cannot receive a new instruction from the main CPU 3. In this case, main CPU3
continues the operation of reading the information on the signal line 35 and sending instructions to the instruction queue Q1 (410) until a new instruction can be accepted via the signal line 401. Details of this operation will be described later.

Next, the instruction queue 410 transmits the input information as described above through the signal line 411 to the pipeline control circuit 40, instruction queue 2 (420), and arithmetic circuit 1 (5).
0), 130. The arithmetic circuit 1 (50) analyzes the data arriving via the signal line 411 and sends it to the signal line 503.
The data in the register file 90 is passed through the arithmetic circuit 1 (
50). Arithmetic circuit 1 (50) is connected to signal line 50
4, the data output from the register file 90 is sent to the signal line 501. Further, information regarding the type of instruction transferred through the signal line 411 is sent to the exception detection circuit 1 (100) through the signal line 502. The exception detection circuit 100 analyzes the type of instruction and checks whether there is an exception. Based on the information sent to the signal line 502, if the instruction cannot be executed by the pipeline control circuit 40, the signal line 101
The pipeline control circuit 40 is notified of the occurrence of the exception through.

The instruction queue 2 (420) receives the data of the instruction queue 1 (410) which is generated by the pipeline control circuit 40 and sent to the signal line 411 in accordance with the signal transferred via the control signal 402. and holds the data through the signal line 421 to the pipeline control circuit 40,
It is sent to instruction queue 3 (430), arithmetic circuit 2 (60), and selector 130. Arithmetic circuit 2 (60) is connected to signal line 5
The data sent from the arithmetic circuit 1 (50) through the signal line 420 and the instruction queue 2 (4
20) and sends the result to the signal line 601. Further, the arithmetic circuit 2 (60) analyzes the data sent from the arithmetic circuit 2 (60) through the signal line 602 for information regarding the consistency of input data. The exception detection circuit 110 checks the consistency (X÷
0, etc.) to determine whether an exception has occurred. Then, whether or not an exception has occurred is sent to the pipeline control circuit 40 through the signal line 111.

The instruction queue 3 (430) inputs and holds the data of the instruction queue 2 (420) sent to the signal line 421 according to the control signal (403) generated by the pipeline control circuit 40, and stores the data. is connected to the pipeline control circuit 40 and the instruction queue 4 (44) through the signal line 431.
0) and is sent to the arithmetic circuit 3 (70). Arithmetic circuit 3 (7
0) is the data sent by the arithmetic circuit 2 (60) through the signal line 601 and the data sent by the instruction queue 3 (430) through the signal line 43.
The arithmetic circuit 2 (60) then executes arithmetic operations based on the data sent through the arithmetic circuit 2 (60). The instruction queue 4 (440) receives a control signal (40) generated by the pipeline control circuit 40.
4), the instruction queue 3 (
430) is input and held, and the data is sent to the pipeline control circuit 40, instruction queue 5 (450), and arithmetic circuit 4 (80) through a signal line 441. The arithmetic circuit 4 (80) is connected to the signal line 7 by the arithmetic circuit 3 (70).
Based on the data outputted through 01 and the data outputted from instruction queue 4 (440) through signal line 441, the operation circuit 3 (70) continues to execute the operation. The result is
The data is written to the register file 90 according to the control signal output through the signal line 802. The data written to the register file 90 is outputted to the register file 90 by the arithmetic circuit 4 (80) through the signal line 803. Further, the register file 90 outputs information regarding the calculation result to the exception detection circuit 3 (120) via the signal line 801. The exception detection circuit 3 (120) checks whether an exception has occurred based on the information sent to the signal line 801, and notifies the pipeline control circuit 40 of the presence or absence of an exception through the signal line 121.

The instruction queue 4 (
440) is latched into the instruction queue 5 (450) according to a control signal output by the pipeline control circuit 40 through the signal line 406. Information output through the signal line 451 is sent to the selector 13 through the signal line 451.
Sent to 0. If no exception occurs, each of the above,
The operation continues. That is, when the main CPU 3 successively reads instructions to be executed by the sub CPU 4, if a certain instruction is in the instruction queue 5 (450), the next instruction is placed in the instruction queue 4 (440), and then the next instruction is placed in the instruction queue 4 (440). is placed in instruction queue 3 (430), and the next instruction is placed in instruction queue 2 (430).
(420), the next instruction is placed in instruction queue 1 (410)
It's in. Operations are executed on these instructions as they progress through the pipeline. When using the execution result of an instruction executed earlier in the pipeline as a source for a later instruction, the instruction queue 1 (410
) and does not transfer control to the next queue (420). At this time, the pipeline control circuit 40 notifies you through the signal line 35 that no new instructions can be accepted, and also notifies you through the signal line 401 of the instruction queue 1 (410
) data is held, and new data is not input to the instruction queue 2 (420) through the signal line 402.

When the main CPU 3 inputs a read/write instruction for the register file 90 of the sub CPU 4, the main CPU 3 pipes a control signal (address, read/write control) regarding the read/write of the register file 90 through the signal line 32. It is sent to the line control circuit 40 and register file 90. At this time, if the data specified by the address is in use, the pipeline control circuit 40 notifies you through the signal line 36 that the register file 90 is in use, and the main CPU 3 requests read/write regarding the register file 90. Prohibited from execution. In this case, the main CPU 3 suspends the execution of the read/write command until the register file 90 becomes available and enters a waiting state, and executes the read/write as soon as it becomes executable.

[0022] Here, a supplementary explanation will be given regarding the fact that the register file 90 is in use. When the main CPU 3 attempts to read the register where the execution results of the instructions stored in the instruction queue 1 (410) are stored, the instructions in the instruction queue 1 (410) have finished executing and the operation results are If the data is read before being written to the register file 90, the data will be incorrect. Therefore, it is necessary to store the instruction in the instruction queue 5 (450) and execute the read instruction after writing to the register file 90 is completed. That is, the pipeline control circuit 4
When the main CPU 3 reads/writes the register storing the operand data of the instruction inside the instruction queue 0 and the register storing the operation result, the instruction in the instruction queue inside the pipeline control circuit 40 Execute after reading the register storing the operand data and storing the operation result. If there are multiple registers in the register file 90 and there is no overlap as described above,
The main CPU 3 reading/writing the register file 90 and the instruction queue reading/writing can be performed in parallel.

[0023] Hereinafter, the operation when an exception occurs will be explained in detail. First, when the exception detection circuit 103 detects an exception, the pipeline control circuit 40 stops normal pipeline operation and enters a mode for processing the exception. At this time, even if an instruction is stored in the instruction queues 410 to 440, the operation is not executed and is interrupted. The pipeline control circuit 40 connects the main CPU through the signal line 37.
3 that the exception detection circuit 120 has detected an exception, and at the same time selects the data output to the signal line 451 to the selector 130 through the signal line 406 and sends it to the pipeline control circuit 40 through the signal line 38. Notify of sending. The main CPU 3 thereby starts exception handling. The selector 130 receives the contents of the instruction queue 5 (450) through the signal line 451 in accordance with this, and
It is sent to the main CPU 3 through the signal line 38. The main CPU 3 performs exception processing for this instruction.

Next, if it is necessary to continue executing the instruction following the instruction that caused the exception, the pipeline control circuit 4
0 returns the pipeline operation to normal and performs the operations described above. If there is no need to execute the instruction that caused the exception, the main CPU 3 transmits the information to the pipeline control circuit 40 through the signal line 301, and the pipeline control circuit 40 uses the signal lines 401, 402, 4 based on the information to be executed.
03, outputs a control signal to 404, and outputs a control signal to the instruction queue (410
, 420, 430, 440). When the exception detection circuit 100 detects an exception and a signal to that effect arrives on the signal line 101, the pipeline control circuit 40 detects that the instruction is sent to the instruction queues 420 and 430 at that time.
, 440, the process is executed in the same manner as described above. Similarly, the instruction queue 4 output through the signal line 411
The main CPU 3 receives the data of 10, and the main CPU 3 receives the data.
PU3 performs exception handling for this instruction. Thereafter, processing continues for the next instruction to be executed. Exception detection circuit 11
0 detects an exception and a signal to that effect is output to the signal line 111, the pipeline control circuit 40 controls the instruction queue 2 (420) through the instruction queue 2 (420), the selector 130, and the signal line 38, as described above. data to main CPU3
and the main CPU 3 performs exception handling. At this time,
If there is an instruction in instruction queue 1 (410), instruction queue 2
Until the exception handling for the instruction (420) is completed,
Instruction queue 1 (410) is controlled to be held by pipeline control circuit 40. Main CPU
After the exception handling of the instruction in instruction queue 2 (420) that caused an exception in step 3 is completed, if it is necessary to continue executing the instruction in instruction queue 1 (410), execute it, and if it is not necessary, cancel it as above. do. 'If exceptions occur simultaneously in a plurality of exception detection circuits, the exception handling for the instructions at the lower stage of the instruction queue is performed first. For example, exception detection circuit 1
If an exception is similarly detected at 00, 110, or 120, exception processing is first performed for the instruction stored in the instruction queue 5 (450). When executing the subsequent instruction after completing the exception handling of the instruction in instruction queue 5 (450),
Next, instruction queue 4 (440), instruction queue 3 (430)
If there is an instruction, after executing it, the instruction queue 2 (42
0). Furthermore, the instruction queue 2 (420
), if it is necessary to execute an instruction subsequent to the instruction in instruction queue 1 (410), exception handling is performed for the instruction in instruction queue 1 (410).

After executing the exception handling for the instruction set in the instruction queue 5 (450), if there is no need to execute the subsequent instruction, the subsequent instruction is canceled as described above. Therefore, the exception handling for the instructions in the instruction queue 2 (420) and instruction queue 1 (410) that have generated an exception is canceled without being performed, and the next instruction to be executed is executed. The same applies when exceptions are detected simultaneously in the exception detection circuits 100 and 110, and the exception handling for instruction queue 2 (420) is executed first, and if necessary (if the instruction in the instruction queue 410 is not canceled) ), then instruction queue 1 (41
Execute exception handling for the instruction 0).

[0026]

[Effects of the Invention] As explained above, according to the present invention, when an exception occurs within the sub CPU, the instruction that should be executed before the instruction that caused the exception is executed within the sub CPU. In some cases, the main CPU can handle exceptions without waiting for their completion, thereby speeding up exception handling.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing an outline of the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing an outline of the operation of the conventional example.

[Explanation of symbols]

1...Memory 2...Input/output port 3...Main CPU 4...Sub CPU 40...Pipeline control circuit 50, 60, 70, 80...Arithmetic circuit 90...Register file 100, 110, 120...Exception detection circuit 130...Selector

Claims (1)

[Claims] 1. A computer system in which when an exception occurs in a first processor, a second processor executes the exception handling, wherein the first processor includes a circuit for detecting an exception due to an operation, and an instruction. When an exception occurs, the instruction that caused the exception and its successors are controlled to be executed first. The first processor has a pipeline control circuit that reads instruction information and an arithmetic circuit that supplies exception information to an exception detection circuit, and the first processor supplies instructions to be executed by the second processor to the second processor. together with the first
When an exception occurs in the processor, the instruction execution control handles the exception and executes the subsequent instruction while the pipeline control circuit is processing an instruction that should be executed before the instruction in which the exception occurred. A computer system comprising a circuit.