JPH04335544A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH04335544A
JPH04335544A JP10546591A JP10546591A JPH04335544A JP H04335544 A JPH04335544 A JP H04335544A JP 10546591 A JP10546591 A JP 10546591A JP 10546591 A JP10546591 A JP 10546591A JP H04335544 A JPH04335544 A JP H04335544A
Authority
JP
Japan
Prior art keywords
thick film
electrode
semiconductor device
semiconductor chip
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10546591A
Other languages
Japanese (ja)
Inventor
Tsukasa Shiraishi
司 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10546591A priority Critical patent/JPH04335544A/en
Publication of JPH04335544A publication Critical patent/JPH04335544A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enhance a quality of a semiconductor device manufactured by a simplified flip chip process in which a semiconductor chip is face down disposed on a main surface of a circuit board formed with a thick film conductive electrode through adhesive made of photo-setting insulating resin and the adhesive is then cured by irradiating with a light while applying a load to the chip. CONSTITUTION:A thick film conductive electrode of a connecting part is formed by coating with Au paste by a screen printing method, leveling it, drying it and then pressure molding it by a sawtooth-shaped pressing surface. Thereafter, a protrusion is formed by baking at a high temperature. Thus, a semiconductor device of a high quality in which defects of a semiconductor chip and an electric connection are reduced, is formed without applying an excess load.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体実装に関わり、工
法を簡略化したフリップチップ実装法により作製する高
品質な半導体装置及びその作製方法に関するものである
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor packaging, and relates to a high-quality semiconductor device manufactured by a flip-chip mounting method, which is a simplified method, and a method for manufacturing the same.

【0002】0002

【従来の技術】近年、半導体装置は電子機器の小型化、
低価格化に伴い工法を簡略化したフリップチップ実装方
式を用いて高密度実装されることが増えてきている。
[Background Art] In recent years, semiconductor devices have become more compact due to the miniaturization of electronic equipment.
With the drop in prices, high-density mounting is increasingly being carried out using the flip-chip mounting method, which is a simplified method.

【0003】以下図面を参照しながら、上記した従来の
工法を簡略化したフリップチップ実装の一例について説
明する。
An example of flip-chip mounting, which is a simplified version of the conventional method described above, will be described below with reference to the drawings.

【0004】図6は従来の工法を簡略化したフリップチ
ップ実装方式にて作製した半導体装置の斜視図で、図7
はその要部断面図を示す。また、図8に回路基板の製造
工程図を、図9にこの回路基板上の厚膜Au電極の形状
概略図を示す。図6、図7において、1は透光性を有す
るガラス材の基板で、2は通常のスクリーン印刷プロセ
スにて形成した厚膜Au電極で、3はこの厚膜Au電極
2に接続する回路導体層である。この回路導体層3は、
厚膜Au電極2に接続された厚膜下部Ag導体4、厚膜
絶縁層5、外部回路への入出力端子部へ接続された厚膜
上部Ag導体6と、この厚膜上部Ag導体6を保護する
厚膜保護層7で構成されている。8は半導体チップで、
9は半導体プロセスを用いて形成した能動素子や受動素
子の素子である。10は絶縁層、11は各素子9を電気
的に接続するAl配線である。12は保護層、13は保
護層12表面に形成されるとともにAl配線11に接続
したAl電極である。14は光硬化型絶縁樹脂よりなる
接着剤である。
FIG. 6 is a perspective view of a semiconductor device manufactured using the flip-chip mounting method, which is a simplified version of the conventional method.
shows a sectional view of its main parts. Further, FIG. 8 shows a manufacturing process diagram of the circuit board, and FIG. 9 shows a schematic diagram of the shape of the thick film Au electrode on this circuit board. In FIGS. 6 and 7, 1 is a substrate made of a transparent glass material, 2 is a thick film Au electrode formed by a normal screen printing process, and 3 is a circuit conductor connected to this thick film Au electrode 2. It is a layer. This circuit conductor layer 3 is
A thick film lower Ag conductor 4 connected to the thick film Au electrode 2, a thick film insulating layer 5, a thick film upper Ag conductor 6 connected to an input/output terminal section to an external circuit, and this thick film upper Ag conductor 6. It is composed of a thick protective layer 7 for protection. 8 is a semiconductor chip,
Reference numeral 9 indicates an active element or a passive element formed using a semiconductor process. 10 is an insulating layer, and 11 is an Al wiring that electrically connects each element 9. 12 is a protective layer; 13 is an Al electrode formed on the surface of the protective layer 12 and connected to the Al wiring 11; 14 is an adhesive made of photocurable insulating resin.

【0005】以上のように構成された半導体装置につい
て、以下その製造方法について説明する。予め、回路基
板を作製しておく。まず、図8に示すように基板1の主
面上に、スクリーン印刷法により専用Auペーストを塗
布し、これを室温で放置してレベリングを行なった後、
120〜150℃で10分程度乾燥し、次に約500℃
位の温度で焼成を行いAu厚膜電極2を形成する。同様
のプロセスを繰り返すことで、順次厚膜下部Ag導体層
4、厚膜絶縁層5、厚膜上部Ag導体層6、厚膜保護層
7を形成していき回路導体層3を構成する。最後に、ス
クライブして、個片状態にして回路基板とする。図9に
形成された厚膜Au電極2の形状概略図を示す。次に、
半導体プロセスを用いて能動素子や受動素子の素子9や
Al配線11が形成された半導体チップ8の保護層12
表面にAl電極13を形成する。次に、予め、図7、図
8に示すように基板1の主面上に、まずスクリーン印刷
法により専用Auペーストを塗布し、これを室温で放置
してレベリングを行う。その後、120〜150℃で1
0分程度乾燥し、次に約500℃位の温度で焼成を行い
Au厚膜電極2を形成する。同様のプロセスを繰り返す
ことで、順次厚膜下部Ag導体層4、厚膜絶縁層5、厚
膜上部Ag導体層6、厚膜保護層7を形成していき回路
導体層3を構成する。最後に、これらの回路導体層3形
成後にスクライブして、個片状態とした回路基板を作製
しておく。図7、図9に形成された厚膜Au電極2の形
状概略図を示す。この回路基板の主面上に、接着剤14
を必要量塗布し、その上に半導体チップ8をフェイスダ
ウンでAl電極13と厚膜Au電極2が当接するように
押し当てる。この時、厚膜Au電極2上の接着剤14は
Al電極13に押し退けられ、厚膜Au電極2とAl電
極13は電気的に接続される。その後、半導体チップ8
の素子9面の反対側より圧力を加え、厚膜Au電極2と
Al電極13を圧着し、回路基板1の裏面より光照射し
、接着剤14を硬化する。このようにして、半導体チッ
プ8を回路基板1上に実装する。この際、確実な電気的
接続とするためには、加圧する荷重は、Al電極13の
表面に自然発生的に形成される絶縁性の酸化膜を、当接
する厚膜Au電極2で物理的に破壊するのに十分なだけ
必要であった。
A method for manufacturing the semiconductor device constructed as described above will be described below. A circuit board is prepared in advance. First, as shown in FIG. 8, a special Au paste is applied on the main surface of the substrate 1 by screen printing method, and after being left at room temperature for leveling,
Dry at 120-150℃ for about 10 minutes, then dry at about 500℃
The Au thick film electrode 2 is formed by firing at a temperature of about 100 mL. By repeating the same process, a thick film lower Ag conductor layer 4, a thick film insulating layer 5, a thick film upper Ag conductor layer 6, and a thick film protection layer 7 are sequentially formed to constitute the circuit conductor layer 3. Finally, it is scribed into individual pieces and used as circuit boards. FIG. 9 shows a schematic diagram of the shape of the thick film Au electrode 2 formed. next,
A protective layer 12 of a semiconductor chip 8 on which active elements and passive elements 9 and Al wiring 11 are formed using a semiconductor process.
An Al electrode 13 is formed on the surface. Next, as shown in FIGS. 7 and 8, a special Au paste is first applied on the main surface of the substrate 1 by screen printing, and leveling is performed by leaving it at room temperature. After that, 1 at 120-150℃
After drying for about 0 minutes, baking is performed at a temperature of about 500° C. to form the Au thick film electrode 2. By repeating the same process, a thick film lower Ag conductor layer 4, a thick film insulating layer 5, a thick film upper Ag conductor layer 6, and a thick film protection layer 7 are sequentially formed to constitute the circuit conductor layer 3. Finally, after forming these circuit conductor layers 3, scribing is performed to produce individual circuit boards. 7 and 9 show schematic diagrams of the shape of the thick film Au electrode 2 formed. Adhesive 14 is applied onto the main surface of this circuit board.
The semiconductor chip 8 is pressed face down onto the semiconductor chip 8 so that the Al electrode 13 and the thick film Au electrode 2 are in contact with each other. At this time, the adhesive 14 on the thick film Au electrode 2 is pushed away by the Al electrode 13, and the thick film Au electrode 2 and the Al electrode 13 are electrically connected. After that, the semiconductor chip 8
Pressure is applied from the side opposite to the element 9 surface to press the thick film Au electrode 2 and the Al electrode 13 together, and light is irradiated from the back surface of the circuit board 1 to harden the adhesive 14. In this way, the semiconductor chip 8 is mounted on the circuit board 1. At this time, in order to ensure a reliable electrical connection, the applied load must be applied so that the insulating oxide film that is naturally formed on the surface of the Al electrode 13 is physically It took just enough to destroy it.

【0006】(特開平2−272764号公報)(Japanese Unexamined Patent Publication No. 2-272764)

【00
07】
00
07]

【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、厚膜Au電極2に蓄積された内部ストレ
スによる経時変化での電気的接続の外れの発生や、半導
体チップ8の裏面への過大な荷重による半導体チップ8
の損傷という問題点を有していた。
[Problems to be Solved by the Invention] However, with the above structure, electrical connections may become disconnected due to changes over time due to internal stress accumulated in the thick-film Au electrode 2, or excessive contact may occur on the back surface of the semiconductor chip 8. Semiconductor chip 8 due to the load
This had the problem of damage to the

【0008】これは、通常のスクリーン印刷法にて形成
した厚膜Au電極2は、図10の(A)に示すように高
さのバラツキが非常に大きいために、図10の(B)に
示すように全ての電極において電極を当接した際、最も
低い厚膜Au電極2−aの高さに合わす他の厚膜Au電
極2ーbの変形量が大きくなるため、これに起因する内
部ストレスが非常に大きいためと、この変形に要する半
導体チップ8裏面からの荷重が過大となる事による。ま
た、図9に示すように通常のスクリーン印刷法にて形成
した厚膜Au電極2は、表面が凹凸の少ない形状をして
いるため、Al電極13との接触面積は広く、酸化膜を
破壊する際にも、半導体チップ8には過大な荷重が必要
となるからである。
This is because the thick film Au electrode 2 formed by the normal screen printing method has very large variations in height as shown in FIG. 10(A). As shown in the figure, when all the electrodes are brought into contact with each other, the amount of deformation of the other thick-film Au electrode 2-b that matches the height of the lowest thick-film Au electrode 2-a increases, and the internal deformation caused by this increases. This is because the stress is extremely large and the load required from the back surface of the semiconductor chip 8 for this deformation is excessive. In addition, as shown in FIG. 9, the thick film Au electrode 2 formed by the normal screen printing method has a surface with few irregularities, so the contact area with the Al electrode 13 is wide and the oxide film is destroyed. This is because an excessive load is required on the semiconductor chip 8 when doing so.

【0009】本発明は上記問題点に鑑み、半導体チップ
及び電気的接続に関する不良を低減した、工法を簡略化
したフリップチップ実装法にて作製する高品質な半導体
装置を提供するものである。
SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a high-quality semiconductor device manufactured by a flip-chip mounting method, which is a simplified method and reduces defects related to semiconductor chips and electrical connections.

【0010】0010

【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体装置は、透光性を有するガラス材の
主面上に厚膜Au電極とこれに接続する回路導体層を形
成した回路基板と、この回路基板の主面上の所定の位置
に光硬化型絶縁樹脂よりなる接着剤を介してフェースダ
ウンにて半導体チップを配置し、半導体チップの素子面
の反対側より加圧して、所定の回路基板上の厚膜Au電
極と半導体チップの素子面に形成したAl電極を当接さ
せた状態で回路基板の裏面より紫外線を照射し接着剤を
硬化して半導体チップを固定し、且つ電気的に接続する
半導体実装方法において、この厚膜Au電極の表面に突
起物を形成した構成を備えたものである。
[Means for Solving the Problems] In order to solve the above-mentioned problems, the semiconductor device of the present invention includes a thick film Au electrode and a circuit conductor layer connected to the thick film Au electrode formed on the main surface of a transparent glass material. A semiconductor chip is placed face down on a circuit board and a predetermined position on the main surface of this circuit board via an adhesive made of photocurable insulating resin, and pressure is applied from the side opposite to the element surface of the semiconductor chip. Then, with the thick film Au electrode on the predetermined circuit board and the Al electrode formed on the element surface of the semiconductor chip in contact with each other, ultraviolet rays are irradiated from the back side of the circuit board to harden the adhesive and fix the semiconductor chip. , and a semiconductor mounting method for electrically connecting the semiconductor device, which includes a structure in which protrusions are formed on the surface of the thick film Au electrode.

【0011】[0011]

【作用】本発明は上記した構成によって、厚膜Au電極
の突起部のみが半導体チップの素子面に形成されたAl
電極に当接する。従って、接触面積は微小であるため、
酸化膜を破壊する際に要する圧力に必要な半導体チップ
への荷重は、従来より少なくてよい。更に、厚膜Au電
極間の高さを揃える際も、突起部のみを変形させるだけ
なので変形量は少なく、蓄積される内部ストレスも少な
くなり、且つ半導体チップに加圧される荷重も少なくな
る。このように、電気的接続に関与するのが厚膜Au電
極に形成した微小な突起部だけなので、半導体チップへ
の加圧荷重は従来より少なく、且つ厚膜Au電極の変形
量も少なくなるため、工法を簡略化したフリップチップ
実装にて作製した半導体装置が高品質なものとなる。
[Operation] According to the above-described structure, only the protrusions of the thick-film Au electrode are formed on the element surface of the semiconductor chip.
Contact with the electrode. Therefore, since the contact area is small,
The pressure required to destroy the oxide film requires less load on the semiconductor chip than in the past. Furthermore, when aligning the heights between the thick-film Au electrodes, only the protrusions are deformed, so the amount of deformation is small, the internal stress accumulated is also reduced, and the load applied to the semiconductor chip is also reduced. In this way, only the minute protrusions formed on the thick-film Au electrode are involved in electrical connection, so the pressure load on the semiconductor chip is less than before, and the amount of deformation of the thick-film Au electrode is also reduced. , semiconductor devices manufactured by flip-chip mounting using a simplified method can be of high quality.

【0012】0012

【実施例】以下本発明の一実施例の半導体装置について
、図面を参照しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

【0013】図1は本発明の実施例における半導体装置
の斜視図を、図2はその要部断面図が示してある。また
、図3に回路基板作製の製造工程図を、図4に回路基板
上の厚膜Au電極に突起部を形成するための、プレス機
のプレス面の形状概略を(A)に斜視図で、(B)にそ
の断面図で示す。図1、図2において、21は透光性を
有するガラス材の基板で、22は通常のスクリーン印刷
にてAuペーストを塗布し、乾燥した後、プレス加工に
て突起物を形成した厚膜Au電極であり、23は、この
突起物を形成した厚膜Au電極22に接続された回路導
体層である。この回路導体層23は、突起部を有す厚膜
Au電極22に接続された厚膜下部Ag導体24、厚膜
絶縁層25、外部回路への入出力端子部へ接続された厚
膜上部Ag導体26と、この厚膜上部Ag導体26を保
護する厚膜保護層27から構成されている。28は半導
体チップで、29は半導体プロセスを用いて能動素子や
受動素子の素子である。30は絶縁層、31は各素子2
9を電気的に接続するAl配線である。32は保護層、
33は保護層32表面に形成されるとともにAl配線3
1に接続したAl電極である。34は光硬化型絶縁樹脂
よりなる接着剤である。
FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a main part thereof. In addition, Fig. 3 shows a manufacturing process diagram for producing a circuit board, and Fig. 4 shows a schematic diagram of the shape of the pressing surface of a press machine for forming protrusions on a thick film Au electrode on a circuit board, and Fig. 4 (A) shows a perspective view. , (B) shows its cross-sectional view. In FIGS. 1 and 2, 21 is a substrate made of a transparent glass material, and 22 is a thick film of Au on which an Au paste is applied by ordinary screen printing, and after drying, protrusions are formed by pressing. 23 is a circuit conductor layer connected to the thick film Au electrode 22 on which the protrusion is formed. This circuit conductor layer 23 includes a thick film lower Ag conductor 24 connected to a thick film Au electrode 22 having a protrusion, a thick film insulating layer 25, and a thick film upper Ag conductor 24 connected to an input/output terminal portion to an external circuit. It consists of a conductor 26 and a thick film protective layer 27 that protects the thick film upper Ag conductor 26. 28 is a semiconductor chip, and 29 is an active element or a passive element using a semiconductor process. 30 is an insulating layer, 31 is each element 2
This is an Al wiring that electrically connects 9. 32 is a protective layer;
33 is formed on the surface of the protective layer 32 and the Al wiring 3
This is an Al electrode connected to 1. 34 is an adhesive made of photocurable insulating resin.

【0014】以上のように構成された半導体装置につい
て、以下、図3及び図4を用いてその製造方法を説明す
る。
A method of manufacturing the semiconductor device constructed as described above will be described below with reference to FIGS. 3 and 4.

【0015】予め回路基板を作製しておく。まず、図3
に示すようにスクリーン印刷法により専用Auペースト
を、基板の主面上に塗布し、これを室温で放置してレベ
リングを行う。その後、120〜150℃で10分程度
乾燥した後、図4に概略で示すような鋸歯状のプレス面
をもつプレス機にてプレスして、表面に複数個の突起物
を形成する。次に約500℃位の温度で焼成を行いAu
厚膜電極22を形成する。この時、形成されたAu厚膜
電極22の形状概略図を図5に示す。その後は、従来例
と同じように通常のスクリーン印刷プロセスで、順次、
厚膜下部Ag導体24、厚膜絶縁層25、厚膜上部Ag
導体26、厚膜保護層27を形成していき、回路導体層
23を形成し、最後にスクライブして個片状態とした回
路基板とする。次に、このような回路基板の主面上に、
従来例と同様にして簡易な工法の半導体フリップチップ
実装を施して半導体装置を作製する。
A circuit board is prepared in advance. First, Figure 3
As shown in Figure 2, a special Au paste is applied onto the main surface of the substrate using a screen printing method, and the paste is left at room temperature to perform leveling. After that, it is dried at 120 to 150° C. for about 10 minutes, and then pressed using a press having a serrated press surface as schematically shown in FIG. 4 to form a plurality of protrusions on the surface. Next, the Au is fired at a temperature of about 500°C.
A thick film electrode 22 is formed. A schematic diagram of the shape of the Au thick film electrode 22 formed at this time is shown in FIG. After that, in the same way as the conventional example, the normal screen printing process is used to print
Thick film lower Ag conductor 24, thick film insulating layer 25, thick film upper Ag
A conductor 26 and a thick film protective layer 27 are formed, a circuit conductor layer 23 is formed, and finally a circuit board is scribed into individual pieces. Next, on the main surface of such a circuit board,
A semiconductor device is manufactured by performing semiconductor flip-chip mounting using a simple method in the same manner as in the conventional example.

【0016】この際、厚膜Au電極22上の微小な突起
部しか、Al電極33に当接して電気的接続に関与しな
い。また、高精度なプレス機にてプレスすることにより
、高さのバラツキも十分小さくすることができる。従っ
て、厚膜Au電極22の変形量は小さくなり、半導体チ
ップ28への荷重も十分小さくなる。このような理由か
ら、荷重により半導体チップ28を損なうことや、厚膜
Au電極22の変形に起因する内部ストレスによる電気
的接続の外れの発生もなくなる。
At this time, only the minute protrusions on the thick film Au electrode 22 come into contact with the Al electrode 33 and participate in electrical connection. In addition, by pressing with a high-precision press machine, variations in height can be made sufficiently small. Therefore, the amount of deformation of the thick film Au electrode 22 becomes small, and the load on the semiconductor chip 28 becomes sufficiently small. For these reasons, damage to the semiconductor chip 28 due to load and disconnection of electrical connections due to internal stress caused by deformation of the thick film Au electrode 22 are avoided.

【0017】以上のように本実施例によれば、簡易なフ
リップチップ実装工法にて作製する半導体装置において
、回路基板の主面上への通常のスクリーン印刷法による
厚膜Au電極形成プロセス中のAuペースト乾燥という
工程後に、鋸歯状のプレス機にてプレス加工して突起物
を形成するという簡単な工程を加えるだけで、上記した
理由により、半導体チップや電気的な接続の不良の少な
い高品質な半導体装置とすることができる。
As described above, according to this embodiment, in a semiconductor device manufactured by a simple flip-chip mounting method, during the process of forming thick film Au electrodes on the main surface of a circuit board by a normal screen printing method, After the process of drying the Au paste, a simple process of pressing with a serrated press to form protrusions is added, and for the reasons mentioned above, high quality semiconductor chips and electrical connections with few defects can be achieved. A semiconductor device can be obtained.

【0018】[0018]

【発明の効果】以上のように本発明は 、透光性を有す
るガラス基材の主面上に突起部を有した導電性電極とこ
れに接続する回路導体層を形成した回路基板と、この回
路基板の主面上の所定の位置に光硬化型絶縁樹脂よりな
る接着剤を介してフェースダウンにて半導体チップを配
置し、半導体チップの素子面の反対側より加圧して、所
定の回路基板上の厚膜導電性電極と半導体チップの素子
面に形成した電極を当接させた状態で回路基板の裏面よ
り紫外線を照射し光硬化型絶縁樹脂よりなる接着剤を硬
化して半導体チップを固定し、且つ電気的に接続した半
導体装置において、前記厚膜導電性電極上に導電性を有
する突起物を形成することにより、半導体チップの損傷
や電気的接続の不良を低減した高品質な半導体装置とす
ることができる。
Effects of the Invention As described above, the present invention provides a circuit board in which a conductive electrode having a protrusion and a circuit conductor layer connected thereto are formed on the main surface of a glass base material having a light-transmitting property; A semiconductor chip is placed face down at a predetermined position on the main surface of the circuit board via an adhesive made of photocurable insulating resin, and pressure is applied from the side opposite to the element surface of the semiconductor chip to secure the predetermined circuit board. With the upper thick-film conductive electrode and the electrode formed on the element surface of the semiconductor chip in contact with each other, ultraviolet rays are irradiated from the back side of the circuit board to harden the adhesive made of photocurable insulating resin and fix the semiconductor chip. A high-quality semiconductor device in which damage to the semiconductor chip and defects in electrical connection are reduced by forming conductive protrusions on the thick film conductive electrode in the electrically connected semiconductor device. It can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の実施例における半導体装置の斜視図で
ある。
FIG. 1 is a perspective view of a semiconductor device in an embodiment of the present invention.

【図2】同実施例における半導体装置の要部断面図であ
る。
FIG. 2 is a sectional view of a main part of the semiconductor device in the same embodiment.

【図3】同実施例における半導体装置の回路基板の製造
工程図である。
FIG. 3 is a manufacturing process diagram of a circuit board of a semiconductor device in the same embodiment.

【図4】同実施例における半導体装置の回路基板のAu
厚膜電極形成のためのプレス機のプレス面の形状概略図
である。
[Fig. 4] Au of the circuit board of the semiconductor device in the same example
FIG. 2 is a schematic diagram of the shape of a press surface of a press machine for forming a thick film electrode.

【図5】同実施例における半導体装置の回路基板のAu
厚膜電極の形状概略図である。
[Fig. 5] Au of the circuit board of the semiconductor device in the same example.
FIG. 3 is a schematic diagram of the shape of a thick film electrode.

【図6】従来の半導体装置の斜視図である。FIG. 6 is a perspective view of a conventional semiconductor device.

【図7】従来の半導体装置要部断面図である。FIG. 7 is a sectional view of a main part of a conventional semiconductor device.

【図8】従来の半導体装置の回路基板の製造工程図であ
る。
FIG. 8 is a manufacturing process diagram of a circuit board of a conventional semiconductor device.

【図9】従来の半導体装置の回路基板の厚膜Au電極形
状概略図である。
FIG. 9 is a schematic diagram of the shape of a thick-film Au electrode on a circuit board of a conventional semiconductor device.

【図10】従来の半導体装置の不良発生要因説明図であ
る。
FIG. 10 is an explanatory diagram of factors causing defects in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1、21  透光性を有するガラス材の基板2  厚膜
Au電極 3、23  回路導体層 4、24  厚膜下部Ag導体 5、25  厚膜絶縁層 6、26  厚膜上部Ag導体 7、27  厚膜保護層 8、28  半導体チップ 9、29  素子 10、30  絶縁層 11、31  Al配線 12、32  保護層 13、33  Al電極
1, 21 Translucent glass substrate 2 Thick film Au electrode 3, 23 Circuit conductor layer 4, 24 Thick film lower Ag conductor 5, 25 Thick film insulating layer 6, 26 Thick film upper Ag conductor 7, 27 Thickness Film protective layer 8, 28 Semiconductor chip 9, 29 Element 10, 30 Insulating layer 11, 31 Al wiring 12, 32 Protective layer 13, 33 Al electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  透光性を有するガラス基材の主面上に
厚膜導電性電極とこれに接続する回路導体層を形成した
回路基板と、この回路基板の主面上の所定の位置に光硬
化型絶縁樹脂よりなる接着剤を介してフェースダウンに
て半導体チップを配置し、半導体チップの素子面の反対
側より加圧して、所定の回路基板上の厚膜導電性電極と
半導体チップの素子面に形成した電極を当接させた状態
で回路基板の裏面より紫外線を照射し光硬化型絶縁樹脂
よりなる接着剤を硬化して半導体チップを固定し、且つ
電気的に接続するフリップチップ実装工法による半導体
装置において、前記厚膜導電性電極上に導電性を有する
突起物を形成したことを特徴とする半導体装置。
Claim 1: A circuit board in which a thick-film conductive electrode and a circuit conductor layer connected thereto are formed on the main surface of a glass substrate having light-transmitting properties; A semiconductor chip is placed face down via an adhesive made of photocurable insulating resin, and pressure is applied from the side opposite to the element surface of the semiconductor chip to connect the thick film conductive electrode on a predetermined circuit board and the semiconductor chip. Flip chip mounting, in which the semiconductor chip is fixed and electrically connected by irradiating ultraviolet rays from the back side of the circuit board with the electrodes formed on the element surface in contact with each other to harden the adhesive made of photocurable insulating resin. 1. A semiconductor device manufactured by a construction method, characterized in that a conductive protrusion is formed on the thick film conductive electrode.
【請求項2】  厚膜導電性電極はAuとしたことを特
徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the thick film conductive electrode is made of Au.
【請求項3】  厚膜Au電極は、スクリーン印刷法に
てAuペーストを塗布し、レベリング、乾燥した後、プ
レス面が鋸歯状のもので圧力成形する。然る後、高温中
で焼成して形成したことを特徴とする請求項1記載の半
導体装置。
3. The thick-film Au electrode is made by applying an Au paste by screen printing, leveling and drying, and then pressure-forming with a press having a serrated surface. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by subsequently firing at a high temperature.
JP10546591A 1991-05-10 1991-05-10 Semiconductor device and manufacture thereof Pending JPH04335544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10546591A JPH04335544A (en) 1991-05-10 1991-05-10 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10546591A JPH04335544A (en) 1991-05-10 1991-05-10 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04335544A true JPH04335544A (en) 1992-11-24

Family

ID=14408330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10546591A Pending JPH04335544A (en) 1991-05-10 1991-05-10 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04335544A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014184439A (en) * 2013-03-21 2014-10-02 Shindengen Electric Mfg Co Ltd Joining method of aluminum member and manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014184439A (en) * 2013-03-21 2014-10-02 Shindengen Electric Mfg Co Ltd Joining method of aluminum member and manufacturing method of semiconductor device

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