JPH05136208A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JPH05136208A
JPH05136208A JP29413291A JP29413291A JPH05136208A JP H05136208 A JPH05136208 A JP H05136208A JP 29413291 A JP29413291 A JP 29413291A JP 29413291 A JP29413291 A JP 29413291A JP H05136208 A JPH05136208 A JP H05136208A
Authority
JP
Japan
Prior art keywords
thick film
electrode
circuit board
semiconductor
conductive electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29413291A
Other languages
Japanese (ja)
Inventor
Tsukasa Shiraishi
司 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP29413291A priority Critical patent/JPH05136208A/en
Publication of JPH05136208A publication Critical patent/JPH05136208A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

PURPOSE:To enhance the quality of a semiconductor device manufactured in a mounting method wherein, after a semiconductor image sensor chip is arranged through ultraviolet-ray curing insulating resin at a specific location on a translucent circuit board on which a thick film conductive electrode is formed, the resin is irradiated with ultraviolet rays to secure the chip, and electrical conduction is effected. CONSTITUTION:A thick film conductive electrode 22 of a connection is so constructed that, after Au paste is applied by a screen printing method, leveled, dried and sintered, a polished surface on an upper part of this film is formed. Also, a polished surface 23 is formed on an upper part of the thick film Au electrode 22 film, whereby such a film can be realized that a cross-sectional shape is trapezoid and that the film thickness is uniform. The allowable range of misalignment in mounting is mounting is widened, and also the deformation amount of the thick film Au electrode or the load amount on a semiconductor chip can be reduced and a semiconductor device with high quality can be made in which fails of electrical connection or damages on a semiconductor image sensor chip 30 are reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体実装に関するもの
で、光学画像を電気信号に変換するイメージセンサなど
の半導体装置及びその製造装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor mounting, and more particularly to a semiconductor device such as an image sensor for converting an optical image into an electric signal and a manufacturing apparatus thereof.

【0002】[0002]

【従来の技術】近年、高密度の多端子、狭ピッチの半導
体の実装を目的として、光あるいは熱硬化型の絶縁樹脂
により導体配線を有する回路基板の電極と半導体素子上
のバンプ電極とを接触させ固定する実装方法が特開平2
−44742号公報などにより提案されている。また最
近では、半導体素子のバンプ電極をAuなどのメッキに
より形成するため高価であることからバンプを用いない
実装方法も提案されている。
2. Description of the Related Art In recent years, for the purpose of mounting a high-density multi-terminal, narrow-pitch semiconductor, an electrode of a circuit board having a conductor wiring is contacted with a bump electrode on a semiconductor element by a light or thermosetting insulating resin. Mounting method for fixing by fixing
No. 44742, for example. In addition, recently, since the bump electrodes of the semiconductor element are formed by plating with Au or the like, it is expensive, and therefore a mounting method without using bumps has been proposed.

【0003】以下図面を参照しながら、上記した従来の
バンプを用いない構造の半導体装置の一例について説明
する。
An example of the conventional semiconductor device having no bump will be described below with reference to the drawings.

【0004】図4は従来の実装方式にて作製したイメー
ジセンサの斜視図で、図5はその要部断面図を示す。ま
た、図6に透光性回路基板の製造工程図を示す。図4、
図5において、1は透光性を有するガラス基板で、2は
通常のスクリーン印刷プロセスにて形成した厚膜Au電
極で、3はこの厚膜Au電極2に接続する回路導体層で
ある。この回路導体層3は、厚膜Au電極2に接続され
た厚膜下部Ag導体4、厚膜絶縁層5、外部回路への入
出力端子部へ接続された厚膜上部Ag導体6と、この厚
膜上部Ag導体6を保護する厚膜保護層7で構成されて
いる。8は半導体イメージセンサチップで、半導体イメ
ージセンサチップ8は半導体プロセスを用いて形成した
能動素子や受動素子の素子9、絶縁層10、各素子9を
電気的に接続するAl配線11及び保護層12、保護層
12表面に形成されるとともにAl配線11に接続した
Al電極13より成り立っている。14は半導体イメー
ジセンサチップ8を固定し、電気的導通をとるための紫
外線硬化型絶縁樹脂である。
FIG. 4 is a perspective view of an image sensor manufactured by a conventional mounting method, and FIG. 5 is a sectional view of the main part thereof. Further, FIG. 6 shows a manufacturing process diagram of the translucent circuit board. Figure 4,
In FIG. 5, 1 is a glass substrate having translucency, 2 is a thick film Au electrode formed by a normal screen printing process, and 3 is a circuit conductor layer connected to this thick film Au electrode 2. The circuit conductor layer 3 includes a thick film lower Ag conductor 4 connected to the thick film Au electrode 2, a thick film insulating layer 5, a thick film upper Ag conductor 6 connected to an input / output terminal portion to an external circuit, and The thick film protective layer 7 is configured to protect the thick film upper Ag conductor 6. Reference numeral 8 denotes a semiconductor image sensor chip. The semiconductor image sensor chip 8 is an element 9 of an active element or a passive element formed by using a semiconductor process, an insulating layer 10, an Al wiring 11 and a protective layer 12 electrically connecting each element 9. , An Al electrode 13 formed on the surface of the protective layer 12 and connected to the Al wiring 11. Reference numeral 14 is an ultraviolet curable insulating resin for fixing the semiconductor image sensor chip 8 and establishing electrical conduction.

【0005】以上のように構成されたイメージセンサに
ついて、以下その製造方法について説明する。まず、半
導体プロセスを用いて能動素子や受動素子の素子9やA
l配線11が形成された半導体チップ8の保護層12表
面にAl電極13を形成する。次に、予め回路基板を図
6に示すように透光性のガラス基板1上に、スクリーン
印刷法によりAuペーストを塗布し、これを室温で放置
してレベリングを行なう。その後、120〜150℃で
10分程度乾燥し、次に約500℃位の温度で焼成を行
いAu厚膜電極2を形成する。同様のプロセスを繰り返
すことで、順次厚膜下部Ag導体層4、厚膜絶縁層5、
厚膜上部Ag導体層6、厚膜保護層7を形成していき回
路導体層3を構成する。最後に、スクライブして、個片
状態とした透光性回路基板を作製しておく。そして、こ
の作製した透光性回路基板上に透光性紫外線硬化型絶縁
樹脂14を必要量塗布し、その上に半導体イメージセン
サチップ8をAl電極13と厚膜Au電極2が当接する
ように押し当てる。この時、厚膜Au電極2上の樹脂1
4は押し退けられ、厚膜Au電極2とAl電極13は電
気的に接続される。その後、半導体イメージセンサチッ
プ8の素子9面の反対側より圧力を加え、厚膜Au電極
2とAl電極13を圧着し、透光性回路基板の裏面より
紫外線を照射して紫外線硬化型樹脂14の硬化を行な
う。このようにして、半導体イメージセンサ8を透光性
回路基板上に実装する。この際、確実な電気的接続とす
るために加圧する荷重は、Al電極13の自然発生的に
形成される絶縁性の酸化膜を、当接する厚膜Au電極2
で物理的に破壊するのに十分なだけ必要である。(例え
ば特開平2−272764号公報など)
A method of manufacturing the image sensor having the above structure will be described below. First, by using a semiconductor process, the active element or passive element 9 or A
An Al electrode 13 is formed on the surface of the protective layer 12 of the semiconductor chip 8 on which the l wiring 11 is formed. Next, as shown in FIG. 6, the circuit board is previously coated with the Au paste by the screen printing method on the translucent glass substrate 1 and left at room temperature for leveling. Then, it is dried at 120 to 150 ° C. for about 10 minutes and then baked at a temperature of about 500 ° C. to form the Au thick film electrode 2. By repeating the same process, the thick film lower Ag conductor layer 4, the thick film insulating layer 5,
The thick film upper Ag conductor layer 6 and the thick film protective layer 7 are formed to form the circuit conductor layer 3. Finally, scribing is performed to prepare a translucent circuit board in an individual state. Then, a required amount of the translucent ultraviolet curable insulating resin 14 is applied onto the produced translucent circuit board, and the semiconductor image sensor chip 8 is contacted with the Al electrode 13 and the thick film Au electrode 2 thereon. Press against. At this time, the resin 1 on the thick film Au electrode 2
4 is pushed away, and the thick film Au electrode 2 and the Al electrode 13 are electrically connected. Thereafter, pressure is applied from the side opposite to the element 9 surface of the semiconductor image sensor chip 8, the thick film Au electrode 2 and the Al electrode 13 are pressure-bonded, and ultraviolet rays are radiated from the rear surface of the transparent circuit board to cure the ultraviolet curable resin 14. Cure. In this way, the semiconductor image sensor 8 is mounted on the translucent circuit board. At this time, the load applied to ensure a reliable electrical connection is such that the thick Au electrode 2 that abuts the spontaneously formed insulating oxide film of the Al electrode 13.
Just enough to physically destroy at. (For example, Japanese Patent Laid-Open No. 2-272764)

【0006】[0006]

【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、厚膜Au電極2に蓄積された内部ストレ
スによる経時変化での電気的接続の外れの発生や、半導
体イメージセンサチップ8の裏面への過大な荷重による
半導体イメージセンサチップ8の損傷という問題点を有
していた。
However, in the above structure, the internal stress accumulated in the thick-film Au electrode 2 causes a disconnection of the electrical connection due to a change with time, and the back surface of the semiconductor image sensor chip 8 is exposed. However, there is a problem that the semiconductor image sensor chip 8 is damaged due to the excessive load.

【0007】この理由は、通常のスクリーン印刷法にて
形成した厚膜Au電極2は、半導体イメージセンサチッ
プ8側のAl電極13に比べて図7の(A)に示すよう
に高さのバラツキが非常に大きいために、図7の(B)
に示すように全ての電極において電極を当接した際、電
極間の距離が最も低い厚膜Au電極2−aの距離になる
まで、主に、他の厚膜Au電極2−bを変形させる必要
があるが、この時のAu電極2ーbの変形量に依存して
内部ストレスが非常に大きくなることと、この変形に要
する半導体イメージセンサチップ8裏面からの荷重が過
大となることによる。従って、厚膜Au電極2間の膜厚
のバラツキを抑え均一なものとすることで、不良発生を
防止できる。また、スクリーン印刷法にて形成された厚
膜Au電極2の断面形状は、放物状でピークとなる位置
のバラツキが大きいので、全ての電極が当接できる位置
範囲も狭く、電気的接続不良発生の原因となった。
The reason for this is that the thick film Au electrode 2 formed by the usual screen printing method has a variation in height as shown in FIG. 7A as compared with the Al electrode 13 on the semiconductor image sensor chip 8 side. 7B is so large that (B) of FIG.
When the electrodes are brought into contact with all of the electrodes as shown in FIG. 6, the other thick film Au electrodes 2-b are mainly deformed until the distance between the electrodes reaches the distance of the thick film Au electrode 2-a. This is necessary because the internal stress becomes extremely large depending on the amount of deformation of the Au electrode 2-b at this time, and the load from the back surface of the semiconductor image sensor chip 8 required for this deformation becomes excessive. Therefore, the occurrence of defects can be prevented by suppressing the variation in the film thickness between the thick film Au electrodes 2 and making the film uniform. In addition, since the cross-sectional shape of the thick film Au electrode 2 formed by the screen printing method is parabolic and has a large variation in the peak position, the position range in which all the electrodes can come into contact is narrow, resulting in poor electrical connection. It caused the occurrence.

【0008】本発明は上記問題点に鑑み、半導体チップ
及び電気的接続に関する不良を低減した、工法を簡略化
したフリップチップ実装法にて作製する高品質な半導体
装置装置及びその製造方法を提供するものである。
In view of the above problems, the present invention provides a high-quality semiconductor device device manufactured by a flip-chip mounting method that reduces defects relating to a semiconductor chip and electrical connection and that simplifies the manufacturing method, and a manufacturing method thereof. It is a thing.

【0009】[0009]

【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体装置は、上面に回路導体層とこの回
路導体層に接続する厚膜導電性電極を有する透光性回路
基板と、この透光性回路基板の上面に光硬化型絶縁樹脂
を介して半導体素子を有し、半導体素子の素子面の反対
側より加圧して、透光性回路基板の所定の位置の厚膜導
電性電極と半導体素子の素子面に形成した電極を当接さ
せた状態で紫外線を照射して光硬化型絶縁樹脂を硬化し
て半導体素子を固定し、かつ電気的に接続する半導体装
置において、厚膜導電性電極は、スクリーン印刷法にて
導電性ペーストを塗布した後、レベリング、乾燥、焼成
を行ってから、導電性膜の上部のを研磨を施し研磨面を
形成した構成を備えたものである。
In order to solve the above-mentioned problems, a semiconductor device of the present invention comprises a translucent circuit board having a circuit conductor layer and a thick film conductive electrode connected to the circuit conductor layer on the upper surface. , A semiconductor element is provided on the upper surface of the transparent circuit board through a photo-curable insulating resin, and pressure is applied from the side opposite to the element surface of the semiconductor element to apply thick film conductivity at a predetermined position of the transparent circuit board. In the semiconductor device in which the semiconductor element is fixed and electrically connected by irradiating ultraviolet rays to cure the photo-curable insulating resin with the conductive electrode and the electrode formed on the element surface of the semiconductor element in contact with each other, The membrane conductive electrode has a configuration in which a conductive paste is applied by a screen printing method, then leveling, drying, and firing are performed, and then the upper portion of the conductive film is polished to form a polished surface. is there.

【0010】[0010]

【作用】本発明は上記した構成によって、厚膜導電性電
極の膜厚を均一なものとすることができ、電極の当接・
圧着の際の厚膜導電性電極の変形量及び半導体素子への
荷重は小さくなる。従って、蓄積される内部ストレスも
少なくなり、且つ半導体イメージセンサチップに加圧さ
れる荷重も少なくなる。また、厚膜導電性電極の断面形
状が台形状となるので、当接・圧着の際の位置ずれに対
する許容範囲も大きくなる。このため、厚膜導電性電極
に蓄積された内部ストレスに起因する経時変化による電
気的接続の外れの発生や位置ずれによる電気的接続の不
良、及び半導体素子の裏面への過大な荷重による半導体
素子の損傷という従来の問題点を解決できるものであ
る。
According to the present invention, the thickness of the thick-film conductive electrode can be made uniform by the above-mentioned constitution, and the contact of the electrode
The amount of deformation of the thick-film conductive electrode and the load on the semiconductor element during pressure bonding are small. Therefore, the accumulated internal stress is reduced and the load applied to the semiconductor image sensor chip is reduced. Further, since the thick-film conductive electrode has a trapezoidal cross-sectional shape, the allowable range for positional displacement at the time of contact / pressure bonding becomes large. For this reason, the occurrence of disconnection of the electrical connection due to a change with time due to the internal stress accumulated in the thick film conductive electrode, the defective electrical connection due to the position shift, and the excessive load on the back surface of the semiconductor element cause the semiconductor element It is possible to solve the conventional problem of damage of the.

【0011】[0011]

【実施例】以下本発明の一実施例の半導体装置及びその
製造方法について、図面を参照しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to one embodiment of the present invention will be described below with reference to the drawings.

【0012】図1は本発明の実施例におけるイメージセ
ンサの斜視図を、図2はその要部断面図が示してある。
また、図3に作製の際使用する研磨装置の概略図を示す
ものである。説明に於て、従来と同一工程については図
6も参照にして説明する。図1、図2、図3において、
21は透光性を有するガラス基板で、22は通常のスク
リーン印刷にてAuペーストを塗布し、乾燥、焼成して
形成したAu電極であり、23はこの焼成した厚膜Au
電極の膜上部を研磨した研磨面で、24は、厚膜Au電
極22に接続された回路導体層である。この回路導体層
24は、厚膜Au電極22に接続された厚膜下部Ag導
体25、厚膜絶縁層26、外部回路への入出力端子部へ
接続された厚膜上部Ag導体27と、この厚膜上部Ag
導体27を保護する厚膜保護層28から構成されてい
る。また、29はAu電極22及び回路導体層23を形
成してない帯状基準領域である。30は半導体イメージ
センサチップで、31は半導体プロセスを用いて形成さ
れた能動素子や受動素子の素子である。32は絶縁層、
33は各素子31を電気的に接続するAl配線である。
34は保護層、35は保護層34表面に形成されるとと
もにAl配線33に接続したAl電極である。36は透
光性を有す紫外線硬化型絶縁樹脂である。つぎに図3に
おいて研磨装置の、37は剛性を有するフレーム、38
は前記帯状領域29のみを当接して走行する位置でフレ
ーム37に取り付けた1対の同形の上部ローラ、39は
フレーム37に設置したAu電極22研磨用の回転グラ
インダで、40はガラス基板21を搬送するためのロー
ダ用ローラーである。41はフレーム37とローダ用ロ
ーラ39を接続するバネである。
FIG. 1 is a perspective view of an image sensor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a main part thereof.
Further, FIG. 3 shows a schematic view of a polishing apparatus used in the production. In the description, the same process as the conventional process will be described with reference to FIG. In FIG. 1, FIG. 2 and FIG.
Reference numeral 21 is a light-transmissive glass substrate, 22 is an Au electrode formed by applying an Au paste by ordinary screen printing, drying and firing, and 23 is this fired thick film Au.
Reference numeral 24 is a polished surface obtained by polishing the upper part of the electrode film, and 24 is a circuit conductor layer connected to the thick film Au electrode 22. The circuit conductor layer 24 includes a thick film lower Ag conductor 25 connected to the thick film Au electrode 22, a thick film insulating layer 26, and a thick film upper Ag conductor 27 connected to an input / output terminal portion to an external circuit. Thick film upper Ag
It is composed of a thick film protective layer 28 that protects the conductor 27. Reference numeral 29 is a strip-shaped reference region in which the Au electrode 22 and the circuit conductor layer 23 are not formed. Reference numeral 30 is a semiconductor image sensor chip, and 31 is an element such as an active element or a passive element formed by a semiconductor process. 32 is an insulating layer,
Reference numeral 33 is an Al wiring that electrically connects each element 31.
Reference numeral 34 is a protective layer, and 35 is an Al electrode formed on the surface of the protective layer 34 and connected to the Al wiring 33. Reference numeral 36 is a translucent ultraviolet curable insulating resin. Next, in FIG. 3, in the polishing apparatus, 37 is a frame having rigidity, and 38 is a frame.
Is a pair of upper rollers of the same shape attached to the frame 37 at a position where only the strip-shaped region 29 is in contact and running, 39 is a rotary grinder for polishing the Au electrode 22 installed on the frame 37, and 40 is the glass substrate 21. It is a loader roller for carrying. Reference numeral 41 is a spring that connects the frame 37 and the loader roller 39.

【0013】以上のように構成されたイメージセンサに
ついて、その製造方法を説明する。まず、半導体プロセ
スを用いて単結晶シリコン基板(ウエハ)上に、フォト
トランジスタまたはフォトダイオードなどの受光素子、
CCDやMOS、バイポーラICなどのアクセス回路な
どの素子31を設けたものを製造する。Al配線33、
保護層34、Al電極35は2層Al配線プロセスを用
い、Al電極35は、スパッタリング法により1μm程
度の膜厚を形成する。その後、このウエハを高精度ダイ
シング技術により切断し、半導体イメージセンサチップ
30を製造する。また、予め回路基板を作製しておく。
従来と同じようにスクリーン印刷法により、まず、Au
ペーストを、ガラス基板21の主面上に塗布し、これを
室温で放置してレベリングを行う。その後、120〜1
50℃で10分程度乾燥した後、約500℃の温度で焼
成を行いAu厚膜電極22を形成した後、順次、同様に
して厚膜下部Ag導体25、厚膜絶縁層26、厚膜上部
Ag導体27、厚膜保護層28を形成していき、回路導
体層24を形成する。但し、この際ガラス基板21上に
は、Au電極22や回路導体層23を形成しない帯状基
準領域29を2箇所以上設置した構成としておく。最後
にスクライブして個片状態とする。然る後、図3に示す
研磨装置にてAu厚膜電極22の上部を回転グラインダ
39を回転させて研磨して研磨面23を形成し、膜厚の
均一化と断面形状を台形状とすることを行う。この研磨
装置は、ガラス基板21上の帯状基準領域29に当接し
て走行している一対の上部ローラ38が、基準領域29
の凹凸に追従して上下するので、この上部ローラ39に
フレーム36を介して設置されている回転グラインダ3
9は連動して上下し、回転グラインダ39とガラス基板
21上部表面との距離は常に一定となる。また、ガラス
基板21の裏面に接しながら回転することでガラス基板
21を搬送するローダ用ローラを通してバネ41によ
り、上部ローラ38がガラス基板21上面に当接する際
の圧力は、適当且つ一定になるようになっている。従っ
て、高精度な膜厚の均一化が実現できる。更に、回転グ
ラインダ39はフレーム37に対し上下左右に可変な機
構とすることで、例えば回転グラインダ39の消耗時の
微調整が可能となるなどして、装置の耐久性、信頼性の
向上が確保できる。次に、従来例と同様にして簡易な実
装方法により透光性回路基板上の所定の位置に、アクリ
レート系の透光性紫外線硬化型絶縁樹脂36をスタンピ
ング法やスクリーン印刷法などにより所定量塗布する。
その上に半導体イメージセンサチップ30をAl電極3
5と厚膜Au電極22の研磨面23が当接するように押
し当てる。その後、半導体イメージセンサチップ30の
素子31面の反対側より圧力を加え、厚膜Au電極22
とAl電極35を圧着し、ガラス基板21の裏面より紫
外線を照射して紫外線硬化型樹脂36の硬化を行う。こ
の際、厚膜Au電極22の膜厚は非常に均一であるの
で、厚膜Au電極22の変形量は小さくなり、半導体イ
メージセンサチップ30への荷重も十分小さくなる。ま
た、断面形状が台形状であるので当接の際の位置ずれに
対する許容範囲が大きく、位置ずれによる電気的接続の
不良が低減する。このようにして、半導体イメージセン
サチップ30を透光性回路基板上に実装する。
A method of manufacturing the image sensor having the above structure will be described. First, a light receiving element such as a phototransistor or a photodiode is formed on a single crystal silicon substrate (wafer) using a semiconductor process,
A device provided with an element 31 such as an access circuit such as a CCD, a MOS, or a bipolar IC is manufactured. Al wiring 33,
A two-layer Al wiring process is used for the protective layer 34 and the Al electrode 35, and the Al electrode 35 is formed to have a film thickness of about 1 μm by a sputtering method. Thereafter, this wafer is cut by a high precision dicing technique to manufacture the semiconductor image sensor chip 30. In addition, a circuit board is prepared in advance.
By the screen printing method as before, first, Au
The paste is applied on the main surface of the glass substrate 21 and left at room temperature for leveling. Then 120-1
After drying at 50 ° C. for about 10 minutes and firing at a temperature of about 500 ° C. to form the Au thick film electrode 22, the thick film lower Ag conductor 25, the thick film insulating layer 26, and the thick film upper part are sequentially formed in the same manner. The Ag conductor 27 and the thick film protective layer 28 are formed to form the circuit conductor layer 24. However, at this time, two or more strip-shaped reference regions 29 where the Au electrode 22 and the circuit conductor layer 23 are not formed are provided on the glass substrate 21. Finally, scribe to individual state. After that, the upper part of the Au thick film electrode 22 is polished by rotating the rotary grinder 39 by the polishing apparatus shown in FIG. 3 to form the polishing surface 23, and the film thickness is made uniform and the cross-sectional shape is trapezoidal. Do things. In this polishing apparatus, a pair of upper rollers 38, which are in contact with the strip-shaped reference area 29 on the glass substrate 21 and are running, make the reference area 29
Since it moves up and down following the irregularities of the rotary grinder 3 installed on the upper roller 39 through the frame 36.
9 moves up and down in conjunction with each other, and the distance between the rotary grinder 39 and the upper surface of the glass substrate 21 is always constant. In addition, the pressure when the upper roller 38 contacts the upper surface of the glass substrate 21 by the spring 41 through the loader roller that conveys the glass substrate 21 by rotating while contacting with the back surface of the glass substrate 21 becomes appropriate and constant. It has become. Therefore, highly accurate uniformization of the film thickness can be realized. Further, the rotary grinder 39 has a mechanism which can be vertically and horizontally variable with respect to the frame 37, so that the rotary grinder 39 can be finely adjusted when it is worn out, thereby ensuring the durability and reliability of the apparatus. it can. Next, similar to the conventional example, an acrylate-based translucent UV-curable insulating resin 36 is applied to a predetermined position on the translucent circuit board by a simple mounting method by a predetermined amount by a stamping method or a screen printing method. To do.
On top of that, the semiconductor image sensor chip 30 and the Al electrode 3
5 and the polishing surface 23 of the thick film Au electrode 22 are pressed against each other. After that, pressure is applied from the side opposite to the surface of the element 31 of the semiconductor image sensor chip 30, and the thick film Au electrode 22
The Al electrode 35 is pressure-bonded, and ultraviolet rays are irradiated from the back surface of the glass substrate 21 to cure the ultraviolet curable resin 36. At this time, since the film thickness of the thick film Au electrode 22 is very uniform, the deformation amount of the thick film Au electrode 22 becomes small, and the load on the semiconductor image sensor chip 30 becomes sufficiently small. In addition, since the cross-sectional shape is trapezoidal, the allowable range for the positional displacement at the time of contact is large, and the defective electrical connection due to the positional displacement is reduced. In this way, the semiconductor image sensor chip 30 is mounted on the translucent circuit board.

【0014】上記のようにして、イメージセンサを製造
する。このイメージセンサについては、ガラス基板21
及び透光性紫外線硬化型樹脂36を通して光情報を半導
体イメージセンサチップ30に形成した素子31の中の
受光素子が検知し、これが電気信号に変換するようにな
っている。
The image sensor is manufactured as described above. For this image sensor, the glass substrate 21
Also, the light receiving element in the element 31 formed on the semiconductor image sensor chip 30 detects the optical information through the transparent ultraviolet curable resin 36 and converts it into an electric signal.

【0015】以上のように本実施例によれば、簡易な実
装方法にて製造することができる半導体装置において、
透光性回路基板上への通常のスクリーン印刷法による厚
膜Au電極形成を行った後、この厚膜Au電極膜の上部
に研磨を施し研磨面を形成することにより、断面形状が
台形状で膜厚が均一な膜となり、上記した理由により、
半導体素子や電気的な接続の不良の少ない高品質な半導
体装置とすることができる。
As described above, according to this embodiment, in the semiconductor device which can be manufactured by a simple mounting method,
After the thick film Au electrode is formed on the translucent circuit board by the usual screen printing method, the thick film Au electrode film is polished on its upper surface to form a polished surface, so that the cross-sectional shape is trapezoidal. The film has a uniform thickness, and for the above reasons,
It is possible to provide a high-quality semiconductor device with few defects in semiconductor elements and electrical connections.

【0016】[0016]

【発明の効果】以上のように本発明の半導体装置は、上
面に回路導体層とこの回路導体層に接続する厚膜導電性
電極を有する透光性回路基板とこの透光性回路基板の上
面の所定の位置に光硬化型絶縁樹脂を介して半導体素子
を配置し、半導体素子の素子面の反対側より加圧して、
前記半導体素子の素子面に形成した電極を当接させた状
態で紫外線を照射して光硬化型絶縁樹脂を硬化して半導
体素子を固定し、かつ電気的に接続する半導体装置にお
いて、この厚膜導電性電極は、スクリーン印刷法にて導
電性ペーストを塗布した後、レベリング、乾燥、焼成を
行なってから、膜の上部に研磨を施し研磨面を形成した
ことにより、断面形状が台形状となることと、高精度な
膜厚の均一化が実現できるので、簡易な工法による半導
体チップの損傷や電気的接続の不良を低減した高品質な
半導体装置とすることができる。
As described above, in the semiconductor device of the present invention, the transparent circuit board having the circuit conductor layer and the thick film conductive electrode connected to the circuit conductor layer on the upper surface, and the upper surface of the transparent circuit board. A semiconductor element is arranged at a predetermined position through a photo-curable insulating resin, and pressure is applied from the opposite side of the element surface of the semiconductor element,
In the semiconductor device in which the semiconductor element for fixing and electrically connecting the semiconductor element by irradiating ultraviolet rays to cure the photo-curable insulating resin in a state where the electrode formed on the element surface of the semiconductor element is in contact with the thick film, The conductive electrode is applied with a conductive paste by a screen printing method, then leveled, dried and baked, and then the upper surface of the film is polished to form a polished surface, so that the cross-sectional shape becomes trapezoidal. In addition, since the film thickness can be made uniform with high accuracy, it is possible to obtain a high-quality semiconductor device in which damage to the semiconductor chip and defective electrical connection are reduced by a simple construction method.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における半導体装置の斜視図。FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the invention.

【図2】同実施例における半導体装置の要部断面図。FIG. 2 is a cross-sectional view of essential parts of a semiconductor device in the example.

【図3】同実施例における研磨装置の概略図FIG. 3 is a schematic view of a polishing apparatus in the same embodiment.

【図4】従来の半導体装置の斜視図。FIG. 4 is a perspective view of a conventional semiconductor device.

【図5】従来の半導体装置の要部断面図。FIG. 5 is a sectional view of a main part of a conventional semiconductor device.

【図6】従来の半導体装置の回路基板の製造工程図。FIG. 6 is a manufacturing process diagram of a circuit board of a conventional semiconductor device.

【図7】従来の半導体装置の不良発生要因説明図。FIG. 7 is an explanatory diagram of causes of defects in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1、21 透光性を有するガラス基板 2、22 厚膜Au電極 3、24 回路導体層 4、25 厚膜下部Ag導体 5、26 厚膜絶縁層 6、27 厚膜上部Ag導体 7、28 厚膜保護層 8、30 半導体イメージセンサチップ 9、31 素子 10、32 絶縁層 11、33 Al配線 12、34 保護層 13、35 Al電極 14、36 紫外線硬化型絶縁樹脂 23 厚膜Au電極の研磨面 29 帯状基準領域 37 研磨装置のフレーム 38 1対の上部ローラ 39 回転グラインダ 40 基板搬送用のローダ用ローラ 41 バネ 1, 21 Light-transmissive glass substrate 2, 22 Thick film Au electrode 3, 24 Circuit conductor layer 4, 25 Thick film lower Ag conductor 5, 26 Thick film insulating layer 6, 27 Thick film upper Ag conductor 7, 28 thickness Film protective layer 8,30 Semiconductor image sensor chip 9,31 Element 10,32 Insulating layer 11,33 Al wiring 12,34 Protective layer 13,35 Al electrode 14,36 UV curable insulating resin 23 Polished surface of thick film Au electrode 29 Belt-shaped Reference Area 37 Frame of Polishing Device 38 Pair of Upper Rollers 39 Rotating Grinder 40 Loader Roller for Transferring Substrate 41 Spring

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 上面に回路導体層と前記回路導体層に接
続する厚膜導電性電極を有する透光性回路基板と、前記
透光性回路基板の上面に光硬化型絶縁樹脂を介して半導
体素子を有し、前記半導体素子の素子面の反対側より加
圧して、前記透光性回路基板の所定の位置に前記厚膜導
電性電極と前記半導体素子の素子面に形成した電極を当
接させた状態で紫外線を照射して光硬化型絶縁樹脂を硬
化して半導体素子を固定し、かつ電気的に接続する半導
体装置において、前記厚膜導電性電極は、スクリーン印
刷法にて導電性ペーストを塗布した後、レベリング、乾
燥、焼成を行なってから、この厚膜導電性膜の上部に研
磨を施し研磨面を形成したことを特徴とする半導体装
置。
1. A translucent circuit board having a circuit conductor layer on its upper surface and a thick film conductive electrode connected to the circuit conductor layer, and a semiconductor on the upper surface of the translucent circuit board via a photocurable insulating resin. The device has an element, and pressure is applied from the side opposite to the element surface of the semiconductor element, and the thick film conductive electrode and the electrode formed on the element surface of the semiconductor element are brought into contact with each other at a predetermined position of the translucent circuit board. In the semiconductor device in which the semiconductor elements are fixed by electrically irradiating the photo-curable insulating resin by irradiating the ultraviolet rays in the above state, and the thick film conductive electrodes are conductive paste by a screen printing method. After applying, leveling, drying, and baking, and then polishing the upper surface of the thick conductive film to form a polished surface.
【請求項2】 厚膜導電性電極はAuとしたことを特徴
とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the thick film conductive electrode is Au.
【請求項3】 半導体素子がイメージセンサであること
を特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the semiconductor element is an image sensor.
【請求項4】 厚膜導電性電極の膜上部の研磨は、透光
性回路基板の上面に帯状の前記厚膜導電性電極及び回路
導体層の形成してない基準領域を独立して2箇所以上設
けた構成とし、前記帯状基準領域のみを当接して走行す
るよう配置された1対の同形のローラと、前記ローラと
剛性を有するフレームを介して前記透光性回路基板の上
面の厚膜導電性電極上の所定の位置に設置された回転グ
ラインダと、前記フレームにバネを介して前記透光性回
路基板の下面と当接するよう回転ローラを配置した構造
において、前記回転ローラは前記透光性回路基板を、バ
ネ力により前記1対のローラに適当な一定の力で押し当
てながら回転することで前記透光性回路基板を搬送し、
前記回転グラインダは基準領域の凹凸を検出する前記1
対のローラに連動することにより前記透光性回路基板上
面と一定距離を保ちながら、回転して前記厚膜導電性電
極を研磨する機構を備えた研磨装置にて施し、研磨面を
形成したことを特徴とする請求項1記載の半導体装置の
製造方法。
4. The polishing of the film upper portion of the thick film conductive electrode is carried out at two independent locations on the upper surface of the transparent circuit board, where the strip-shaped thick film conductive electrode and the reference region where the circuit conductor layer is not formed are independently formed. A thick film on the upper surface of the translucent circuit board via a pair of rollers of the same shape arranged so as to contact only the strip-shaped reference region and to travel, and a frame having rigidity with the rollers. In a structure in which a rotating grinder installed at a predetermined position on a conductive electrode and a rotating roller are arranged in the frame so as to come into contact with the lower surface of the transparent circuit board via a spring, the rotating roller is the transparent member. The transparent circuit board is conveyed by rotating the flexible circuit board while pressing it against the pair of rollers with an appropriate constant force by a spring force,
The rotating grinder detects irregularities in a reference area.
The polishing surface was formed by a polishing device equipped with a mechanism for rotating and polishing the thick film conductive electrode while keeping a constant distance from the upper surface of the transparent circuit board by interlocking with a pair of rollers. The method for manufacturing a semiconductor device according to claim 1, wherein
JP29413291A 1991-11-11 1991-11-11 Semiconductor device and its manufacturing method Pending JPH05136208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29413291A JPH05136208A (en) 1991-11-11 1991-11-11 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29413291A JPH05136208A (en) 1991-11-11 1991-11-11 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH05136208A true JPH05136208A (en) 1993-06-01

Family

ID=17803718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29413291A Pending JPH05136208A (en) 1991-11-11 1991-11-11 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH05136208A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019009234A (en) * 2017-06-22 2019-01-17 スタンレー電気株式会社 Method of manufacturing electronic device and, apparatus for manufacturing electronic device
JP2019009235A (en) * 2017-06-22 2019-01-17 スタンレー電気株式会社 Method of manufacturing electronic device, and, apparatus for manufacturing electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019009234A (en) * 2017-06-22 2019-01-17 スタンレー電気株式会社 Method of manufacturing electronic device and, apparatus for manufacturing electronic device
JP2019009235A (en) * 2017-06-22 2019-01-17 スタンレー電気株式会社 Method of manufacturing electronic device, and, apparatus for manufacturing electronic device

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