JPH04335543A - Mounting of ic chip - Google Patents
Mounting of ic chipInfo
- Publication number
- JPH04335543A JPH04335543A JP10710891A JP10710891A JPH04335543A JP H04335543 A JPH04335543 A JP H04335543A JP 10710891 A JP10710891 A JP 10710891A JP 10710891 A JP10710891 A JP 10710891A JP H04335543 A JPH04335543 A JP H04335543A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- mounting
- circuit board
- bonding
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 abstract description 6
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はＩＣチップを回路基板に
実装することに係り、特に実装密度の向上に好適なＩＣ
実装に関する。[Industrial Application Field] The present invention relates to mounting an IC chip on a circuit board, and particularly to mounting an IC chip on a circuit board.
Regarding implementation.
【０００２】0002
【従来の技術】従来のＩＣチップ実装は、金属ワイヤー
を使いＩＣチップのＩＣパットと回路基板を接続し電気
的な導通をとったりあるいは、回路基板からフィンガー
を出し、ＩＣチップのＩＣパットに圧着により接続し電
気的な導通をとり実装を行っていた。[Prior Art] Conventional IC chip mounting involves connecting the IC pads of the IC chip and the circuit board using metal wires to establish electrical continuity, or by taking out fingers from the circuit board and crimping them onto the IC pads of the IC chip. They were connected to establish electrical continuity and then mounted.
【０００３】0003
【発明が解決しようとする課題】上記従来技術では、Ｉ
Ｃチップの高密度化により実装密度の限界が出てきてい
る。[Problem to be Solved by the Invention] In the above prior art, I
As the density of C chips increases, there is a limit to the packaging density.
【０００４】本発明の目的はワイヤーボンディングとギ
ャグボンディングを併用することにより、高密度なＩＣ
チップ実装を実現することにある。An object of the present invention is to fabricate a high-density IC by using wire bonding and gag bonding together.
The purpose is to realize chip mounting.
【０００５】[0005]
【課題を解決するための手段】上記目的は、ＩＣチップ
のＩＣパッドにギャグボンディングを行いＩＣチップと
回路基板のフィンガーを樹脂等で固定し、その後でワイ
ヤーボンディングを行うことにより併用ができるため達
成される。[Means for solving the problem] The above object is achieved because it can be used in combination by performing gag bonding to the IC pad of the IC chip, fixing the IC chip and the fingers of the circuit board with resin, etc., and then performing wire bonding. be done.
【０００６】[0006]
【実施例】以下実施例に基づいて本発明を詳しく説明す
る。EXAMPLES The present invention will be explained in detail below based on examples.
【０００７】図２は従来の実施例である。図２の（ａ）
はワイヤーボンディングによるＩＣチップ実装の断面で
あり、回路基板２にＩＣチップ１をのせ、金属ワイヤー
４によってＩＣチップのＩＣパッドと回路基板を接続す
るが、ＩＣチップのパッドの数が多くなれば、１本１本
ボンディングを行うため、それだけ実装時間がかかる。
また、ＩＣチップのパッド密度を上げるために、パッド
間の距離を縮めればパッド間でワイヤーが接触してしま
う恐れがある。しかし、ワイヤーボンディングはワイヤ
ーの修正等が、簡単なため、パッド数が少ない時には有
効である。図２の（ｂ）はギャグボンディングによるＩ
Ｃチップ実装の断面であり、ＩＣチップ１がＩＣパンプ
５を介して回路基板のフィンガー３と接続される。この
方式だと１回でボンディングを行うため、ＩＣチップの
パッド数に関係なく実装時間を少なくできる。しかし、
１度ボンディングを行うと修正するのにたいへん時間が
かかり、効率が悪くなってしまう。FIG. 2 shows a conventional embodiment. Figure 2(a)
is a cross section of IC chip mounting by wire bonding, where the IC chip 1 is placed on the circuit board 2 and the IC pads of the IC chip and the circuit board are connected by the metal wire 4. However, as the number of pads on the IC chip increases, Since bonding is performed one by one, the mounting time is increased accordingly. Furthermore, if the distance between pads is reduced in order to increase the pad density of an IC chip, there is a risk that wires may come into contact between the pads. However, wire bonding is effective when the number of pads is small because it is easy to modify the wire. Figure 2(b) shows I by gag bonding.
This is a cross section of C chip mounting, in which the IC chip 1 is connected to the finger 3 of the circuit board via the IC pump 5. With this method, bonding is performed in one step, so the mounting time can be reduced regardless of the number of pads on the IC chip. but,
Once bonding is performed, it takes a lot of time to correct it, resulting in poor efficiency.
【０００８】本発明は、図１の様な断面になる。まず、
ＩＣチップ１と回路基板のフィンガー３をＩＣバンプ５
を介して接続を行うこの部分は、回路基板のフィンガー
３がたいへん薄い金属であるため強度的に非常に弱くな
ってしまう。そのため、この接合部を樹脂６により固定
を行う。これによりＩＣチップと回路基板との強度を増
すことができる。次に、金属ワイヤー４によりＩＣチッ
プ１と回路基板２の接続を行う。この様にワイヤーボン
ディングとギャグボンディングを組み合せることが可能
である。The present invention has a cross section as shown in FIG. first,
IC chip 1 and circuit board finger 3 are connected to IC bump 5
Since the fingers 3 of the circuit board are made of very thin metal, the strength of this part where the connection is made is very weak. Therefore, this joint portion is fixed with resin 6. This increases the strength of the IC chip and circuit board. Next, the IC chip 1 and the circuit board 2 are connected using the metal wire 4. In this way, it is possible to combine wire bonding and gag bonding.
【０００９】以上の様に、図１のＩＣチップ実装を行う
ことにより、従来より実装密度の向上が可能となる。As described above, by performing the IC chip mounting shown in FIG. 1, it is possible to improve the mounting density compared to the conventional method.
【００１０】0010
【発明の効果】本発明によれば、ＩＣチップの実装にワ
イヤーボンディング及びギャグボンディングの２つの方
式を利用できるため、今まで以上の高密度な実装が出来
る効力がある。According to the present invention, since two methods, wire bonding and gag bonding, can be used for mounting IC chips, it is possible to perform higher density mounting than ever before.
【図１】本発明の実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】本発明を説明する上での従来の実装を示す断面
図である。FIG. 2 is a cross-sectional view showing a conventional implementation for explaining the present invention.
１ ＩＣチップ ２ 回路基板 ３ フィンガー ４ 金属ワイヤー ５ ＩＣバンプ ６ 樹脂 1 IC chip 2 Circuit board 3 Finger 4 Metal wire 5 IC bump 6 Resin
Claims (1)
いて、ギャグボンディングとワイヤーボンディングを併
用することを特徴とするＩＣチップ実装。1. An IC chip mounting characterized in that gag bonding and wire bonding are used together in mounting the IC chip on a circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10710891A JPH04335543A (en) | 1991-05-13 | 1991-05-13 | Mounting of ic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10710891A JPH04335543A (en) | 1991-05-13 | 1991-05-13 | Mounting of ic chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04335543A true JPH04335543A (en) | 1992-11-24 |
Family
ID=14450674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10710891A Pending JPH04335543A (en) | 1991-05-13 | 1991-05-13 | Mounting of ic chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04335543A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222594A (en) * | 1995-02-14 | 1996-08-30 | Nec Corp | Semiconductor device |
-
1991
- 1991-05-13 JP JP10710891A patent/JPH04335543A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222594A (en) * | 1995-02-14 | 1996-08-30 | Nec Corp | Semiconductor device |
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