JPH04334053A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04334053A JPH04334053A JP3102992A JP10299291A JPH04334053A JP H04334053 A JPH04334053 A JP H04334053A JP 3102992 A JP3102992 A JP 3102992A JP 10299291 A JP10299291 A JP 10299291A JP H04334053 A JPH04334053 A JP H04334053A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- resin
- shielding member
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229920005989 resin Polymers 0.000 claims abstract description 29
- 239000011347 resin Substances 0.000 claims abstract description 29
- 229910000679 solder Inorganic materials 0.000 claims description 33
- 238000007789 sealing Methods 0.000 abstract description 16
- 239000000463 material Substances 0.000 abstract 3
- 238000005476 soldering Methods 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 14
- 239000004020 conductor Substances 0.000 description 11
- 238000010897 surface acoustic wave method Methods 0.000 description 4
- 229920006351 engineering plastic Polymers 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置に係わり、特
にチップを上下に重ねたマルチチップ半導体装置におい
て、第一のチップに重置される第二のチップに遮蔽部材
を被せてはんだ接続部分を覆い、樹脂封止に際して樹脂
が充填されないようになした半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and in particular, in a multi-chip semiconductor device in which chips are stacked one on top of the other, a second chip placed on top of a first chip is covered with a shielding member to form a solder connection area. The present invention relates to a semiconductor device that covers the semiconductor device and prevents it from being filled with resin during resin sealing.
【０００２】近年、電子機器の軽薄短小、高密度実装の
要請に応えて、１個のパッケージの中に複数個の素子（
チップ）を実装した半導体装置が開発されている。この
ような複数個のチップを複合実装した半導体装置（以下
、マルチチップ半導体装置と呼称）には、複数個のメモ
リ素子を実装して見かけ上の記憶容量を増大させた半導
体装置もある。また、いろいろな機能をもった２種類以
上のチップを１個のパッケージの中に収納し、例えばア
ナログ素子とロジック素子の組み合わせとかメモリ素子
とロジック素子の組み合わせといった能動素子同士、あ
るいは例えば、フィルタや振動子などに用いられる表面
弾性波（ＳＡＷ）素子とかセンサとして用いられる磁気
抵抗（ＭＲ）素子といった受動素子とロジック素子を複
合したマルチチップ半導体装置もある。In recent years, in response to demands for lighter, thinner, smaller, and higher-density packaging of electronic devices, multiple elements (
Semiconductor devices mounted with chips have been developed. Among such semiconductor devices in which a plurality of chips are mounted in a composite manner (hereinafter referred to as a multi-chip semiconductor device), there is also a semiconductor device in which a plurality of memory elements are mounted to increase the apparent storage capacity. In addition, two or more types of chips with various functions are housed in one package, and active elements such as a combination of analog elements and logic elements, a combination of memory elements and logic elements, or filters, etc. There are also multi-chip semiconductor devices that combine passive elements and logic elements, such as surface acoustic wave (SAW) elements used in vibrators and magnetoresistive (MR) elements used as sensors.
【０００３】ところで、このようなマルチチップ半導体
装置は、生産性を向上させて低価格を実現するためにも
、従来から行われているような樹脂モールドによる封止
を行ってプラスチックパッケージにすることができれば
真に好都合である。[0003] Incidentally, in order to improve productivity and lower prices, such multi-chip semiconductor devices can be packaged in plastic by encapsulating them with resin molding, as has been done in the past. It would be really convenient if this could be done.
【０００４】0004
【従来の技術】半導体素子などのチップを実装する方式
は、チップに設けられた電極部とパッケージの導出端子
との間を如何に接続するかによって多種多様であるが、
大きくはワイヤボンディング法とワイヤレスボンディン
グ法に分けられる。2. Description of the Related Art There are many different methods for mounting chips such as semiconductor devices, depending on how the electrodes provided on the chip and the lead-out terminals of the package are connected.
It can be broadly divided into wire bonding method and wireless bonding method.
【０００５】単体のチップを実装する場合には、チップ
をリードフレームにマウントしてワイヤボンディングす
る方式がよく用いられている。しかし最近では、導出端
子数が多くなり端子の間隔も狭いチップに対しては、ワ
イヤボンディングでは処理し切れなくなり、ワイヤレス
ボンディングが用いられるようになっている。[0005] When mounting a single chip, a method is often used in which the chip is mounted on a lead frame and wire bonded. However, recently, wire bonding cannot handle chips with a large number of lead-out terminals and narrow terminal spacing, and wireless bonding has come to be used.
【０００６】ワイヤレスボンディングには、フリップチ
ップ方式とかビームリード方式などが古くからよく知ら
れているが、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｉｏｎ
Ｂｏｎｄｉｎｇ）方式もよく用いられるようになって
いる。[0006] For wireless bonding, the flip chip method and the beam lead method have been well known for a long time, but TAB (Tape Automation
The bonding method has also become popular.
【０００７】一方、複数個のチップを一つのパッケージ
の中に実装したマルチチップ半導体装置の場合には、チ
ップ同士を接続することが不可欠である。そして、例え
ばＩＣカードのようなチップを平面に並べて実装する場
合には、パッケージにワイヤボンディングし、そのパッ
ケージを介してチップ同士を接続することもできる。On the other hand, in the case of a multi-chip semiconductor device in which a plurality of chips are mounted in one package, it is essential to connect the chips to each other. For example, when chips such as an IC card are mounted side by side on a plane, wire bonding may be performed to a package and the chips may be connected to each other via the package.
【０００８】ところが、少なくとも２個のチップを重ね
てパッケージをできるだけ小さくしようとすると、間隔
をもたせて配置し適宜ループを形成しながらワイヤボン
ディングを行わせる空間的な余裕がない。そこで、チッ
プ同士の接続に対しては、ワイヤレスボンディングが用
いられる。However, when trying to make the package as small as possible by stacking at least two chips, there is no space to arrange the chips with a certain distance between them and to perform wire bonding while forming appropriate loops. Therefore, wireless bonding is used to connect chips to each other.
【０００９】図３は従来のマルチチップ半導体装置の一
例の一部切欠き斜視図、図４は図３の要部の拡大断面図
である。図において、１は第一のチップ、１ａはパッド
、１ｂは導体部、２は第二のチップ、２ａははんだバン
プ、７はパッケージ、７ａは導体パターン、８は蓋、１
０はマルチチップ半導体装置である。FIG. 3 is a partially cutaway perspective view of an example of a conventional multi-chip semiconductor device, and FIG. 4 is an enlarged sectional view of the main part of FIG. In the figure, 1 is the first chip, 1a is a pad, 1b is a conductor, 2 is a second chip, 2a is a solder bump, 7 is a package, 7a is a conductor pattern, 8 is a lid, 1
0 is a multi-chip semiconductor device.
【００１０】第一のチップ１は、例えばロジック素子な
どである。そして、第一のチップ１の上には、例えばア
ナログ素子とかＳＡＷフィルタのような受動素子からな
る第二のチップ２が積み重なって接続されている。この
第一のチップ１と第二のチップ２の接続はワイヤを用い
ない直付けで行われ、フリップチップ方式とも呼ばれる
ワイヤレスボンディング方式で接続される。The first chip 1 is, for example, a logic element. On top of the first chip 1, a second chip 2 consisting of passive elements such as analog elements and SAW filters is stacked and connected. The first chip 1 and the second chip 2 are connected by direct attachment without using wires, and by a wireless bonding method also called a flip-chip method.
【００１１】第二のチップ２の電極部２ｂには、図４に
示したようにはんだを玉状に盛ったはんだバンプ２ａが
設けられる。そして、このはんだバンプ２ａに対向する
第一のチップ１には、予備はんだを施した導体部１ｂが
設けられる。[0011] The electrode portion 2b of the second chip 2 is provided with a solder bump 2a, which is a bead-shaped solder layer, as shown in FIG. The first chip 1 facing the solder bumps 2a is provided with a conductor portion 1b which is pre-soldered.
【００１２】第一のチップ１と第二のチップ２の接続に
際しては、第二のチップ２をフェースダウンして第二の
チップ２を導体部１ｂに載せ、導体部１ｂの予備はんだ
とはんだバンプ２ａを加熱溶融すれば、両者１ｂと２ａ
が融着する。[0012] When connecting the first chip 1 and the second chip 2, place the second chip 2 face down on the conductor part 1b, and apply preliminary solder and solder bumps on the conductor part 1b. If 2a is heated and melted, both 1b and 2a
are fused.
【００１３】この方式ははんだリフロー方式とも呼ばれ
、はんだバンプ２ａの大きさつまりはんだの量を制御す
れば、数百μｍの狭いピッチに対して比較的粗い位置合
わせであっても、はんだの表面張力によって融着される
位置が自己修正されるので、自動化することも容易であ
る。This method is also called the solder reflow method, and if the size of the solder bumps 2a, that is, the amount of solder, is controlled, the solder surface can be adjusted even if the alignment is relatively rough for a narrow pitch of several hundred μm. It is also easy to automate because the position of the weld is self-corrected by tension.
【００１４】こうして第二のチップ２を背負った第一の
チップ１は、例えば、セラミック製のパッケージ７に実
装される。最近では、このパッケージ７が例えばポリイ
ミド系のスーパエンジニアリングプラスチック （エン
プラ） で構成されるようになってきている。The first chip 1 carrying the second chip 2 in this manner is mounted in a package 7 made of ceramic, for example. Recently, this package 7 has come to be made of, for example, polyimide-based super engineering plastic.
【００１５】このパッケージ７に第一のチップ１の実装
するには、まず、第一のチップ１をパッケージ７の底部
に接着し、次いで、第一のチップ１に設けられたパッド
１ａと、そのパッド１ａに対向したパッケージ７に設け
られた導体パターン７ａ間を、ワイヤ６でボンディング
することによって行われる。次いで、パッケージ７に蓋
８を被せて気密封止すれば、マルチチップ半導体装置が
できあがる。In order to mount the first chip 1 on this package 7, first, the first chip 1 is glued to the bottom of the package 7, and then the pads 1a provided on the first chip 1 and its This is done by bonding with a wire 6 between conductor patterns 7a provided on the package 7 facing the pad 1a. Next, by covering the package 7 with a lid 8 and hermetically sealing it, a multi-chip semiconductor device is completed.
【００１６】[0016]
【発明が解決しようとする課題】以上述べたように、従
来から第一のチップと第二のチップを接続する方式には
、はんだバンプを用いたフリップチップ方式のフェース
ダウンボンディングが採られている。ところが、はんだ
が比較的容易に腐食したりマイグレーションを起こした
りするのではんだ接続部分の信頼性が得難い。[Problems to be Solved by the Invention] As mentioned above, the method of connecting the first chip and the second chip has traditionally been flip-chip type face-down bonding using solder bumps. . However, since the solder corrodes or migrates relatively easily, it is difficult to obtain reliability at the soldered joint.
【００１７】そのために、従来のマルチチップ半導体装
置の実装形態は、パッケージに蓋を被せて内部に空間を
設け、せんだ接続部分に異物が接触しないような構成に
なっている。つまり、封止用の樹脂の透水性を考慮する
と、樹脂封止による安価で生産性に富んだパッケージが
できなかった。[0017] For this reason, in the conventional mounting form of a multi-chip semiconductor device, the package is covered with a lid to provide a space inside to prevent foreign matter from coming into contact with the soldered connection portion. In other words, considering the water permeability of the sealing resin, it has not been possible to create a package that is inexpensive and highly productive by resin sealing.
【００１８】また、樹脂封止の場合には、金型のキャビ
ティ内の空間全体に樹脂が充填されるので、第二のチッ
プが例えばＳＡＷフィルタのような素子の表面に異物が
密接すると機能しなくなるようなチップの場合にも、樹
脂封止によるパッケージができなかった。In addition, in the case of resin sealing, since the entire space inside the mold cavity is filled with resin, the second chip may not function if foreign matter comes into close contact with the surface of the element, such as a SAW filter. Even in the case of chips that would otherwise disappear, it was not possible to package them using resin sealing.
【００１９】そこで本発明は、第一のチップに重置され
る第二のチップに遮蔽部材を冠着してはんだ接続部分を
覆い、樹脂封止に際して樹脂が充填されないようになし
た半導体装置を提供することを目的としている。Accordingly, the present invention provides a semiconductor device in which a shielding member is attached to a second chip superimposed on the first chip to cover the solder connection portion so that resin is not filled during resin sealing. is intended to provide.
【００２０】[0020]
【課題を解決するための手段】上で述べた課題は、第一
のチップと、第二のチップと、遮蔽部材を有し、前記第
一のチップは、リードフレームの、ステージにマウント
され、かつインナリードにワイヤボンディングされるも
のであり、前記第二のチップは、はんだバンプを具え、
該はんだバンプを介して第一のチップにフェースダウン
ボンディングされるものであり、前記遮蔽部材は、帽子
状をなして第二のチップに液密可能に外嵌するものであ
って、第一のチップがマウント済みのリードフレームが
が樹脂封止される際、該第一のチップと第二のチップの
はんだ接続部分に樹脂が流入することを遮るものである
ように構成された半導体装置によって解決される。[Means for Solving the Problem] The problem described above has a first chip, a second chip, and a shielding member, the first chip is mounted on a stage of a lead frame, and the second chip is wire-bonded to the inner lead, and the second chip includes a solder bump,
The shielding member is face-down bonded to the first chip via the solder bump, and the shielding member has a cap shape and is fitted onto the second chip in a liquid-tight manner. The problem is solved by a semiconductor device configured to prevent resin from flowing into the solder connection portion of the first chip and the second chip when the lead frame on which the chip is mounted is sealed with resin. be done.
【００２１】[0021]
【作用】２種類のチップを重ねて１個のパッケージの中
に封止してなる従来のマルチチップ半導体装置は、フェ
ースダウンボンディングのはんだ接続部分を保護するた
めにパッケージの中に空間を設けた実装形態が採られて
いたが、本発明においては、樹脂封止するようにしてい
る。[Operation] Conventional multi-chip semiconductor devices, which are made by stacking two types of chips and sealing them in one package, require a space inside the package to protect the solder connection part of face-down bonding. Although a mounting form has been adopted, in the present invention, resin sealing is used.
【００２２】すなわち、本発明では、第一のチップの上
にはんだバンプを用いたフリップチップ方式のフェース
ダウンボンディングされた第二のチップに、帽子状の遮
蔽部材を被せるようにしている。そして、樹脂封止の際
に、この遮蔽部材によって、第一のチップと第二のチッ
プの間のはんだ接続部分に樹脂が流れ込まないようにし
ている。That is, in the present invention, a hat-shaped shielding member is placed over the second chip, which is face-down bonded using a flip-chip method using solder bumps on the first chip. During resin sealing, the shielding member prevents the resin from flowing into the solder connection portion between the first chip and the second chip.
【００２３】そうすると、はんだ接続部分がパッケージ
の樹脂と遮蔽部材とに二重に覆われて外気と遮断される
ので、はんだが腐食したりマイグレーションを起こした
りして、接続の信頼性が損なわれることを防止すること
ができる。[0023] In this case, the solder connection part is doubly covered with the resin of the package and the shielding member and is isolated from the outside air, which may cause corrosion or migration of the solder, impairing the reliability of the connection. can be prevented.
【００２４】[0024]
【実施例】図１は本発明の実施例の一部切欠き斜視図、
図２は図１の要部の分解斜視図、である。図において、
１は第一のチップ、１ａはパッド、１ｂは導体部、２は
第二のチップ、２ａははんだバンプ、３は遮蔽部材、４
はリードフレーム、４ａはステージ、４ｂはインナリー
ド、５は樹脂、６はワイヤである。[Embodiment] FIG. 1 is a partially cutaway perspective view of an embodiment of the present invention.
FIG. 2 is an exploded perspective view of the main parts of FIG. 1. In the figure,
1 is a first chip, 1a is a pad, 1b is a conductor part, 2 is a second chip, 2a is a solder bump, 3 is a shielding member, 4
is a lead frame, 4a is a stage, 4b is an inner lead, 5 is a resin, and 6 is a wire.
【００２５】図１〜図２において、第一のチップ１には
、周縁部に複数個のワイヤボンディング用のパッド１ａ
が設けられ、中央部には第二のチップ２がフリップチッ
プ方式のフェースダウンボンディングがなされる複数個
の予備はんだした導体部１ｂが設けられている。第二の
チップ２には、周縁部に複数個のはんだバンプ２ａが設
けられている。In FIGS. 1 and 2, a first chip 1 has a plurality of wire bonding pads 1a on its periphery.
A plurality of pre-soldered conductor portions 1b are provided in the central portion to which the second chip 2 is subjected to face-down bonding using a flip-chip method. A plurality of solder bumps 2a are provided on the periphery of the second chip 2.
【００２６】第一のチップ１に第二のチップ２を接続す
るには、第一のチップ１の上に、導体部１ｂとはんだバ
ンプ２ａが対向するように第二のチップ２をフェースダ
ウンして載せ、はんだを加熱溶融させて導体部１ｂとは
んだバンプ２ａを融着させる。こうして、第一のチップ
１と第二のチップ２が接続され、こゝまでの構成は従来
例の変わらない。To connect the second chip 2 to the first chip 1, place the second chip 2 face down on top of the first chip 1 so that the conductor portion 1b and the solder bump 2a face each other. The conductor portion 1b and the solder bump 2a are fused together by heating and melting the solder. In this way, the first chip 1 and the second chip 2 are connected, and the configuration up to this point is unchanged from the conventional example.
【００２７】第一のチップ１に第二のチップ２をフェー
スダウンボンディングしたあとは、第二のチップ２に図
２に示したように遮蔽部材３を被せる。この遮蔽部材３
は帽子状の形状をしており、金属ないしは樹脂封止の際
の成形温度よりも高い、例えば耐熱温度が ２００°Ｃ
を超えるＰＰＳなどのスーパエンプラで構成することが
できる。After face-down bonding the second chip 2 to the first chip 1, the second chip 2 is covered with a shielding member 3 as shown in FIG. This shielding member 3
It has a hat-like shape and has a heat resistance temperature higher than the molding temperature for metal or resin sealing, for example, 200°C.
It can be constructed from super engineering plastics such as PPS that exceeds
【００２８】遮蔽部材３の、第一のチップ１に当接する
下端面は、第一のチップ１の上に設けられたいろいろな
素子を損傷しないように平滑に仕上げてある。そして、
精度よく作れば遮蔽部材３を第二のチップ２に嵌合させ
て下端面を第一のチップ１に液密可能に密接させること
ができる。しかし、必要に応じて、例えばシリコン樹脂
などの接着材を用い、遮蔽部材３を第一のチップ１に固
着した方がより実用的である。こうして、遮蔽部材３は
、第一のチップ１と第二のチップ２の間隙に存在する接
続部分を液密可能に覆うようになっている。The lower end surface of the shielding member 3 that comes into contact with the first chip 1 is finished smooth so as not to damage the various elements provided on the first chip 1. and,
If made accurately, the shielding member 3 can be fitted onto the second chip 2 and its lower end surface can be brought into close contact with the first chip 1 in a liquid-tight manner. However, it is more practical to fix the shielding member 3 to the first chip 1 using an adhesive such as silicone resin, if necessary. In this way, the shielding member 3 covers the connection portion existing in the gap between the first chip 1 and the second chip 2 in a liquid-tight manner.
【００２９】次いで、遮蔽部材３が被せられた第一のチ
ップ１は、リードフレーム４のステージ４ａにマウント
される。そして、パッド１ａとインナリード４ｂの間が
ワイヤボンディングされてワイヤ６で接続される。Next, the first chip 1 covered with the shielding member 3 is mounted on the stage 4a of the lead frame 4. Then, the pad 1a and the inner lead 4b are connected by a wire 6 by wire bonding.
【００３０】樹脂封止は、通常行われているエポキシ系
樹脂などの低圧トランスファモールドによって行われる
、この際、樹脂５は遮蔽部材３に遮られて、第一のチッ
プ１と第二のチップ２の接続部分には流れ込まないよう
になっている。樹脂封止したあとは、リードフレーム４
を切断し、アウタリードを整形すれば本発明になるマル
チチップの半導体装置ができあがる。Resin sealing is performed by a commonly used low-pressure transfer molding of epoxy resin, etc. At this time, the resin 5 is blocked by the shielding member 3 and the first chip 1 and the second chip 2 are sealed. It is designed so that it does not flow into the connection part. After resin sealing, lead frame 4
By cutting and shaping the outer leads, a multi-chip semiconductor device according to the present invention is completed.
【００３１】[0031]
【発明の効果】従来からチップを上下に重ねたマルチチ
ップ半導体装置においては、チップ間の接続にはんだバ
ンプを用いたフリップチップ方式のフェースダウンボン
ディングが用いられているが、はんだ接続部分を保護す
るために従来は樹脂封止によるパッケージができなかっ
たが、本発明においては、上に重なる第二のチップに遮
蔽部材を被せる。そして、樹脂封止の際、はんだ接続部
分に樹脂が流れ込まないようにしている。[Effects of the Invention] Conventionally, in multi-chip semiconductor devices in which chips are stacked one on top of the other, flip-chip type face-down bonding using solder bumps has been used to connect chips. Therefore, in the past, it was not possible to package with resin sealing, but in the present invention, the overlying second chip is covered with a shielding member. Then, during resin sealing, the resin is prevented from flowing into the solder connection portion.
【００３２】その結果、はんだ接続部分の信頼性を保っ
たまゝ生産性の向上と低価格化を図ることができるよう
になった。従って、今後ますます多機能化が進められて
増加の傾向にあるマルチチップ半導体装置の発展に対し
て、本発明は寄与するところが大である。As a result, it has become possible to improve productivity and reduce costs while maintaining the reliability of the soldered joints. Therefore, the present invention will greatly contribute to the development of multi-chip semiconductor devices, which are expected to become more and more multi-functional in the future.
【図１】 本発明の実施例の一部切欠き斜視図である
。FIG. 1 is a partially cutaway perspective view of an embodiment of the invention.
【図２】 図１の要部の分解斜視図である。FIG. 2 is an exploded perspective view of the main parts of FIG. 1.
【図３】 従来のマルチチップ半導体装置の一例の一
部切欠き斜視図である。FIG. 3 is a partially cutaway perspective view of an example of a conventional multi-chip semiconductor device.
【図４】 図３の要部の拡大断面図である。FIG. 4 is an enlarged sectional view of the main part of FIG. 3.
１ 第一のチップ １ａ パッド
１ｂ 導体部
２ 第二のチップ ２ａ はんだバ
ンプ３ 遮蔽部材
４ リードフレーム ４ａ ステージ
４ｂ インナリード
５ 樹脂
６ ワイヤ1 First chip 1a Pad
1b Conductor part 2 Second chip 2a Solder bump 3 Shielding member 4 Lead frame 4a Stage
4b Inner lead 5 Resin 6 Wire
Claims (2)
プ（２） と、遮蔽部材（３） を有し、前記第一のチ
ップ（１） は、リードフレーム（４） の、ステージ
（４ａ）にマウントされ、かつインナリード（４ｂ）に
ワイヤボンディングされるものであり、前記第二のチッ
プ（２） は、はんだバンプ（２ａ）を具え、該はんだ
バンプ（２ａ）を介して前記第一のチップ（１） にフ
ェースダウンボンディングされるものであり、前記遮蔽
部材（３） は、帽子状をなして前記第二のチップ（２
） に液密可能に外嵌するものであって、前記第一のチ
ップ（１） がマウント済みの前記リードフレーム（４
） が樹脂封止される際、該第一のチップ（１） と第
二のチップ（２） のはんだ接続部分に樹脂（５） が
流入することを遮るものであることを特徴とする半導体
装置。Claim 1: A first chip (1), a second chip (2), and a shielding member (3), the first chip (1) being a stage of a lead frame (4). (4a) and wire bonded to the inner lead (4b), the second chip (2) is provided with a solder bump (2a), and the second chip (2) is provided with a solder bump (2a), and the The shielding member (3) has a hat shape and is bonded face down to the first chip (1).
) is externally fitted in a liquid-tight manner to the lead frame (4) on which the first chip (1) is mounted.
) is encapsulated with resin, the semiconductor device prevents the resin (5) from flowing into the solder connection portion of the first chip (1) and the second chip (2). .
第二のチップ（２） に外嵌して前記第一のチップ（１
） に接着されるものである請求項１記載の半導体装置
。2. The shielding member (3) has a lower end surface that fits over the second chip (2) and is connected to the first chip (1).
) The semiconductor device according to claim 1, wherein the semiconductor device is bonded to a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3102992A JPH04334053A (en) | 1991-05-09 | 1991-05-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3102992A JPH04334053A (en) | 1991-05-09 | 1991-05-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04334053A true JPH04334053A (en) | 1992-11-20 |
Family
ID=14342194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3102992A Withdrawn JPH04334053A (en) | 1991-05-09 | 1991-05-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04334053A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7088983B2 (en) | 1999-02-03 | 2006-08-08 | Rohm Co., Ltd. | Semiconductor device for radio communication device, and radio communication device using said semiconductor device |
-
1991
- 1991-05-09 JP JP3102992A patent/JPH04334053A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7088983B2 (en) | 1999-02-03 | 2006-08-08 | Rohm Co., Ltd. | Semiconductor device for radio communication device, and radio communication device using said semiconductor device |
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