JPH04333929A - Cache memory control system - Google Patents

Abstract

PURPOSE:To accelerate a program processing by staying the instruction train of a program loop under execution existent in a cache memory until the end a loop processing. CONSTITUTION:When the condition of a branching instruction for returning is established and a size (loop size) from the branching destination instruction to the branching instruction is smaller than a cache memory size, the address of the branching instruction, the address of the branching destination and the loop side are set to registers 11, 12 and 13 and by detecting the establishment of the condition in the case of executing the same branching instruction again at a comparator 14 and an AND gate 18, a state under loop execution is detected to turn a flag 20 on. When the flag 20 is turned on, a cache controller 4 extracts the loop instruction train shown by the registers 11-13 from a main memory 2 and writes it is a cache memory 3 and until the comparator 14 detects that the address of the instruction to be executed exceeds the address of the branching instruction, the loop instruction train in the cache memory 3 is not turned out.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus equipped with a cache memory, and more particularly to a cache memory control method suitable for executing a program loop.

0002

2. Description of the Related Art In recent years, information processing apparatuses are generally equipped with a cache memory in which a copy of a portion of the contents of a memory such as a main memory is stored.

In this type of information processing device, when a memory access request is made, it is checked whether or not the target instruction (or data) exists in the cache memory, that is, whether there is a cache hit or not (mishit). By retrieving the target instruction (or data) from the cache memory, the access speed of the instruction (or data) is increased.

[0004] Furthermore, in the event of a miss, the instruction (or data) that caused the miss is accessed to read a block of data of a predetermined size containing the target instruction (or data), and the block data is stored in the cache memory. This makes it possible to speed up access to instructions (or data) in the vicinity of the instruction (or data) following the instruction (or data). When this block data is stored in the cache memory, other block data previously stored in the storage location will be evicted.

[0005]

As described above, in the past, instructions (or data) were stored from the main memory to the cache memory in units of blocks of a predetermined size. However, with the method of replacing the cache memory in block units, even if there is a loop in the program and the entire loop (instruction sequence) can be stored in the cache memory, some data may become invalid. However, there is a problem in that the program may be overwritten with other data, increasing the processing time of the program.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to transfer the instruction string of the program loop being executed to the processing of the loop when the instruction string constituting the program loop being executed can fit into the cache memory. It is an object of the present invention to provide a cache memory control method that can reliably make programs reside in a cache memory until they are completed, thereby speeding up program processing.

[0007]

[Means for Solving the Problems] The present invention detects that a program loop consisting of an instruction sequence that can fit into a cache memory is being executed when a branch of a previous branch instruction is established, thereby reconfiguring the loop. The entire instruction sequence is stored in the cache memory, and the instruction sequence forming the loop is not evicted from the cache memory until the end of the processing of the same loop is detected.

[0008]

[Operation] In the above configuration, the CPU detects that the instruction string from the branch destination instruction indicated by the branch destination address to the branch instruction is completely stored in the cache memory when a branch of the previous branch instruction is established. The instruction address of the branch instruction, the branch destination address, and the size of the instruction sequence from the branch destination instruction to the branch instruction are held in registers, and if the branch instruction is executed again and the branch is taken, the branch instruction is inserted into the program loop. It detects that a program loop is being executed, that is, a program loop is being executed, and requests the cache controller to store a sequence of instructions constituting the program loop in the cache memory.

[0009] Accordingly, the cache controller takes out the instruction sequence of the program loop from, for example, the main memory and stores it in the cache memory according to the contents of the register. During the period when the contents of the above registers are valid (during the execution period of the program loop), the cache controller responds to access requests from the CPU by performing normal memory access rather than caching. Takes an instruction and sends it to the CPU.

Now, the contents of the above register are determined as follows: When the instruction address of the instruction being executed exceeds the instruction address of the branch instruction held in the above register, it is assumed that the processing of the program loop has ended (the one that has escaped from the loop). ), cleared. When the contents of the register are cleared, the cache controller performs caching in response to an access request from the CPU, and in the case of a cache miss, stores block data including the requested instruction in the cache memory.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of an information processing apparatus having a cache memory to which the present invention is applied.

In FIG. 1, numeral 1 is a CPU which forms the center of the device and is in charge of executing instructions; 2 is a main memory used for storing various programs and data; and 3 is a copy of a part of the contents of the main memory 2, such as a program. A cache memory (instruction cache) in which a copy of a part of is placed, 4 is a cache controller that accesses the cache memory 3 or the main memory 2 in response to a main memory access request from the CPU 1. Note that a cache memory (data cache) in which a copy of part of the data on the main memory 2 is placed is omitted in FIG.

The CPU 1 has a register 11 (REG#1) for holding the instruction address of a conditional branch instruction that specifies the previous branch destination, and a register 11 (REG#1) for holding the instruction address of the conditional branch instruction that specifies the branch destination to return to. Register 12 for holding (
REG#2) and a register 13 (REG#3) are provided. This register 13 is used to hold the size of the instruction string from the instruction at the branch destination address specified by the conditional branch instruction to the branch instruction (hereinafter referred to as loop size). The registers 11 to 13 can be referenced by the cache controller 4.

The CPU 1 also contains the instruction address of the instruction currently being executed (the instruction to be executed) and the register 11 (RE
A comparator 14 is provided to compare the content held in the branch instruction (branch instruction address) of the branch instruction G#1). When the comparator 14 detects that the instruction address of the instruction being executed matches the contents of the register 11, the comparator 14 detects a loop configuration branch instruction, which indicates that a branch instruction for configuring a program loop is being executed. A signal 15 is output, and when it is detected that the instruction address of the instruction being executed exceeds the contents of the register 11, a loop end detection signal 16 indicating the end of the program loop processing is output. This loop end detection signal 16 is
It is used as a clear signal to clear the contents of registers 11 to 13 (REG #1 to #3).

The CPU 1 further includes a logic between the loop configuration branch instruction detection signal 15 from the comparator 14 and a branch established signal 17 indicating that the condition is satisfied (that the branch is established) when the conditional branch instruction is executed. AND gate 18 that takes the product
and a loop instruction string storage flag (F) 20 that is set (turned on) in response to an output signal (hereinafter referred to as a loop execution detection signal) 19 of the AND gate 18. This loop instruction string storage flag 20 is stored in registers 11 to 1.
The configuration instruction sequence of the program loop specified by the contents of 3 (
This command is used to instruct the cache controller 4 to store a loop instruction sequence) in the cache memory 3 and perform cache memory access that does not involve caching. The loop instruction string storage flag 20 is reset (turned off) in response to the output signal of the OR gate 22 which takes the logical sum of the loop end detection signal 16 and the REG rewrite signal 21 indicating rewriting of the registers 11 to 13.

Next, the operation of the configuration shown in FIG. 1 will be explained with reference to FIGS. 2 to 4.
This will be explained with reference to the flowchart. First, when the CPU 1 executes a conditional branch instruction to go back (i.e., a conditional branch instruction in which the branch destination when the condition is met is an address before the branch instruction), when the condition is met and the branch is executed, The value obtained by subtracting the address of the branch destination from the address of the branch instruction (the absolute value of the relative address) is the size of the branch instruction itself (
(instruction length), that is, the instruction sequence from the branch destination instruction to the branch instruction (the loop size when the branch instruction is an instruction for configuring a program loop)
(Step S1 in FIG. 2).

Next, the CPU 1 compares the calculated loop size with the size of the cache memory 3 (cache size) and determines that the loop size is less than or equal to the cache size, that is, the constituent instruction sequence of the corresponding program loop is in the cache memory 3. If it is detected that the registers 11 to 13 (REG #1 to #3) are all cleared (steps S2 and S3 in FIG.
), the address of the branch instruction being executed is stored in register 11, and the address of the branch destination specified by the same branch instruction is stored in register 12.
and set the calculated loop size in the register 13 (step S4 in FIG. 2).

[0018] Furthermore, even if some value has already been set in registers 11 to 13, the CPU 1 determines that the calculated loop size is smaller than the loop size indicated by register 13 (REG#3) (less than or equal to the cache size). If it is larger, the active REG rewrite signal 21 is output (steps S5 and S6 in FIG. 2), and the register setting in step 4 is performed. As a result, registers 11 to 13
is rewritten with information regarding a new program loop that is larger in size than the previously set program loop. At this time, the output signal of the OR gate 22 is
It becomes true in response to the G rewrite signal 21, and thereby the loop instruction string storage flag 20 is turned off.

Now, when the branch is established (branch condition is satisfied), the CPU 1 sequentially executes the instruction sequence after the branch destination instruction. The instruction at this time is given from the cache controller 4 as follows by outputting an instruction access request together with an instruction address from the CPU 1 to the cache controller 4.

That is, the cache controller 4
When there is an instruction access request from 1, the state of the loop instruction string storage flag 20 is checked (step S21 in FIG. 4), and if it is in the off state as in this embodiment, the cache memory 3 is accessed by so-called caching. By doing this (step S23 in FIG. 4), the requested command is obtained and output to the CPU 1. At this time, if a miss occurs, the block containing the requested instruction is of course read from the main memory 2 and written to the corresponding area of the cache memory 3.

[0021] In this way, the instruction sequence after the branch destination instruction is executed in order, and eventually an instruction with the same instruction address as the instruction address held in register 11, that is, information setting in registers 11 to 13, is triggered. When the conditional branch instruction is executed again, the comparator 14 outputs an active loop configuration branch instruction detection signal 15.

At this time, if the condition of the re-executed conditional branch instruction is satisfied, an active branch established signal 17 indicating that the condition is satisfied is output from a decoder (not shown). As a result, the AND gate 18 outputs an active loop execution detection signal 19 indicating that the program loop is being executed (because the re-executed conditional branch instruction is a branch instruction that constitutes a program loop). Then, the loop instruction string storage flag 20 is turned on.

When the loop instruction string storage flag 20 is turned on, the cache controller 4 executes the loop instruction string storage process shown in the flowchart of FIG. 3 as described below.

That is, the cache controller 4 first
Retrieve the contents (branch destination address, loop size) of registers 12 and 13 (REG #2, #3) in PU1 (Figure 3
Step S11). Next, the cache controller 4
Using the branch destination address indicated by the register 12 as the start address, a loop instruction string of the size indicated by the register 13 is sequentially retrieved from the main memory 2 (step S12 in FIG. 3).

[0025] The cache controller 4 then selects a branch destination instruction specified by the instruction address held in the register 11 from the instruction sequence retrieved from the main memory 2, that is, a branch destination instruction specified by the branch destination address held in the register 12. The instruction string (loop instruction string) up to the branch instruction is written in order from the first address of the cache memory 3 (step S13 in FIG. 3). In this way, in this embodiment, when it is detected that a program loop is being executed, the entire instruction sequence of the loop is written to the cache memory 3, which is different from block writing when a miss occurs in conventional caching. I want to be

On the other hand, when the condition of the re-executed branch instruction is satisfied, the CPU 1 sequentially executes the instruction sequence after the branch destination instruction. The instruction at this time is given from the cache controller 4 as follows by outputting an instruction access request together with an instruction address from the CPU 1 to the cache controller 4.

That is, the cache controller 4
When there is an instruction access request from 1, the state of the loop instruction string storage flag 20 is checked (step S21 in FIG. 4), and if it is in the on state as in this example, the register 12 (REG# By subtracting the contents of 2) (branch destination address) and setting the value as the address of the cache memory 3, read access to the cache memory 3 in the same way as normal memory access (step S2 in FIG. 4).
2) Obtain the requested instruction and output it to the CPU 1. At this time, the operation of the so-called cache hit/miss detection mechanism for caching is suppressed or ignored, and caching is not performed. You will not be kicked out either.

In this way, the CPU 1 sequentially executes the loop instruction sequence, and eventually the branch instruction specified by the instruction address held in the register 11 is executed, the branch is not taken, and the access of the next instruction is interrupted. As requested. In this case, since the instruction address of that instruction is larger than the instruction address (branch instruction address) held in the register 11, the active signal from the comparator 14 indicates the end of the program loop processing (exit from the loop). A loop end detection signal 16 is output. As a result, the contents of registers 11 to 13 (REG #1 to #3) are cleared, and the loop instruction string storage flag 20 is turned off. When the loop instruction string storage flag 20 turns off, the cache controller 4 accesses the cache memory 3 by caching in response to an instruction access request from the CPU 1 (step S21 in FIG. 4).
, S23).

In the above embodiment, the case where the register 13 (REG#3) for holding the loop size was provided was explained, but if the instruction length is fixed, the loop size is determined from the contents of registers 11 and 12. Since the size can be determined, the register 13 does not necessarily have to be provided. Furthermore, the processing of the CPU 1 shown in the flowchart of FIG.
This can be easily realized using a hardware circuit.

[0030]

[Effects of the Invention] As detailed above, according to the present invention,
When a branch to the previous branch instruction is taken, by detecting that a program loop consisting of a sequence of instructions that can fit into the cache memory is being executed, all the instruction sequences that constitute the loop are stored in the cache memory, and the execution of the same loop is executed. Since the constituent instructions of the same loop are not ejected from the cache memory until the end of processing is detected, the constituent instructions of the program loop can be fetched at high speed, and program processing can be accelerated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information processing device having a cache memory to which the present invention is applied.

FIG. 2 is a flowchart for explaining a register setting operation in the CPU 1 in FIG. 1;

FIG. 3 is a flowchart for explaining a loop instruction string storage operation in the cache controller 4 of FIG. 1;

4 is a flowchart for explaining a cache access operation in the cache controller 4 of FIG. 1. FIG.

[Explanation of symbols]

1...CPU, 2...Main memory, 3...Cache memory, 4...
Cache controller, 11... register (REG#1
), 12...Register (REG#2), 13...Register (
REG#3), 14... Comparator (first and second detection means)
, 18... AND gate (first detection means), 20... Loop instruction string storage flag (F).

Claims (4)

[Claims] 1. An information processing device equipped with a cache memory, comprising: a first detection means for detecting that a program loop consisting of a sequence of instructions that can fit into the cache memory is being executed; comprising means for storing all constituent instruction sequences of the program loop in the cache memory according to a detection result, and second detection means for detecting the end of processing of the program loop,
A cache memory control method characterized in that the instruction sequence constituting the program loop is not ejected from the cache memory until the end is detected by the second detection means. 2. An information processing device equipped with a cache memory, comprising: a first register for holding an instruction address of a branch instruction specifying a previous branch destination; and an address of the branch destination specified by the branch instruction. A second register for holding the above-mentioned first and second registers, and a second register for holding the above-mentioned first and second registers, and detecting that, when a branch of the above-mentioned branch instruction is established, the instruction sequence from the branch destination instruction to the same branch instruction is fully stored in the above-mentioned cache memory. By means of setting information in the second register and detecting the establishment of a branch of the branch instruction of the instruction address held in the first register, a program loop consisting of an instruction string that can be stored in the cache memory is configured. a first detecting means for detecting that the first detecting means is being executed;
According to the detection result of the detection means, all instruction strings from the instruction at the branch destination address held in the second register to the branch instruction at the instruction address held in the first register are stored in the cache memory. means for storing and detecting that the address of the instruction being executed exceeds the instruction address held in the first register;
a second detection means for detecting the end of the processing of the program loop, and prevents the constituent instruction sequence of the program loop from being evicted from the cache memory until the end is detected by the second detection means. A cache memory control method that is characterized by: 3. An information processing device equipped with a cache memory, comprising: a first register for holding an instruction address of a branch instruction specifying a previous branch destination; and an address of the branch destination specified by the branch instruction. a second register for holding the size of the instruction string from the instruction at the branch destination address specified by the branch instruction to the branch instruction, and a third register for holding the size of the instruction string from the instruction at the branch destination address specified by the branch instruction to the branch instruction, and the branch completion of the branch instruction. Sometimes, by detecting that the instruction string from the branch destination instruction to the branch instruction is completely stored in the cache memory, it is determined whether valid information is not set in the first to third registers or If the size indicated by the third register is smaller than the size of the instruction string from the instruction at the branch destination address specified by the branch instruction that took the branch to the same branch instruction, the information is transferred to the first to third registers. Detecting that a program loop consisting of an instruction sequence that can fit into the cache memory is being executed by detecting the execution of a branch instruction of the instruction address held in the first register and the setting means. and a first detection means for detecting a branch from the instruction at the branch destination address held in the second register to the instruction address held in the first register according to the detection result of the first detection means. The processing of the program loop is performed by storing the entire instruction sequence up to the instruction in the cache memory, and by detecting that the address of the instruction being executed exceeds the instruction address held in the first register. a second detection means for detecting the end, and the constituent instruction string of the program loop is not ejected from the cache memory until the end is detected by the second detection means. Cache memory control method. 4. The contents of the first and second registers are cleared in response to detection of completion of processing of the program loop by the second detection means. cache memory control method.