JPH0362143A - Cache-write-back control system - Google Patents

Abstract

PURPOSE:To execute cache-write-back at high speed by detecting and selecting simply data whose contents are different from that of the data in the corresponding area of a storage device from among the data in an objective block to be cache-written-back, and executing cache-write-back. CONSTITUTION:When the data of the same address of a cache memory 12 and a subcache memory 13 do not coincide with each other, read-out data from the memory 12 was re-written previously, and therefore, this data is different from the data of the corresponding address of main storage 11. Accordingly, control logic 15 executes operation to write the read-out data from the memory 12 to the main storage 11, and after that, it proceeds to the processing of the next address. Then, when the logic 15 executes this control operation for the objective block to be cache-written-back in the memory 12 and the block in the subcache memory 13, the data of the block in the main storage 11 corresponding to the address having turned into cache mishit is read out. Accordingly, the data whose contents are different from that of the data in the corresponding area of the storage device can be simply detected and selected.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a system that includes a cache memory in which a copy of the contents of a part of a storage device is placed and that applies a cache write hack method. In particular, the present invention relates to a cache write-back control method for efficiently performing cache write-back operations.

(Prior art) Computer systems in recent years are generally equipped with a cache memory in which a copy of the contents of a part of the main memory is stored. By obtaining data, upper memory 1
．． The main memory access (memory access) is made faster by eliminating the need for actual access to the second memory. Similarly, it is also known to provide a disk controller with a cache memory in which a copy of the contents of a portion of the disk device is placed, in order to speed up disk access. The cache memory provided in this disk controller is generally called a disk cache.

Now, as mentioned above, in a system equipped with a cache memory in which a copy of the contents of a part of the main memory or a storage device such as a disk device is stored, in order to further increase the processing speed, the CPU, etc. When a write access request is made, writing is performed only to the cache memory, and writing to the storage device is performed at different timings using data stored in the cache memory (at the time of a cache miss when the corresponding cache memory block is evicted, or A cache write-back method is generally applied, which is performed block by block (regularly). For example, in a method that performs cache write-back operation when there is a cache miss,
When a cache miss occurs, all the contents of the block to be evicted from the cache memory (cache block) are written back from the cache memory to the storage device. The block data will be read and stored in the eviction target block.

On the other hand, in a method that periodically performs cache write-back operations, each entry in a cache directory that manages cache memory block by block indicates whether or not the contents of the corresponding block need to be written back to the storage device. A flag is set. This write-back flag is turned on when data is written to a block in the cache memory in response to a write access request. The state of the write-back flag of each entry in the cache directory is checked periodically, and all contents of blocks for which the flag is on are written back to the storage device.

When this write-back is executed, the corresponding write-back flag is turned off.

(Problems to be Solved by the Invention) As described above, in conventional systems that apply the cache write-back method, all data in blocks in the cache memory that are subject to cache write-back are written back to the storage device. This write-back operation (cache write-back operation) takes a lot of time. However, the target block for cache writeback contains data that is the same as the data in the corresponding area of the storage device, and it would be wasteful to write even such data back to the storage device using cache writeback operations. there were.

This invention was made in view of the above circumstances, and its purpose is to selectively cache write back only data that is different from the data in the corresponding area of the storage device, out of the data in the target block of cache write back. An object of the present invention is to provide a cache write-back control method that can speed up cache write-back operations.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a system that is equipped with a cache memory in which a copy of a part of the contents of a storage device is placed, and that applies a cache write-back method. A sub-cache memory has a block area of Controls the reading of data lj of a predetermined length from the target block area in the cache memory and the block area in the sub-cache memory corresponding to the same area, and controls the writing of data read from the west block area of the cache memory to the storage device. and a comparison means for comparing both data read from the cache memory and the sub-cache memory under the read control of the control means to detect whether or not there is a match,
The present invention is characterized in that when data matching is detected by the comparison means, the control means omits the operation of writing the corresponding read data from the cache memory to the storage device. .

(Operation) According to the above configuration, when data is read from the storage device to the block area of the cache memory, the data is stored as is in the corresponding block area of the sub-cache memory. When a write access request is made from a CPU or the like, corresponding write data is written to the cache memory.

At this time, the operation of writing the write data to the corresponding area of the sub-cache memory is not performed. Furthermore, since the cache buffer method is applied, the operation of writing the write data to the corresponding area of the storage device is not performed. Now, during a cache write-back operation in which data in the cache memory is written to the storage device, under the control of the control means, not only the block area in the cache memory that is the object of cache write-back but also the block area in the sub-cache memory corresponding to the same area are Reading is performed in data units of a predetermined length. Both data read from the cache memory and the sub-cache memory are compared by a comparing means to detect whether or not they match. If the data read from the cache memory has been rewritten at the time of a write access request, the comparison means will detect a mismatch, and if the data has not been rewritten, a match will be detected. The comparison result of this comparison means (detection result of presence or absence of a match) is notified to the control means. When the comparison means detects a match H during the cache write hack operation, the control means assumes that the data read from the cache memory at that time is the same as the data in the corresponding area of the storage device, and performs the above-mentioned process. The operation of writing the read data to the corresponding area of the storage device is omitted, and the read data from the cache memory at that time is written to the corresponding area of the storage device only when a comparison means detects no match. As a result of the above, among the data in the block area in the cache memory that is subject to cache writeback, only the data that has been rewritten at the time of a write access request and whose content differs from the corresponding data in the storage device is selectively written back to the storage device. Compared to the conventional method in which all data in a block area is unconditionally written back to the storage device, cache write-back operations can be performed faster.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a computer system to which the present invention is applied. In the figure, 11 is a storage device in which various program data, general data, etc. are stored, such as main memory, 12 is a cache memory in which a copy of a part of the main memory 11 is placed at the block tit position, and 13 is a cache memory 12. Same number of blocks (block area)
It is a sub-cache memory with When data (block data) in the main memory 11 is read to the cache memory 121N block, the sub cache memory 18 transfers the block data to the same sub cache memory 121N block.
It is used to save as is in the corresponding block of 3.

14 constitutes the center of the system and accesses the main memory 11 via the cache memory 12; 15 indicates a block in the cache memory 12 that is subject to cache write back during cache write back operation and a sub cache corresponding to the block; In addition to controlling the reading of data units of a predetermined length from blocks in the memory 13,
A control logic controls writing of data read from a block in the cache memory 12 to the above-mentioned tall according to a comparison result of a comparator 17, which will be described later. 1B is a memory control line used for control of the above-mentioned tall by the control logic 15. It is. 17 is a comparator for comparing data read from the cache memory 12 and sub-cache memory 13 during cache write-back operation (under control of the control logic 15) and detecting whether or not they match; 18 is a comparator 17; This is a signal line for notifying the control logic 15 of the comparison result (detection result of the presence or absence of a match). Note that in FIG. 1, the directory memory for managing directory information in the cache memory 12 and the like are omitted because they are not directly related to the present invention.

Next, the operation of one embodiment of the present invention will be explained.

First, when the control logic 15 reads and writes block data in the main memory II to a corresponding block in the cache memory 12, it also writes the same block data to the corresponding block in the sub-cache memory 13. The CPU 14 is
When an access request is made to the queen tall, if block data corresponding to the access destination address exists in the cache memory 12, only the cache memory 12 is accessed at high speed. Therefore, when a cache hit occurs at the time of a write access request, write data is written only into the corresponding block of the cache memory 12.

At this time, since writing to the main memory 11 is not performed,
A mismatch occurs in the contents of corresponding blocks in the main memory 11 and cache memory 12, respectively. Therefore, a cache write-back operation is required to separately write back the data of the corresponding block in the cache memory 12 to the main memory 11. This operation is performed as follows when a cache miss occurs at the time of an access request from the CPU 14 and a block consisting of the cache memory 12 is evicted.

A cache miss occurs and the cache memory 12
When a block to be evicted in the block, that is, a block to be cached write-back is determined, the control logic 1
5 sequentially generates the addresses of the cache write-back target blocks and starts reading data in units of a predetermined length from the cache memory 12. This address is also given to the sub cache memory 13 at the same time. Thus, the control logic 15 executes reading from the same address of the sub-cache memory 13 as the cache memory 12 simultaneously with reading from the cache memory 12. Data read simultaneously from the same address in cache memory 12 and sub-cache memory 13 is supplied to comparator 17. Comparator 17 compares both data and determines whether or not both data match.

The comparison result of comparator 17 is supplied to control logic 15 via signal line 18. control logic 1
5, it is determined based on the state of the signal line 1B (whether or not the comparator 17 has determined that there is a match, that is, whether or not the data read from the cache memory 12 has been rewritten at the time of the write access request; Depending on the determination result) Queen T
Writing to all is controlled via the memory control line 16. That is, the control logic 15 determines that if the data at the same address in the cache memory 12 and the sub-cache memory 13 match, the data read from the cache memory 12 has not been rewritten, and therefore the same data and the data in the main memory 11 are the same. Since the data at the corresponding address has the same content, cache memory 1
The operation of writing the data read from No. 2 into the main memory 11 is omitted and the process proceeds to the next address. On the other hand, l of the cache memory 12 and sub-cache memory 13,
If the data at the jJ-address does not match, the data read from the cache memory 12 has been rewritten, and therefore the same data and the data at the main memory 11 The logic I5 executes an operation of writing read data from the cache memory 12 into the main memory 11, and then proceeds to process the next address.

The control logic 15 performs the above control operations on the cache write-back target block in the cache memory 12 and the sub-cache memory 1 corresponding to the same block.
When executed for all addresses in block 3, that is, when a series of cache write-back operations are completed, the main memory 11 corresponding to the address that caused the cache miss is
The data in the inner block is read and written to the inner block of the cache memory 12 and sub-cache memory 13, which have been read targets up to that point. At this time, if there is a cache miss at the time of a write access request, part of the data in the corresponding block of the cache memory 12 is rewritten to write data.

In the above embodiment, a case was explained in which a cache write-back operation is performed at the time of a cache miss. However, in the present invention, as described in the conventional example, a write-back flag is prepared corresponding to each block of the cache memory. The present invention can also be applied to a system that periodically checks the state of the flag and performs a cache write-back operation according to the check result. The present invention is also applicable to cache write-back operations in disk cache systems.

[Effects of the Invention] As detailed above, according to the present invention, among the data in the target block of cache writeback, data with different contents from the data in the corresponding area of the storage device can be easily detected and the same data can be easily detected. Since it is possible to selectively write back only the data in the cache, it is possible to significantly speed up the cache write back operation compared to the conventional method in which all the data in the target block of the cache write back is written back in the cache.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a computer system to which the present invention is applied. 11... Main memory (storage device), 12... Cache memory, 13... Sub cache memory, 14...
CPU, 15...control logic (control means)
, 17... Comparator.

Claims (1)

[Scope of Claims] A system that includes a cache memory in which a copy of the contents of a part of the storage device is placed and applies a cache write-back method, which has the same number of block areas as the cache memory, and has the same number of block areas as the cache memory; A sub-cache memory for storing data in the corresponding block area when data is read into a block area of the cache memory, and a sub-cache memory for storing the data in the corresponding block area when the data is read into a block area of the cache memory, and a sub-cache memory for storing the data in the corresponding block area in the cache memory and the same block area in the cache memory that is subject to cache write-back during cache write-back operation. a control means for controlling the reading of data units of a predetermined length from the block area in the sub-cache memory corresponding to the area, and controlling the writing of data read from the block area in the cache memory to the storage device; Comparing the data read from the cache memory and the sub-cache memory by the read control of the means to detect whether or not there is a match, and depending on the detection result, whether or not it is necessary for the control means to write the data to the storage device. a comparison means for notifying whether the data read from the cache memory and the sub-cache memory match, and when the comparison means detects that both data read from the cache memory and the sub-cache memory match, 1. A cache write-back control system, characterized in that an operation of writing data read from the storage device into the storage device is omitted under the control of the control means.