JPH031249A - Buffer memory device - Google Patents

Abstract

PURPOSE:To simplify the update processing of a buffer memory by performing the write of block load data on the buffer memory and the registration of block address information and the change of an effective display flag bit with the same timing when a block load processing is performed. CONSTITUTION:When the block load processing is started and coincidence is obtained between the block address information and rewrite address information or an error occurs in the block load data while performing the block load processing, the reset of the effective display bit is performed, and also, neither registration nor update of the block address information are performed. Also, when noncoincidence is obtained between the block address information and the rewrite address information and no error occurs in the block load data, the update of the buffer memory 11 and a directory memory 12 and the reset of the effective flag bit are performed after the entry generation of the block load data is completed. In such a way, it is possible to simplify the processing by attaining the unitary management of the update processing of the buffer memory 11, and to perform efficiently the update processing.

Description

Detailed Description of the Invention Object of the Invention (Industrial Field of Application) The present invention relates to a buffer memory device that stores and holds a copy of the contents of a main memory, and in particular to an efficient update process in block load processing. This relates to the buffer memory IF performed.

(Prior Art) There is a buffer memory device used in computer systems, etc., which is configured as shown in FIG. 4, for example.

In the buffer memory device shown in FIG. 4, the buffer memory 11, which forms the center of the device, has a four-level set associative memory structure, and stores block data of a part of the main memory (not shown). is stored. The directory memory 12 provided corresponding to this buffer memory 11 contains address information (on the main storage device) of the program data stored in the barafun memory 11
block address) is registered corresponding to the block data.

In addition, in order to match the data stored in the main storage device and the buffer memory 11, a display flag memory is provided with a valid display flag bit (■) indicating whether or not the data stored in the buffer memory 11 is valid. 13 are provided. This valid display flag bit V is reset when the data stored in the main storage device and the buffer memory 11 do not match.

In other words, such a Balanoa memory device can be used as a multi-C
When used in a PU system or a system having many I10 devices, requests to the main storage device from the main CPU or I10 devices are monitored. In such a monitoring state, if a rewrite request occurs, the rewritten address on the main memory is retrieved and a search is performed using this address information. If the data corresponding to the address information is stored in the buffer memory 11, the valid display flag bit V is reset.This invalidates the data rewritten in the main storage device in the buffer memory 11. In order to match the contents of the main memory and buffer memory, the valid display flag bit ■
is used.

In such a configuration, when the CPU accesses the main memory, a memory address is given to the address register 14 and held there.

Among the retained memory addresses, column address part 1
Each level of directory memory 12 is accessed by 4fl. The block address read out from the directory memory 12 for each level is given to the corresponding comparator 15 and compared with the block address section 14a of the address register 14 for each level.

If there is a match in the comparison results, it is determined that the data accessed by the CPU to the main storage device exists in the buffer memory 11 (hit).

In such a case, the column address section 1 of the address register 14 is controlled by the buffer memory control circuit 16.
The data to be accessed is read from the address of the buffer memory 11 indicated by 411 and the intra-block address section 14C.

On the other hand, if there is no match in the comparison result, it is determined that the data to be accessed does not exist in the buffer memory 11 (mishit). In such a case, a series of processing called block load processing is performed.

Hereinafter, the block loading process will be explained with reference to FIG.

When the directory memory 12 is searched and there is a miss, a request is made to read data from the main storage device using the block address where the miss occurred. In parallel with this, the block address recorded as 0 in the address of the directory memory 12 corresponding to the 7th address of the buffer memory 11 in which the data read from the main memory is stored is replaced with the block address of the miss. Updated. Further, a valid display flag bit V corresponding to the updated block address is set. after that,
The block data read from the main storage device is sequentially written and stored in the buffer memory 11, and the block 0-read processing is completed.

In such a block load process, after a block data read request is made, if the buffer memory device is not receiving data from the main device, -
It is possible to reset the valid indication flag bit V once set. In a split control type system bus, this is due to the buffer 7 mechanism [Qtf
This is particularly effective when fi is used.

(Problems to be Solved by the Invention) As described above, in the conventional buffer memory device, in the block load process, the block data is stored in the buffer due to the rewriting of the 70 block addresses and the setting of the valid display flag bit. It was stored in memory.

In such block [1-code processing, block 1
] - An error may occur in the read data. For example, a parity error occurs during data bus transfer, a page is absent when the system bus is configured with virtual addresses, or a parity error occurs in the main memory. If such an error is detected in the block-loaded data, the valid indication flag bit V, which was previously set corresponding to the loaded data, must be reset.

As described above, conventionally, the valid display pins 1 to 1 are set/reset at two timings τ. As a result, the updating process of the buffer memory becomes complicated and inefficient.

Therefore, the present invention has been made in view of the above, and its purpose is to simplify the process by unifying the update process of buffer candy and to efficiently perform the update process. An object of the present invention is to provide a buffer memory device.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a buffer memory in which a copy of the contents of the main storage device is stored and block address information corresponding to the contents of the buffer memory are provided. a registered directory memory, and performs block load processing when a copy of the main storage device is not stored in the buffer memory, updates the buffer memory and the directory memory, and displays validity corresponding to block address information. In a buffer memory device that sets flag bits, the present invention includes a detecting means for detecting whether block address information during block load processing and blue rewriting address information during main memory capacity rewriting match; control means for resetting a valid display flag bit and prohibiting the block address information from being registered in the directory memory when a match is detected by the detection means or an error in the block load data; configured.

(Operation) In the above configuration, the present invention is effective when block load processing is started and block address information and rewrite address information match during block load processing, or when an error occurs in block load data. The display flag bit is reset and block address information is not updated. In addition, if the block address information and rewrite address information do not match and no error occurs in the block load data, update the buffer memory and directory memory and set the valid display flag bit after completing the block load data entry creation. I try to do this.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of a buffer memory device according to an embodiment of the present invention. In the device shown in the figure, the validity display flag bit V is set at the time of loading the final data of the block loaded data. ,
Note that in FIG. 1, components having the same reference numerals as those in FIG. 4 have the same functions, and their explanations will be omitted.

In FIG. 1, the buffer memory device differs from the conventional pack-a-memory device shown in FIG. 27 is added.

The address selection circuit 21 includes an address register that holds a memory address for a CPU (not shown) to access a main memory (not shown). The address selection circuit 21 selects the memory address held in the address register and the CPLJ or I10 other than the main CPU.
Select old address information when a device other than the main CPLI, such as a device, rewrites the main storage device. The address selection circuit 21 is initiated by the CPU! ! When a device is accessed, a memory address is selected, and when the main storage device is rewritten by another device, rewrite address information is selected. The selected memory address is
The block address portion 21a is provided to the block load address register 23 and address comparator 15. In addition, the column address part 21b of the memory address is
The information is applied to the directory memory 12 and searched.

The block load address register 23 receives and holds the block load address selected by the address selection circuit 21 and held in the block address section 21a of the address register.

The retained block load address is sent to address comparator 2.
given to 5.

The address comparator 25 receives the block load address held in the block load address register 23 and the old address information selected by the address selection circuit 21 and compares the rain sound.

That is, the address comparator 25 detects whether the rewrite address information of the main storage device is the block load address of the block load process when the matching R function by bus monitoring is activated during the block load process. . The address comparator 25 provides a match signal to the control circuit 27 when the cleaning address information and the block load address match as a result of the comparison.

The control circuit 27 controls the setting/resetting of the valid display flag bit V provided in the display flag memory 13 and the writing of address information corresponding to block loaded block data into the directory memory 12.

As shown in FIG. 2, the control circuit 27 includes a flip 70 tube (hereinafter referred to as rF/FJ) circuit 31 and an OR circuit.
It consists of a gate 33 and an audience control circuit 35.

The F/F circuit 31 is set by a start signal indicating that block load processing has started, and the OR gate 33
It is reset by the output of When set, the F/F circuit 31 outputs a command signal that commands the setting of the valid display flag bit V and also commands the loading of block load address information into the directory memory 12.

The OR gate 33 takes the logical sum of the match signal given from the address comparator 25, the detection signal, and the end signal, and
/F circuit 31 is reset. The detection signal is a signal indicating that an error has been detected in block loaded data. The end signal is block road!
2! This is a signal indicating that the process has been completed and the entry creation has ended.

The obsolete control circuit 35 sets the load movement display flag bit V corresponding to the block load address in response to the command signal output from the F/F circuit 31. Further, the loading control circuit 35 controls loading of the address information held in the block address section 21 of the address register of the address selection circuit 21 into the direct memory 12.

As explained above, one embodiment of the present invention is constructed, and the operation of this embodiment will now be explained with reference to the timing chart shown in FIG.

When the directory memory 12 is searched and there is a miss, a start signal for starting block load processing is output, and block 1 code processing is started. The start signal is given to the F/F circuit 31. The F/F circuit 31 is in a critical state because the completion signal is not applied to the OR gate 33 until the creation of an entry for the block data read from the main memory is completed. As a result, the command signal is not output from the F/F circuit 31 to the rewriting control circuit. Therefore, even if block load processing is started, the valid display flag bit V is not set and the address information corresponding to the block data is not written.

When block load processing is started and an error is detected in the data read from the main memory, a detection signal indicating the detection of an error is provided to OR gate 33. As a result, the F/F circuit 31 enters a reset state. In other words, even if all the data read from the main 2vi device is stored in the buffer memory 11 and entry creation is completed and the end signal is given to the F/F circuit 31, the F/F circuit 31 does not receive the detection signal. The reset state is maintained by

Therefore, even during block load processing, if an error occurs in the data read from the main memory, the valid display flag bit V is not set and tl is not written into the directory memory 12.

Further, when block load processing is started and the matching function based on bus monitoring is activated, the block load address held in the block load address register 23 and the replacement address information selected by the address selection circuit 21 are The signal is applied to a comparator 25 for comparison.

As a result of the comparison, if the block load address and the review address information match, it is determined that the block load address of the main storage device is to be rewritten from another device, and a match signal is given to the OR gate 33. .

As a result, the F/F circuit 31 enters a reset state. That is, even if the end signal is given to the F/F circuit 31, the F/F circuit 31
The /F circuit 31 is held in a reset state by the match signal. Therefore, when the main memory is rewritten to the block load address, the block data read from the main memory becomes invalid, so the valid display flag bit V is set and the directory memory 1
Fortune-telling to 2 is not performed.

On the other hand, when the block load processing is completed without the coincidence signal and the detection signal being given to the OR gate 33 and the completion signal is given to the OR gate 33, the F/F circuit 31 is placed in a set state by the start signal. As a result, a command signal is given to the rewrite control circuit 35, and 2) the rewrite control circuit 35 writes address information corresponding to the block data to the directory memory 12, and also corresponds to the address information written to the directory memory 12. The valid display flag bit V is set.

Therefore, in the block load process, the loaded block data is transferred to the barafunz memory 11, the address information corresponding to the block data is stored in the block data memory 12, and the valid display flag corresponding to the address information is stored. Bit V is set at the same timing.

[Effects of the Invention] As explained above, according to the buffer memory device to which the present invention is applied, during block load processing, block load data is occupied in the buffer memory, block address information is registered, and a valid display flag bit is set. changes can be made at the same timing. This centralizes and simplifies the buffer memory update process, allowing you to update! 2! This makes it possible to effectively perform burying.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a buffer memory device according to an embodiment of the present invention, FIG. 2 is a diagram that does not show the main part configuration of the device shown in FIG. 1, and FIG. 3 is the same as shown in FIG. 1. FIG. 4 is a block diagram showing one configuration of a conventional buffer memory device, and FIG. 5 is a timing chart of a device not shown in FIG. 4. 11...Buffer memory 12...Directory memory 13...Display flag memory 21...Address selection circuit 23...Block load address register 25...
Address comparator 27...Control circuit 31...F/F circuit 33...OR gate 35...Rewriting control circuit Agent Patent attorney Hide Miyoshi Mishit start signal Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] A buffer memory in which a copy of the contents of the main storage device is stored, and a directory memory in which block address information corresponding to the contents of the buffer memory is registered; In a buffer memory device that performs a block load process when the block address information is not stored in the buffer memory, updates the buffer memory and the directory memory, and sets a valid display flag bit corresponding to block address information. a detection means for detecting whether the block address information and the rewrite address information when rewriting the main memory device match; and a detection means for detecting whether a match is detected by the detection means or an error in block load data is detected. A buffer memory device comprising: control means for resetting a valid display flag bit and prohibiting the block address information from being registered in the directory memory when the block address information is registered in the directory memory.