JPH04329694A - Corrosion proof structure on soldering connection - Google Patents
Corrosion proof structure on soldering connectionInfo
- Publication number
- JPH04329694A JPH04329694A JP3099920A JP9992091A JPH04329694A JP H04329694 A JPH04329694 A JP H04329694A JP 3099920 A JP3099920 A JP 3099920A JP 9992091 A JP9992091 A JP 9992091A JP H04329694 A JPH04329694 A JP H04329694A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- corrosion
- base metal
- solder joint
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005260 corrosion Methods 0.000 title claims abstract description 21
- 230000007797 corrosion Effects 0.000 title abstract description 18
- 238000005476 soldering Methods 0.000 title abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000010953 base metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000007789 sealing Methods 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 abstract description 23
- 239000007769 metal material Substances 0.000 abstract 1
- 239000008188 pellet Substances 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 229910052725 zinc Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000010970 precious metal Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005536 corrosion prevention Methods 0.000 description 1
- 230000006353 environmental stress Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000008407 joint function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Prevention Of Electric Corrosion (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置などのはんだ
付け部を防食する技術、特に、リードやバンプのはんだ
接続部あるいは封止部の腐食防止に用いて効果のある技
術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for preventing corrosion of soldered parts of semiconductor devices, and particularly to a technique effective for preventing corrosion of soldered joints or sealing parts of leads and bumps.
【０００２】0002
【従来の技術】従来、例えば表面実装型の半導体装置を
基板などへ実装する場合、基板の配線パターン上に半導
体装置のリードを位置合わせして載置し、はんだ付けに
より電気的接続及び機械的固定を行っている。[Prior Art] Conventionally, when mounting a surface-mounted semiconductor device on a board, for example, the leads of the semiconductor device are aligned and placed on the wiring pattern of the board, and electrical connections and mechanical connections are made by soldering. It is fixed.
【０００３】なお、この種の技術については、例えば、
応用技術出版株式会社発行「表面実装型ＬＳＩパッケー
ジの実装技術とその信頼性向上」３３３〜３４３頁に記
載がある。また、フリップチップ技術に関しては、総研
出版株式会社、１９８５年発行「超ＬＳＩテクノロジー
」６０５〜６１０頁に記載がある。[0003] Regarding this type of technology, for example,
It is described in ``Surface-mounted LSI package mounting technology and its reliability improvement'' published by Applied Technology Publishing Co., Ltd., pages 333-343. Further, flip-chip technology is described in "Very LSI Technology" published by Souken Publishing Co., Ltd. in 1985, pages 605-610.
【０００４】0004
【発明が解決しようとする課題】ところが、上記公報に
記載された従来技術には、以下の問題のあることを本発
明者は見い出した。However, the present inventor has found that the prior art described in the above publication has the following problems.
【０００５】すなわち、錫（Ｓｎ ）を含まないはんだ
材を用い、かつリード間隔を狭くした場合、はんだ量が
少なくなる（リード幅が小さく、接触面積が少なくなる
ため）ために、はんだ付け部が環境ストレスによって腐
食の影響を受け易くなる。この腐食によってはんだ付け
部が劣化し、これが破断に到り、電極部での電気的な導
通不良、封止部での気密不良などを招くという問題があ
る。また、電極間への導電性腐食生成物の析出によって
、電流リークを生じ、信頼性を低下させるという問題も
あった。[0005] That is, when a solder material that does not contain tin (Sn) is used and the lead spacing is narrowed, the amount of solder is reduced (because the lead width is small and the contact area is small), so the soldered part is Environmental stress increases susceptibility to corrosion. This corrosion causes the soldered portion to deteriorate, leading to breakage, resulting in problems such as poor electrical continuity at the electrode portion and poor airtightness at the sealing portion. Furthermore, there is also the problem that conductive corrosion products are deposited between the electrodes, causing current leakage and reducing reliability.
【０００６】そこで、本発明の目的は、はんだ付け部に
腐食を生じないようにし、はんだ付け部の信頼性を向上
させることのできる技術を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a technique that can prevent corrosion of the soldered portion and improve the reliability of the soldered portion.
【０００７】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
【０００８】[0008]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.
【０００９】すなわち、表面実装型の半導体装置のリー
ドと基板などのプリント部とが接続されるはんだ接続部
であって、該はんだ接続部のはんだの組成金属に対し、
卑金属を電気的に接触させるようにしている。That is, in a solder joint where a lead of a surface-mounted semiconductor device is connected to a printed part of a board, etc., the metal composition of the solder of the solder joint is
Base metals are brought into electrical contact.
【００１０】0010
【作用】上記した手段によれば、はんだ接続部に電気的
に接触している卑金属は、ガルバノ電池作用によって犠
牲陽極として機能し、はんだ接続部のはんだ又ははんだ
バンプが陰極防食され、はんだ又ははんだバンプの腐食
を防止する。したがって、はんだ接続部が防食され、は
んだ接続部の高信頼化を図ることができる。[Operation] According to the above-mentioned means, the base metal that is in electrical contact with the solder joint functions as a sacrificial anode by the action of a galvano cell, and the solder or solder bump of the solder joint is cathodic protected, and the solder or solder bump is cathodic protected. Prevent bump corrosion. Therefore, the solder joints are protected from corrosion, and the reliability of the solder joints can be improved.
【００１１】[0011]
【実施例１】図１は本発明によるはんだ接続部の防食構
造の一実施例を示す断面図である。Embodiment 1 FIG. 1 is a cross-sectional view showing an embodiment of the anti-corrosion structure for solder joints according to the present invention.
【００１２】ここでは、例えば、ＱＦＰ，ＳＯＰ等のＦ
ＰＰ型の半導体装置を配線基板に実装する場合を示して
いる。[0012] Here, for example, F of QFP, SOP, etc.
This shows a case where a PP type semiconductor device is mounted on a wiring board.
【００１３】半導体装置１は、ダイパッド２上に配設さ
れた半導体チップ３のパッドとリード４のインナーリー
ド部、及びパッドとインナーリード部とを接続するボン
ディングワイヤ５の各々がレジン６によってモールドさ
れた構成を有している。レジン６の側面より突出してい
るリード４のアウターリード部は、Ｌ字形に曲げ加工が
施され、その端部はレジン６の底面に平行になるように
されている。リード４の端部は、配線基板７の表面に形
成されたフットプリント８に、はんだ９を介して接続さ
れている。以上は従来構成に相当する部分であるが、こ
れに対し本発明は、はんだ接続部の防食のために、はん
だ９の周囲（又は少なくともその一部）のフットプリン
ト８上に保護膜１０を電気的に接続している。In the semiconductor device 1, the pads of the semiconductor chip 3 disposed on the die pad 2, the inner lead portions of the leads 4, and the bonding wires 5 connecting the pads and the inner lead portions are each molded with resin 6. It has a similar configuration. The outer lead portion of the lead 4 protruding from the side surface of the resin 6 is bent into an L shape, and its end portion is parallel to the bottom surface of the resin 6. The ends of the leads 4 are connected to footprints 8 formed on the surface of the wiring board 7 via solder 9. The above is a part corresponding to the conventional structure, but in contrast, the present invention electrically coats the protective film 10 on the footprint 8 around the solder 9 (or at least a part thereof) in order to prevent corrosion of the solder joint. connected.
【００１４】この保護膜１０は、はんだ９の組成金属よ
りも卑金属な金属が用いられる。例えば、常温水中にお
ける金属の卑金属と貴金属は次のような関係にある。This protective film 10 is made of a metal that is more base metal than the metal composition of the solder 9. For example, the relationship between base metals and precious metals in water at room temperature is as follows.
【００１５】
卑金属←
→貴
金属 Ｋ Ｃａ Ｎａ Ｍｇ Ａｌ
Ｚｎ Ｆｅ Ｎｉ Ｓｎ Ｐｂ Ｈ Ｃ
ｕ Ｈｇ Ａｇ Ｐｔ Ａｕ （陽極
）
（陰極
）卑金属と貴金属は離れるほど効果は顕著になるが、例
えばはんだ９にＰｂや銀Ａｇを含む場合、保護膜１０に
はＮｉ、Ｚｎなどを用いることが生産性の点からも好ま
しい。このような組み合わせにより、ガルバノ電池作用
によって卑金属側であるＮｉ、Ｚｎが陽極として機能し
、はんだ９が陰極として機能し、陰極を防食する。0015 Base metal←
→Precious metals K Ca Na Mg Al
Zn Fe Ni Sn Pb H C
u Hg Ag Pt Au (Anode)
(Cathode) The effect becomes more pronounced as the distance between the base metal and the noble metal increases. For example, when the solder 9 contains Pb or silver Ag, it is preferable to use Ni, Zn, etc. for the protective film 10 from the viewpoint of productivity. With such a combination, Ni and Zn on the base metal side function as an anode due to galvano cell action, and the solder 9 functions as a cathode, thereby protecting the cathode from corrosion.
【００１６】なお、図１の構成では、保護膜１０をはん
だ９の周辺にのみ設けるものとしたが、図２に示す如く
、はんだ９の接続面の下面を覆うように形成することも
できる。この構成では保護膜１０の形成は、図１の実施
例に比べて容易であるので、量産性は向上する。In the configuration shown in FIG. 1, the protective film 10 is provided only around the solder 9, but it can also be formed to cover the lower surface of the connection surface of the solder 9, as shown in FIG. With this configuration, the formation of the protective film 10 is easier than in the embodiment shown in FIG. 1, so mass productivity is improved.
【００１７】[0017]
【実施例２】図３は本発明の実施例２を示す断面図であ
る。本実施例においては、前記実施例とは同一であるも
のには同一引用数字を用いたので、以下においては重複
する説明を省略する。Embodiment 2 FIG. 3 is a sectional view showing Embodiment 2 of the present invention. In this embodiment, the same reference numerals are used for the same parts as in the previous embodiment, and therefore, redundant explanation will be omitted below.
【００１８】本実施例は、接続部以外のリード４の外表
面に保護膜１０を設けるようにしたところに特徴がある
。このように、はんだ９と保護膜１０が直接的に接して
いなくとも、電気的な導通の得られる金属（この場合、
リード４の先端部）であれば間接的であっても問題はな
い。この実施例では、保護膜１０が半導体装置側に設け
られることから、半導体メーカ側で加工できる利点があ
る。This embodiment is characterized in that a protective film 10 is provided on the outer surface of the lead 4 other than the connecting portion. In this way, even if the solder 9 and the protective film 10 are not in direct contact, a metal (in this case,
There is no problem even if it is indirect as long as it is the tip of the lead 4). In this embodiment, since the protective film 10 is provided on the semiconductor device side, there is an advantage that it can be processed by the semiconductor manufacturer.
【００１９】[0019]
【実施例３】図４は本発明の実施例３を示す断面図であ
る。本実施例においても、前記各実施例と同一であるも
のには同一引用数字を用いたので、以下においては重複
する説明を省略する。Embodiment 3 FIG. 4 is a sectional view showing Embodiment 3 of the present invention. In this embodiment as well, the same reference numerals are used for the same parts as in each of the above embodiments, and therefore, redundant explanation will be omitted below.
【００２０】本実施例は、接続部の全表面（リード先端
及びはんだ９の各露出面）に保護膜１０を設けるように
したものである。この構成では、はんだ９の露出面が保
護膜１０によって直接に覆われるので、ガルバノ電池作
用による防食効果に対し、更に防食効果は高くなる。In this embodiment, a protective film 10 is provided on the entire surface of the connection part (the lead tip and each exposed surface of the solder 9). In this configuration, the exposed surface of the solder 9 is directly covered with the protective film 10, so that the corrosion prevention effect is even higher than that due to the galvano cell action.
【００２１】[0021]
【実施例４】図５は本発明の実施例４を示す断面図であ
る。本実施例においても、前記各実施例と同一であるも
のには同一引用数字を用いている。Embodiment 4 FIG. 5 is a sectional view showing Embodiment 4 of the present invention. In this embodiment as well, the same reference numerals are used for the same parts as in each of the above embodiments.
【００２２】ここでは、半導体装置としてフリップチッ
プ型を示している。この半導体装置は、半導体ペレット
１１にはんだバンプ１２を設けて構成されている。はん
だバンプ１２は、下地金属層１３を介して半導体ペレッ
ト１１に接続されている。このような半導体装置は、配
線基板７上の形成された下地金属層１４にはんだ接続さ
れる。この下地金属層１４の露出面に対し、保護膜１０
が設けられる。はんだバンプ１２がＰｂ−Ｓｎ系の場合
、保護膜１０にＮｉ、Ｚｎなどを用いれば、ガルバノ電
池作用により保護膜１０自身が陽極となり、はんだバン
プ１２を陰極防食する。以上により、はんだバンプ１２
の腐食を防止できるので、マイクロ接続部の高信頼化を
図ることが可能になる。Here, a flip-chip type semiconductor device is shown. This semiconductor device is constructed by providing solder bumps 12 on a semiconductor pellet 11. Solder bump 12 is connected to semiconductor pellet 11 via underlying metal layer 13 . Such a semiconductor device is soldered to a base metal layer 14 formed on the wiring board 7. Protective film 10 is applied to the exposed surface of base metal layer 14.
is provided. When the solder bumps 12 are made of Pb-Sn, if Ni, Zn, or the like is used for the protective film 10, the protective film 10 itself becomes an anode due to galvano cell action, and the solder bumps 12 are protected from cathodic corrosion. With the above, the solder bump 12
Since corrosion can be prevented, it is possible to improve the reliability of micro-connections.
【００２３】[0023]
【実施例５】図６は本発明の実施例５を示す断面図であ
る。本実施例においては、図５の実施例と同一であるも
のには同一引用数字を用いているので、ここでは説明を
省略する。Embodiment 5 FIG. 6 is a sectional view showing Embodiment 5 of the present invention. In this embodiment, the same reference numerals are used for the same parts as in the embodiment of FIG. 5, so the explanation will be omitted here.
【００２４】本実施例は、前記実施例が保護膜１０を下
地金属層１４上に設けていたのに対し、はんだバンプ１
２の露出面に保護膜１０を設けたところに特徴がある。
このようにすれば、配線基板７側及び半導体ペレット１
１側に設ける必要がなくなり、高密度実装化に対応する
ことができる。In this embodiment, the protective film 10 was provided on the base metal layer 14 in the previous embodiment, whereas the solder bump 1 was provided on the base metal layer 14.
The feature is that a protective film 10 is provided on the exposed surface of 2. In this way, the wiring board 7 side and the semiconductor pellet 1
There is no need to provide it on the first side, making it possible to support high-density packaging.
【００２５】[0025]
【実施例６】図７は本発明の実施例６を示す断面図であ
る。Embodiment 6 FIG. 7 is a sectional view showing Embodiment 6 of the present invention.
【００２６】本実施例はハーメチック型のＭＣＣ（マイ
クロ・チップ・キャリア）半導体装置の例である。This embodiment is an example of a hermetic type MCC (micro chip carrier) semiconductor device.
【００２７】図５に示した構造の半導体ペレット１１は
、その上面（放熱面）が“コ”の字形断面形状を有する
キャップ１５の内面のメタライズ１８ａに熱伝導はんだ
１６によって接続され、はんだバンプ１２はベース１７
（絶縁材が用いられると共に内部に上下方向に配線パタ
ーンが形成されている）上のパターン電極に接続されて
いる。キャップ１５及びベース１７の周縁部の各対向面
にはメタライズ１８ｂが施され、対向する周縁部のメタ
ライズ１８ｂ間は半導体ペレット１１を密封するために
封止はんだ１９によって接続されている。The semiconductor pellet 11 having the structure shown in FIG. 5 has its upper surface (heat dissipation surface) connected to the metallization 18a on the inner surface of the cap 15 having a "U"-shaped cross section by means of heat conductive solder 16, and solder bumps 12 is base 17
It is connected to the upper pattern electrode (an insulating material is used and a wiring pattern is formed inside in the vertical direction). Metallization 18b is applied to opposing surfaces of the peripheral edges of the cap 15 and the base 17, and the metallization 18b on the opposing peripheral edges are connected by a sealing solder 19 to seal the semiconductor pellet 11.
【００２８】このような構造の半導体装置にあって、保
護膜１０は封止部の上下又は一方の外側面に施される。
例えば、封止はんだ１９がＰｂ−Ａｇ系である場合、保
護膜１０にはＳｎ、Ｎｉ、Ｚｎなどを用いることで、ガ
ルバノ電池作用により、保護膜１０自身を陽極とし、封
止はんだ１９を陰極防食とすることができる。In the semiconductor device having such a structure, the protective film 10 is applied to the upper and lower sides of the sealing portion or to one of the outer surfaces. For example, when the sealing solder 19 is Pb-Ag-based, by using Sn, Ni, Zn, etc. for the protective film 10, the protective film 10 itself becomes an anode and the sealing solder 19 becomes a cathode due to galvano cell action. It can be used as corrosion protection.
【００２９】[0029]
【実施例７】図８は本発明の実施例７を示す断面図であ
る。Embodiment 7 FIG. 8 is a sectional view showing Embodiment 7 of the present invention.
【００３０】本実施例は、図７の実施例と対象を同じに
するものであるが、保護膜１０の設置部分を異ならせた
ところに特徴がある。すなわち、封止部を覆うように保
護膜１０を設け、図６の実施例と同様に、封止はんだ１
９の防食効果に加え、キャップ１５及びベース１７の外
側面に保護膜１０のための領域を確保する必要が無くな
るので、パッケージの薄型化が可能になる。This embodiment has the same object as the embodiment shown in FIG. 7, but is characterized in that the portion where the protective film 10 is installed is different. That is, the protective film 10 is provided so as to cover the sealing portion, and the sealing solder 1 is provided as in the embodiment shown in FIG.
In addition to the anticorrosive effect of 9, it is no longer necessary to secure an area for the protective film 10 on the outer surfaces of the cap 15 and the base 17, so that the package can be made thinner.
【００３１】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。[0031] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.
【００３２】例えば、上記実施例の内の複数の組み合わ
せとすることも可能である。For example, it is also possible to combine a plurality of the above embodiments.
【００３３】[0033]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記の通りである。[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.
【００３４】すなわち、表面実装型の半導体装置のリー
ドと基板などのプリント部とが接続されるはんだ接続部
であって、該はんだ接続部のはんだの組成金属に対し、
卑金属を電気的に接触させるようにしたので、はんだ接
続部が防食され、はんだ接続部の高信頼化を図ることが
できる。That is, in a solder joint where a lead of a surface-mounted semiconductor device is connected to a printed part of a board, etc., the composition metal of the solder of the solder joint is
Since the base metals are brought into electrical contact, the solder joints are protected from corrosion and the reliability of the solder joints can be improved.
【図１】本発明によるはんだ接続部の防食構造の一実施
例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a corrosion-proof structure for a solder joint according to the present invention.
【図２】図１の実施例の変形例を示す断面図である。FIG. 2 is a sectional view showing a modification of the embodiment of FIG. 1;
【図３】本発明の実施例２を示す断面図である。FIG. 3 is a sectional view showing a second embodiment of the present invention.
【図４】本発明の実施例３を示す断面図である。FIG. 4 is a sectional view showing a third embodiment of the present invention.
【図５】本発明の実施例４を示す断面図である。FIG. 5 is a sectional view showing a fourth embodiment of the present invention.
【図６】本発明の実施例５を示す断面図である。FIG. 6 is a sectional view showing Example 5 of the present invention.
【図７】本発明の実施例６を示す断面図である。FIG. 7 is a sectional view showing a sixth embodiment of the present invention.
【図８】本発明の実施例７を示す断面図である。FIG. 8 is a sectional view showing Example 7 of the present invention.
１ 半導体装置 ２ ダイパッド ３ 半導体チップ ４ リード ５ ボンディングワイヤ ６ レジン ７ 配線基板 ８ フットプリント ９ はんだ １０ 保護膜 １１ 半導体ペレット １２ はんだバンプ １３ 下地金属層 １４ 下地金属層 １５ キャップ １６ 熱伝導はんだ １７ ベース １８ａ メタライズ １８ｂ メタライズ １９ 封止はんだ 1 Semiconductor device 2 Die pad 3 Semiconductor chip 4 Lead 5 Bonding wire 6 Resin 7 Wiring board 8 Footprint 9 Solder 10 Protective film 11 Semiconductor pellet 12 Solder bump 13 Base metal layer 14 Base metal layer 15 Cap 16 Thermal conductive solder 17 Base 18a Metallization 18b Metallize 19 Sealing solder
Claims (6)
板などのプリント部とが接続されるはんだ接続部であっ
て、該はんだ接続部のはんだの組成金属に対し、卑金属
を電気的に接触させることを特徴とするはんだ接続部の
防食構造。1. A solder joint where a lead of a surface-mounted semiconductor device is connected to a printed part such as a board, wherein a base metal is brought into electrical contact with the metal composition of the solder of the solder joint. Anti-corrosion structure for solder joints.
表面又は前記プリント部の表面に設けたことを特徴とす
る請求項１記載のはんだ接続部の防食構造。2. The anticorrosion structure for a solder joint according to claim 1, wherein the base metal is provided on at least a surface of the lead or a surface of the printed portion.
ように設けることを特徴とする請求項１記載のはんだ接
続部の防食構造。3. The anti-corrosion structure for a solder joint according to claim 1, wherein the base metal is provided to cover the solder joint.
体装置のはんだバンプとベースの下地金属層とが接続さ
れるはんだ接続部であって、該はんだ接続部のはんだの
組成金属に対し、卑金属を電気的に接触させることを特
徴とするはんだ接続部の防食構造。4. A solder joint where a solder bump of a microchip carrier type semiconductor device is connected to a base metal layer of the base, wherein a base metal is electrically added to the composition metal of the solder of the solder joint. Corrosion-proof structure for solder joints, which is characterized by the fact that they are brought into contact with each other.
又は前記下地金属層の表面に設けたことを特徴とする請
求項４記載のはんだ接続部の防食構造。5. The anticorrosion structure for a solder joint according to claim 4, wherein the base metal is provided on the surface of the solder bump or the surface of the base metal layer.
り、その封止部のはんだの組成金属に対し、卑金属を電
気的に接触させることを特徴とする請求項４記載のはん
だ接続部の防食構造。6. The anticorrosion structure for a solder joint according to claim 4, wherein the semiconductor device is of a hermetic type, and a base metal is brought into electrical contact with a metal composition of the solder of the sealing part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3099920A JPH04329694A (en) | 1991-05-01 | 1991-05-01 | Corrosion proof structure on soldering connection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3099920A JPH04329694A (en) | 1991-05-01 | 1991-05-01 | Corrosion proof structure on soldering connection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04329694A true JPH04329694A (en) | 1992-11-18 |
Family
ID=14260211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3099920A Pending JPH04329694A (en) | 1991-05-01 | 1991-05-01 | Corrosion proof structure on soldering connection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04329694A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5590047A (en) * | 1993-08-05 | 1996-12-31 | Clarion Co., Ltd. | Information processing apparatus |
-
1991
- 1991-05-01 JP JP3099920A patent/JPH04329694A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5590047A (en) * | 1993-08-05 | 1996-12-31 | Clarion Co., Ltd. | Information processing apparatus |
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