JPH04329692A - Both side mounting type memory package - Google Patents
Both side mounting type memory packageInfo
- Publication number
- JPH04329692A JPH04329692A JP3126801A JP12680191A JPH04329692A JP H04329692 A JPH04329692 A JP H04329692A JP 3126801 A JP3126801 A JP 3126801A JP 12680191 A JP12680191 A JP 12680191A JP H04329692 A JPH04329692 A JP H04329692A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- double
- mounting type
- sided
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims abstract description 12
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、両面実装型メモリパッ
ケージに関し、特に、メモリICの配線性の向上を図っ
た両面実装型メモリパッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-sided memory package, and more particularly to a double-sided memory package that improves the wiring of a memory IC.
【0002】0002
【従来の技術】従来、例えば、図6および図7に示すよ
うに、両面実装型メモリパッケージは、プリント基板3
の表裏に互いに同一機能を有する接続ピンを有した一対
のメモリIC1をそれぞれ向かい合せて配線してある。2. Description of the Related Art Conventionally, for example, as shown in FIGS. 6 and 7, a double-sided mounting type memory package has a printed circuit board
A pair of memory ICs 1 each having connection pins having the same function on the front and back sides of the memory IC 1 are wired facing each other.
【0003】さらに、具体的に説明する。図6は両面実
装型メモリパッケージの表面図、図7はその裏面を表面
からみた透視図である。本図から明らかなように、メモ
リIC1のピンは、表裏面において、互いに鏡に写した
ような対称になることから、表面,裏面でそれぞれ別々
に、例えばメモリIC制御信号パターン5が引かれる。
すなわち、全く同機能のピンにパターンが2本存在する
ことになる。[0003] A more specific explanation will be provided. FIG. 6 is a front view of the double-sided mount type memory package, and FIG. 7 is a perspective view of the back side thereof viewed from the front side. As is clear from the figure, since the pins of the memory IC 1 are symmetrical to each other on the front and back surfaces, as if mirrored, for example, the memory IC control signal pattern 5 is drawn separately on the front and back surfaces. In other words, there are two patterns for pins with exactly the same function.
【0004】また、表面,裏面のいずれか一方において
パターンを引こうとすると、表面から裏面への貫通ホー
ル6が2つ必要となり、配線性が悪化する。なお、4は
メモリIC1とメモリIC制御信号5とを接続する引き
出し線である。Furthermore, when attempting to draw a pattern on either the front or back surface, two through holes 6 are required from the front surface to the back surface, resulting in poor wiring performance. Note that 4 is a lead line connecting the memory IC 1 and the memory IC control signal 5.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の両面実装型メモリパッケージにあっては、表裏
面に実装されるメモリICの入出力ピンの配置が同一の
ため、向かい合せで配線すると表裏では入出力ピン同士
が対応しなくなって離れてしまい、メモリICの共通ピ
ンの配線性が悪くなるという問題があった。[Problems to be Solved by the Invention] However, in the conventional double-sided memory package described above, the input/output pins of the memory ICs mounted on the front and back sides are the same, so if they are wired facing each other, However, there was a problem that the input/output pins no longer correspond to each other and are separated from each other, resulting in poor wiring of the common pins of the memory IC.
【0006】すなわち、上述した従来の技術では、両面
実装型メモリパッケージにおけるメモリICの共通制御
信号(アドレス等)はメモリICのピン配置の構成上、
表裏面に実装されるメモリICのピン位置にずれが生じ
、配線性の悪化を生じていた。That is, in the conventional technology described above, the common control signals (address, etc.) of the memory IC in the double-sided memory package are
Misalignment occurred in the pin positions of the memory ICs mounted on the front and back surfaces, resulting in poor wiring performance.
【0007】本発明は、上記の問題点にかんがみてなさ
れたもので、配線性の向上を図った両面実装型メモリパ
ッケージの提供を目的とする。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a double-sided mounting type memory package with improved wiring performance.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するため
本発明の両面実装型メモリパッケージは、プリント基板
の表裏に、互いに同一機能を有する接続ピンを有した表
側メモリICおよび裏側メモリICをそれぞれ向かい合
せて配線した両面実装型メモリパッケージにおいて、表
側メモリICの接続ピンと裏側メモリICの接続ピンと
を、上記向かい合わせた状態で同一機能を有するピン同
士が互いに対応する対称な関係に配置した構成としてあ
る。[Means for Solving the Problems] In order to achieve the above object, the double-sided mounting type memory package of the present invention includes a front side memory IC and a back side memory IC each having connection pins having the same function on the front and back sides of a printed circuit board. In a double-sided memory package with wires facing each other, the connection pins of the front side memory IC and the connection pins of the back side memory IC are arranged in a symmetrical relationship such that pins having the same function correspond to each other in the facing state. be.
【0009】[0009]
【作用】上記構成からなる両面実装型メモリパッケージ
によれば、表側メモリICおよび裏側メモリICを実装
すると、同一機能を有するピン同士が互いに対応するの
で、これらのピンをスルーホール等を介して一本の配線
パターンに接続することができる。[Operation] According to the double-sided mounting type memory package having the above configuration, when the front side memory IC and the back side memory IC are mounted, pins having the same function correspond to each other, so these pins can be connected together through a through hole or the like. Can be connected to the wiring pattern of the book.
【0010】0010
【実施例】以下、本発明の実施例について図面を参照し
て説明する。図1および図2は、本発明の実施例に係る
表側メモリIC1および裏側メモリIC2を示す平面図
、図3ないし図5は本発明の実施例に係る両面実装型メ
モリパッケージを示す平面図,横断面図および縦断面図
である。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are plan views showing a front side memory IC1 and a back side memory IC2 according to an embodiment of the present invention, and FIGS. 3 to 5 are plan views and cross-sectional views showing a double-sided mounting type memory package according to an embodiment of the present invention. They are a top view and a longitudinal cross-sectional view.
【0011】図1および図2において、表側メモリIC
1および裏側メモリIC2は、10本の接続ピンを左右
に突出させて形成されている。そして、表側メモリIC
1の接続ピン01〜10と裏側メモリIC2の接続ピン
01〜10とは、互いに向かい合せた状態で同一機能を
有するピン同士が互いに対応する対称な関係に配置され
ている。In FIGS. 1 and 2, the front side memory IC
1 and the back side memory IC 2 are formed with ten connection pins protruding left and right. And the front side memory IC
The connection pins 01 to 10 of the memory IC 1 and the connection pins 01 to 10 of the back side memory IC 2 are arranged in a symmetrical relationship such that pins having the same function correspond to each other while facing each other.
【0012】すなわち、実施例は、メモリIC1を従来
品とすると、これとピン対称型のメモリIC2を使用し
たものである。そして、図1および図2中01〜10で
示すメモリICピンは、同番号のピンは同機能(同じ制
御信号を意味する)を有するものである。That is, in this embodiment, assuming that the memory IC1 is a conventional product, a pin-symmetrical type memory IC2 is used. 1 and 2, pins with the same numbers have the same function (meaning the same control signal).
【0013】図2において、両面実装型メモリパッケー
ジは、プリント基板3に、メモリIC制御信号パターン
5を付設し、表裏面のパターンを接続するためのスルー
ホール6を有している。In FIG. 2, the double-sided mounting type memory package has a memory IC control signal pattern 5 attached to a printed circuit board 3, and a through hole 6 for connecting the patterns on the front and back sides.
【0014】そして、両面実装型メモリパッケージのプ
リント基板3の表面に、表側メモリIC1を実装し、他
方にピン対称型の裏側メモリIC2を実装する。符号4
は、メモリICの制御信号を効率よく配線するための引
き出し線である。[0014] Then, the front side memory IC1 is mounted on the front surface of the printed circuit board 3 of the double-sided mounting type memory package, and the pin-symmetric type back side memory IC2 is mounted on the other side. code 4
is a lead line for efficiently wiring control signals of the memory IC.
【0015】すなわち、本実施例では、表側メモリIC
1を従来品とすると、表面に従来のメモリIC1を実装
し、裏面にピン対称型メモリIC2を実装している関係
になる。That is, in this embodiment, the front side memory IC
1 is a conventional product, the conventional memory IC 1 is mounted on the front surface, and the pin symmetrical memory IC 2 is mounted on the back surface.
【0016】したがって、前記のように、メモリICを
表裏面に実装すると、メモリIC1,2の同機能のピン
はプリント基板3をはさみ全く同位置に配されることに
なり、スルーホール6一つで接続することが可能となる
。Therefore, as described above, when the memory ICs are mounted on the front and back sides, the pins with the same function of the memory ICs 1 and 2 are arranged at exactly the same position across the printed circuit board 3, and only one through hole 6 is provided. It is possible to connect with.
【0017】また、メモリIC制御信号パターン5の配
線においては、表裏面に実装されたメモリICの引き出
し線4をスルーホール6で接続し、このスルーホール6
をメモリIC制御信号パターン5に接続する。Furthermore, in the wiring of the memory IC control signal pattern 5, the lead wires 4 of the memory ICs mounted on the front and back surfaces are connected through a through hole 6.
is connected to memory IC control signal pattern 5.
【0018】メモリIC制御信号パターン5は、メモリ
ICの共通制御信号(アドレス,RAS,CAS,WE
等)の本数分だけ存在し、従来の技術のように、表裏面
各々パターンを配線していたのとは異なり、従来と比較
して配線効率は単純に2倍良くなる。Memory IC control signal pattern 5 includes memory IC common control signals (address, RAS, CAS, WE
etc.), and unlike the conventional technology in which patterns were wired on each of the front and back surfaces, the wiring efficiency is simply doubled compared to the conventional technology.
【0019】また、メモリIC制御信号パターン5を表
裏面のどちらかで配線しようとすると、スルーホール6
が2つ必要となるが本発明の手法を用いるとスルーホー
ル6も半減することができる。Furthermore, when attempting to wire the memory IC control signal pattern 5 on either the front or back side, the through hole 6
However, by using the method of the present invention, the number of through holes 6 can also be reduced by half.
【0020】[0020]
【発明の効果】以上説明したように本発明の両面実装型
メモリパッケージによれば、従来のメモリICと全く対
称なピン配置のメモリICを両面実装型メモリパッケー
ジの表裏面どちらかに実装させることになるので、一本
の配線パターンに表裏のメモリICの同一機能を有する
ピンを接続することができ、メモリICの共通制御信号
パターンの配線性を向上させることができるという効果
がある。[Effects of the Invention] As explained above, according to the double-sided memory package of the present invention, a memory IC having a pin arrangement completely symmetrical to that of a conventional memory IC can be mounted on either the front or back side of the double-sided memory package. Therefore, it is possible to connect pins having the same function of the front and back memory ICs to one wiring pattern, and there is an effect that the wiring performance of the common control signal pattern of the memory ICs can be improved.
【図1】本発明の実施例に係る両面実装型メモリパッケ
ージに使用する表側メモリICを示す平面図である。FIG. 1 is a plan view showing a front side memory IC used in a double-sided mount type memory package according to an embodiment of the present invention.
【図2】本発明の実施例に係る両面実装型メモリパッケ
ージに使用する裏側メモリICを示す平面図である。FIG. 2 is a plan view showing a back side memory IC used in a double-sided mount type memory package according to an embodiment of the present invention.
【図3】本発明の実施例に係る両面実装型メモリパッケ
ージを示す平面図である。FIG. 3 is a plan view showing a double-sided mounting type memory package according to an embodiment of the present invention.
【図4】本発明の実施例に係る両面実装型メモリパッケ
ージを示す横断面図である。FIG. 4 is a cross-sectional view showing a double-sided mounting type memory package according to an embodiment of the present invention.
【図5】本発明の実施例に係る両面実装型メモリパッケ
ージを示す縦断面図である。FIG. 5 is a vertical cross-sectional view showing a double-sided mounting type memory package according to an embodiment of the present invention.
【図6】従来の両面実装型メモリパッケージを示す平面
図である。FIG. 6 is a plan view showing a conventional double-sided mounting type memory package.
【図7】従来の両面実装型メモリパッケージの裏面の状
態を示す透視平面図である。FIG. 7 is a perspective plan view showing the back side of a conventional double-sided memory package.
1 表側メモリIC 2 裏側メモリIC 3 プリント基板 4 引き出し線 5 メモリIC制御信号パターン 6 スルーホール 1 Front side memory IC 2 Back side memory IC 3 Printed circuit board 4 Lead line 5 Memory IC control signal pattern 6 Through hole
Claims (1)
能を有する接続ピンを有した表側メモリICおよび裏側
メモリICをそれぞれ向かい合せて配線した両面実装型
メモリパッケージにおいて、表側メモリICの接続ピン
と裏側メモリICの接続ピンとを、上記向かい合わせた
状態で同一機能を有するピン同士が互いに対応する対称
な関係に配置したことを特徴とする両面実装型メモリパ
ッケージ。1. In a double-sided memory package in which a front side memory IC and a back side memory IC each having connection pins having the same function are wired facing each other on the front and back sides of a printed circuit board, the connection pins of the front side memory IC and the back side memory IC are wired facing each other. A double-sided mounting type memory package characterized in that connection pins of an IC are arranged in a symmetrical relationship such that pins having the same function correspond to each other when facing each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3126801A JPH04329692A (en) | 1991-04-30 | 1991-04-30 | Both side mounting type memory package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3126801A JPH04329692A (en) | 1991-04-30 | 1991-04-30 | Both side mounting type memory package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04329692A true JPH04329692A (en) | 1992-11-18 |
Family
ID=14944299
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3126801A Pending JPH04329692A (en) | 1991-04-30 | 1991-04-30 | Both side mounting type memory package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04329692A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5420756A (en) * | 1992-06-19 | 1995-05-30 | Kabushiki Kaisha Toshiba | Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern |
JP2006216956A (en) * | 2005-02-02 | 2006-08-17 | Samsung Electronics Co Ltd | Memory module with wiring structure |
-
1991
- 1991-04-30 JP JP3126801A patent/JPH04329692A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5420756A (en) * | 1992-06-19 | 1995-05-30 | Kabushiki Kaisha Toshiba | Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern |
JP2006216956A (en) * | 2005-02-02 | 2006-08-17 | Samsung Electronics Co Ltd | Memory module with wiring structure |
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