JPH0432952A - Interruption controller - Google Patents

Abstract

PURPOSE:To evade the frequent interruption of the operation of a processor by providing an interruption mask means, and monitoring the number of instruction which are altered every time an interruption signal is accepted and outputting an interruption signal to the processor when the number of instructions reaches a specific number. CONSTITUTION:An process informing means 20 provided to the processor 1 informs a processor 3 of a group of instructions required to complete a process and the number of the instructions in advance. The instruction buffer means 21 of the processor 3 is stored with the group of instructions. The interruption mask means 22 monitors the number of instructions which are subtracted every time, for example, the group of instructions is executed and outputs the interruption signal 104 to the processor 1 only when the number of the instructions becomes, for example, 0. Therefore, no interruption to the processor 1 is initiated until the group of the instructions is all executed. Consequently, the state wherein the processing of the processor 1 is interrupted by frequent interruption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interrupt control device that limits interrupts issued to a processor from a processing device that executes various types of processing.

(Prior Art) Information processing systems generally consist of a processor that performs overall control and management of the system, a keyboard and display, and various processing devices such as disk devices and printers. .

These various processing devices accept instructions from the processor and execute operations according to these instructions. Also, when the operation according to this instruction is completed, an interrupt is sent to the processor to notify the processor of this fact.Normally, the transfer of the instruction and the generation of the interrupt are executed by occupying the information transmission path each time. Furthermore, if a certain process is completed by executing a plurality of instructions, operations such as instruction transfer and interrupts will be repeated several times. The configuration of a computer system that controls such interrupts is herein referred to as an interrupt control device.

FIG. 2 shows an explanatory diagram of a conventional interrupt control device.

In the figure, a processing device 3 is connected to a processor 1 via an information transmission line (pass line) 2 and transmission lines 2a and 2b.

The processor 1 controls and manages the processing device 3. Information transmission path 2 and transmission path 2a.

2b is a signal line that transmits various control information, data, and the like. The processing device 3 executes predetermined processing under the control of the processor 1, such as writing and reading in the case of a disk device.

The processing device 3 includes a device control section 5 that controls the operation of the processing device 3, a processing mechanism 6 that executes various processes under the control of the device control section 5, and an interrupt control section that controls the generation of interrupts to the processor 1. Mask means 7 are provided. The interrupt masking means 7 is provided with a flip-flop 8 and an AND gate 9. The processor 1 and the processing device 3 are connected to the information transmission path 2 via transmission paths 2a and 2b, respectively.

In the processing device 3, the device control unit 5 controls the processing mechanism 6.
A processing control signal 101 is outputted to the interrupt masking means 7, and an interrupt control signal 102 is outputted to the interrupt masking means 7. From the processing mechanism 6, the flip-flop 8 of the interrupt masking means 7
An interrupt signal 103 is output to the set (S) terminal of. Further, the output of the output (Q) terminal of the flip-flop 8 is inputted to one input terminal of an AND gate 9, and furthermore, an interrupt signal 104 is outputted from the output terminal of the AND gate 9 toward the information transmission path 2. Note that this interrupt signal 104 is actually output to the information transmission line 2 via the transmission line 2b. A reset signal RST and a mask signal MS based on the mask control signal 102 are input to the reset (R) terminal of the flip-flop 8 and the other input terminal of the AND gate 9, respectively. A control signal 105 is transmitted between the device control section 5 and the information transmission path 2. This control signal 105 is actually transmitted via the transmission line 2b. Further, a data line 106 for transmitting various data is provided between the transmission N2b and the processing mechanism 6.

The processing control signal 101 consists of various control information for the device control section 5 to control the processing mechanism 6, and includes, for example, various instruction codes and parameters. The interrupt control signal 102 includes a reset signal RST for resetting the flip-flop 8, a mask signal MS for limiting (masking) the output of an interrupt signal when the processor 1 is in a state where it cannot accept an interrupt, and the like. The 0 interrupt signal 103, which is a signal, is a signal for notifying the processor l of the completion when the processing mechanism 6 executes an instruction based on the processing control signal 101. The interrupt signal 104 is held at the AND gate 9 and is output to the AND gate 9. The interrupt signal 104 corresponds to the interrupt signal 103 output from the AND gate 9 when the mask signal MS is invalid (high level).

Here, taking the case where the processing device 3 is a disk device as an example,
The operation of each part will be explained with reference to FIG.

FIG. 3 is an explanatory diagram of the conventional operation.

It is assumed that the processor 1 is in a state where it can accept interrupts at any time. Therefore, the device control unit 5
It is assumed that an interrupt control signal 102 for setting the mask signal MS to an invalid state and resetting the flip-flop 8 by the reset signal R3T is outputted in advance under the control of .

Now, when a processing request for executing processing using the processing device 3 is issued to the processor 1 (for example, read processing of a disk device), the processor 1 outputs a group of instructions to the processing device 3.

In this case, the processor 1 first asks the processing device 3 whether or not the file to be read exists on the storage medium in the processing device 3, and if so, its storage location (
Issue a search command (seek command) to search the physical area).

When the execution of this instruction is completed, the processor 1 issues a physical area notification instruction to notify the physical area grasped as a result of this seek instruction. Next, a read command is issued to instruct successive access to the notified physical area. Then, processing such as issuing a file content notification command to notify the processor 1 of the contents of the read file is sequentially performed.

These commands are notified to the device control unit 5 as a control signal 105 (step Sl). Device control unit 5 that received the notification
processes various commands obtained by analyzing the control signal 10
1 and is notified to the processing mechanism 6. The processing mechanism 6 executes processing corresponding to various commands indicated by the processing control signal 101 (step S2). When the processing is completed, the processing mechanism 6 outputs an interrupt signal 103 (step S3). This interrupt signal 103 causes the output of the output terminal Q to go high and is input to the AND gate. In ANDGATE 9,
The interrupt signal 104 is output because the mask signal MS is in an invalid state, that is, at a high level.
The information is supplied to the processor 1 via the information transmission path 2. When processor l accepts this interrupt (step S4)
, executes interrupt processing such as analyzing the reason for the interrupt, and when this analysis is completed, outputs a control signal etc. to generate an interrupt control signal 102 for resetting the flip-flop 8 (step S5). Then, the next instruction (instruction 2) in the group of instructions is output (step S
6). Thereafter, steps S7 to Sll are similarly executed, and when the last instruction (instruction n) of the group of instructions is processed (step 512), steps S13 to S15 are executed, and the processor 1 executes the instructions to be executed. It recognizes that there are no more commands and terminates the process.

(Problem to be Solved by the Invention) As described above, the conventional processing device 3 accepts an interrupt each time each instruction constituting a group of instructions is executed, and then executes the next instruction. The process of notifying the command to be executed will be repeated.

Therefore, when the processor 1 is executing a process other than the processing device 3, the process is frequently interrupted, resulting in a decrease in the operating efficiency of the processor 1. Further, the processing device 3 also interrupts the processor 1 every time it executes one instruction and causes the processor 1 to analyze the reason for the interrupt, which causes the problem that a new instruction cannot be executed promptly.

The present invention has been made with attention to the above points, and is an interrupt control device that avoids situations where the operation of a processor is frequently interrupted, and further allows a processing device to quickly complete execution of a group of instructions. The purpose is to provide the following.

(Means for Solving the Problems) An interrupt control device of the present invention includes a processor and a processing device that is connected to the processor via an information transmission path and executes predetermined processing under the control of the processor. In the processor, the processor includes processing notification means for notifying the processing device of a group of instructions and the number of instructions for executing the predetermined processing, and the processing device is configured to receive the group of instructions notified from the processor. instruction buffer means for accumulating instructions, a processing mechanism for reading and executing the instructions from the previous E-instruction buffer means, and interrupt masking means for accepting an interrupt signal outputted each time the processing mechanism executes one instruction. The interrupt masking means monitors the number of instructions, which is changed every time the interrupt signal is accepted, and outputs the interrupt signal to the processor when the number of instructions reaches a predetermined number.

(Operation) This device notifies the processing device in advance of a group of commands and the number of commands required to complete the processing by means of a processing notification means provided in the processor. The instruction buffer means 21 of the processing device stores a group of instructions. On the other hand, the interrupt masking means monitors the number of instructions subtracted each time a group of instructions is executed, and outputs an interrupt signal to the processor only when the number of instructions becomes O, for example. This reduces the situation where an interrupt signal is output from the processing mechanism to the processor each time each instruction of a group of instructions is completed.

(Example) FIG. 1 shows an explanatory diagram of an interrupt control device of the present invention.

In the figure, a processor 1 is connected to a processing device 3 via an information transmission line (path line) 2 and transmission lines 2a and 2b.

The processor 1 controls and manages the processing device 3. The information transmission path 2 is a signal line that transmits various control information, data, and the like. The processing device 3 executes predetermined processing under the control of the processor 1, such as writing and reading in the case of a disk device.

The processor 1 is provided with a process notification means 20 that notifies the processing device 3 of a group of instructions and the number of instructions necessary for completing a certain process.

The processing device 3 stores a device control section 5 that controls the operation of the processing device 3, a processing mechanism 6 that executes various processes under the control of the device control section 5, and a group of instructions notified from the processor 1. , an instruction buffer means 21 for outputting to the sequential processing mechanism 6, and an interrupt masking means 22 for controlling the generation of interrupts to the processor 1.

The instruction buffer means 21 is provided with a buffer memory 31 and a buffer control section 32. The buffer memory 31 is composed of a FIFO-format RAM or the like that individually stores a group of instructions notified from the processor 1. The buffer control unit 32 controls writing and reading of the buffer memory 31 via the memory control line MC.

The interrupt masking means 22 is provided with a flip-flop 8, AND gates 9 and 35, and an instruction number counter 36. The instruction number counter 36 is made up of a storage device that stores the number of instructions notified from the processor 1.

In the processing device 3, the device control section 5 outputs a processing control signal 101 to the buffer control section 32 of the instruction buffer means 21, and an interrupt control signal 102 to the interrupt masking means 22.

A processing control signal 101a is transmitted between the buffer control unit 32 and the processing mechanism 6. Also, buffer memory 3
A command signal 200 is transmitted from the processor 1 to the processing mechanism 6. From the processing mechanism 6 to the buffer control unit 32, the instruction counter 36, and one input of the AND gate,
An interrupt signal 103 is being output. instruction counter 36
A count signal O8 is outputted from the gate to the other input of the AND gate 35 and the buffer control section 32. The output signal of the AND gate 35 is input to the S terminal of the flip-flop 8. The output signal of the Q terminal of the flip-flop 8 is input to one input terminal of the AND gate 9. An interrupt signal 104 is output from the output terminal of the AND gate 9. The R terminal of the flip-flop 8 and the other input terminal of the AND gate 9 each receive a mask control signal 1.
Reset signal RST and mask signal M based on 02
S is input.

The processing control signal 101a is a signal by which the buffer control unit 32 controls the processing mechanism 6 based on the processing control signal 101. Command signal 200 consists of a command code read from buffer memory 31. Count signal O8
is a signal that becomes valid (high level) when the content of the instruction counter 36 becomes O. In addition, transmission line 2b
A data line 201 for transmitting various data is provided between the buffer memory 31 and the instruction counter 36.

The operation of the interrupt control device having the above configuration will be explained with reference to FIG.

FIG. 4 is an explanatory diagram of the operation according to the present invention.

It is assumed that the processor 1 is in a state where it can accept interrupts at any time. Therefore, the device control unit 5
It is assumed that an interrupt control signal 102 for setting the invalid state of the mask signal MS and resetting the flip-flop 8 by the reset signal RST is outputted in advance under the control of . It is also assumed that the buffer memory 31 and the instruction counter 36 have also been initialized.

Now, when a processing request for executing processing using the processing device 3 is issued to the processor 1 (for example, read processing of a disk device), the processor 1 outputs a group of instructions to the processing device 3.

In this case, the processing notification means 20 of the processor 1 outputs a control signal 105 to notify the device control unit 5 of a group of instructions and the number of instructions. As a result, the number of instructions is stored in the instruction counter 36 via the data line 201 (step S1), and a group of instructions (n instructions) is stored in the buffer memory 31 (steps 83 to S8).

On the other hand, upon receiving the notification from the processor 1, the device control section 5 outputs a processing control signal 101 to the buffer control section 32. The buffer control unit 32 outputs a processing control signal 101a to the processing mechanism 6 to start the processing mechanism 6,
The buffer memory 31 is read out. in this case,
First, instruction 1 is read and process 1 is executed (step S9). Note that the buffer control unit 32 shifts the contents of the buffer memory 31 when the contents of the buffer memory 31 are read. That is, instruction 2 is stored in the area where instruction 1 has been stored up to now, and instruction 3 is stored in the area where instruction 2 has been stored. When processing 1 is completed, processing mechanism 6 outputs interrupt signal 103 (step 510). The instruction counter 36 that accepted this interrupt signal
changes the number of instructions (subtraction in this case), determines whether the content is a predetermined number (“0” in this case), and returns 0.
If not, the count signal O8 is invalidated and output (step 511). Further, when the interrupt signal 103 is input, the buffer control unit 32 grasps the state of the count signal O8, and if it is in an invalid state, outputs the processing control signal 101a again (Step 512), and gives the processing mechanism 6 the command 2 ( Process 2) is executed (step 513).

Thereafter, steps S14 to S18 are similarly executed.

Now, when a group of n instructions is completed and an end interrupt occurs in step S18, the content of the instruction counter 36 becomes O. Therefore, the instruction counter 36 sets the count signal C8 to valid and outputs it. As a result, the output terminal of the AND gate 35 becomes high level, and the Q terminal of the flip-flop 8 becomes high level. Therefore, an interrupt signal 104 is output from the output terminal of the AND gate 9 and is notified to the processor 1. When the processor 1 receives the interrupt signal (step 520), the processor 1 accesses the processing device 3, recognizes that there are no more instructions to be executed, that is, the group of instructions has been completed, and ends the process.

As described above, the processing mechanism 6 outputs the interrupt signal 103 each time the execution of an individual instruction among a group of instructions is completed, but if a group of instructions remains to be executed, the interrupt masking means 22, that is, the interrupt signal 103 is masked by the count signal C8 output from the instruction counter 36,
The interrupt signal 104 is prevented from being output to the processor 1.

The present invention is not limited to the above embodiments.

In the embodiment, the processing device 3 has been described using a disk device as an example, and the case of read processing as an example. However, the processing device 3 is not limited to the read processing of a disk device, and may be used, for example, in the case of printing processing of a printer, etc. can perform similar processing. Further, the instruction counter 36 does not necessarily need to be provided in the interrupt masking means 22; for example, a predetermined area of the buffer memory 31 can be used to store the number of instructions, and this number of instructions can be changed at the timing when the interrupt signal 103 is output. It's okay.

(Effects of the Invention) The interrupt control device described above receives a group of instructions and the number of instructions from the processing device, and an interrupt to the processor does not occur until all of the instructions in the group are executed.
The processor can reduce the occurrence of interruptions in processing due to frequent interruptions. Therefore, it is possible to avoid a situation where the operating efficiency of the processor decreases.

Furthermore, since the processing device does not need to receive notification of a new instruction from the processor each time it executes one instruction, it can quickly complete a group of instructions.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the interrupt control device according to the present invention, FIG. 2 is an explanatory diagram of the conventional interrupt control device, FIG. 3 is an explanatory diagram of the conventional operation, and FIG. 4 is an explanatory diagram of the operation according to the present invention. be. 1... Processor, 3... Processing device, 6... Processing mechanism, 20... Processing notification means, 21... Instruction bar sofa means, 22... Interrupt masking means. Prosensor side Prosensor side 4 all karan l Bacifer memory and mechanical mechanism

Claims (1)

[Scope of Claims] A device comprising: a processor; and a processing device that is connected to the processor via an information transmission path and executes a predetermined process under the control of the processor, wherein the processor has the following functions for the processing device: processing notification means for notifying a group of instructions and the number of instructions for executing the predetermined process, the processing device comprising: an instruction buffer means for accumulating the group of instructions notified from the processor; A processing mechanism for reading and executing an instruction from the instruction buffer means; and an interrupt masking means for accepting an interrupt signal outputted each time the processing mechanism executes one instruction; An interrupt control device that monitors the number of instructions, which is changed each time the instruction is accepted, and outputs the interrupt signal to the processor when the number of instructions reaches a predetermined number.